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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
1,690 Commits 3 Branches 10 Tags 86 MiB
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stefan schippers 52f35e30c2 avoid video updating when loading multiple files in hierarchical ps/pdf export 2023-04-27 08:49:52 +02:00
XSchemWin Correct menu accelerator shown for "merge" function (b key) 2023-04-11 09:33:25 +02:00
doc update documentation (symbol generators), add missing images 2023-04-23 11:06:08 +02:00
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xschem_library allow tcl procedures to generate generator script and parameters, update vhdl and verilog netlisters to handle generator schematic/symbol references 2023-04-26 09:54:35 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions