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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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stefan schippers 501fb7943f removed completely menu View->Show/hide->Show net names on symbol pins 2024-05-02 14:41:15 +02:00
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin drc_check(): if no fet_drc procedure found do nothing 2024-04-25 09:13:23 +02:00
doc add @#pin:spice_get_voltage attribute for pin texts that displays voltage of net attached to pin. remove net_name=... attributes from symbols and instance global attributes since it is no more used. set default value for show_pin_net_names to 1. 2024-05-02 10:32:12 +02:00
scconfig add missing scconfig/src/tty/ dir 2024-05-02 10:33:10 +02:00
src removed completely menu View->Show/hide->Show net names on symbol pins 2024-05-02 14:41:15 +02:00
tests update LCC_instances.sch (3) 2024-04-01 04:06:11 +02:00
xschem_library add @#pin:spice_get_voltage attribute for pin texts that displays voltage of net attached to pin. remove net_name=... attributes from symbols and instance global attributes since it is no more used. set default value for show_pin_net_names to 1. 2024-05-02 10:32:12 +02:00
.gitignore gitignore update 2023-01-16 13:41:16 -07:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
CMakeLists.txt Added png and embedded graphs to ps and pdf export 2023-01-15 21:34:43 -07:00
Changelog update Changelog for 3.4.4 2023-10-05 08:06:47 +02:00
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Makefile added install_pdf to create pdf doc from html man pages 2023-07-03 11:38:09 +02:00
Makefile.conf.in config.h: generate HAS_LIBREADLINE, do not add #include line for libreadline (yet) as this is wip 2024-05-01 11:53:54 +02:00
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README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in config.h: generate HAS_LIBREADLINE, do not add #include line for libreadline (yet) as this is wip 2024-05-01 11:53:54 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions