update LCC_instances.sch (3)
This commit is contained in:
stefan schippers
parent
cd46bad8d2
commit
48b1f8eb31
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@ -199,7 +199,7 @@ proc netlist_test {} {
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loading.sch vhdl 2975204502
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mos_power_ampli.sch spice 3405708328
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hierarchical_tedax.sch tedax 998070173
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LCC_instances.sch spice 1888015492
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LCC_instances.sch spice 372367338
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pcb_test1.sch tedax 1925087189
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test_doublepin.sch spice 4159808692
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simulate_ff.sch spice 574849766
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@ -27,13 +27,13 @@ V {}
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S {
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}
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E {}
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L 4 210 -300 230 -320 {}
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L 4 210 -300 250 -300 {}
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L 4 230 -320 250 -300 {}
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L 4 230 -220 250 -240 {}
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L 4 210 -240 250 -240 {}
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L 4 210 -240 230 -220 {}
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L 4 230 -300 230 -240 {}
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L 4 220 -310 240 -330 {}
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L 4 220 -310 260 -310 {}
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L 4 240 -330 260 -310 {}
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L 4 240 -230 260 -250 {}
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L 4 220 -250 260 -250 {}
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L 4 220 -250 240 -230 {}
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L 4 240 -310 240 -250 {}
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L 4 350 -580 370 -560 {dash=3}
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L 4 370 -600 370 -560 {dash=3}
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L 4 350 -580 370 -600 {dash=3}
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@ -42,41 +42,86 @@ L 4 1420 -730 1440 -750 {dash=3}
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L 4 1420 -770 1420 -730 {dash=3}
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L 4 1420 -770 1440 -750 {dash=3}
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L 4 1350 -750 1420 -750 {dash=3}
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B 2 790 -490 1410 -260 {flags=graph,unlocked
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y1 = 0
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y2 = 3
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divy = 6
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x1=0
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x2=3
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divx=6
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node="a
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zz%0
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zz%1
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zzz
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xkeeper.y
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xkeeper.y%1"
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color="8 6 12 7 9 10"
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sweep="v(a)"
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dataset=0
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hilight_wave=2}
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B 2 10 -1080 340 -730 {flags=graph,unlocked
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y1 = 0
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y2 = 3
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divy = 6
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x1=0
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x1=2.7755576e-17
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x2=3
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divx=6
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node="a z"
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color="7 6"
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sweep="z a"
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}
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rawfile=$netlist_dir/LCC_instances.raw
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sim_type=dc
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dataset=0}
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B 2 850 -270 1150 -60 {flags=graph
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y1=0
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y2=3
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ypos1=0
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ypos2=2
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divy=5
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subdivy=1
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unity=1
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x1=0
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x2=3
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divx=5
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subdivx=1
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xlabmag=1.0
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ylabmag=1.0
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dataset=0
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unitx=1
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logx=0
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logy=0
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rainbow=0
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sweep=a
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color="7 8 6"
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node="zz%0
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zz%1
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a%0"
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rawfile=$netlist_dir/LCC_instances.raw
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sim_type=tran
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hilight_wave=-1}
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B 2 850 -480 1150 -270 {flags=graph
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y1=0
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y2=3
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ypos1=0
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ypos2=2
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divy=5
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subdivy=1
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unity=1
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x1=0
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x2=3
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divx=5
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subdivx=1
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xlabmag=1.0
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ylabmag=1.0
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dataset=0
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unitx=1
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logx=0
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logy=0
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rainbow=0
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sweep=a
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color="7 8 6"
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node="zz%0
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zz%1
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a%0"
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rawfile=$netlist_dir/LCC_instances.raw
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sim_type=dc
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hilight_wave=-1}
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B 8 255 -871.25 295 -831.25 {}
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B 8 113.75 -1002.5 153.75 -962.5 {}
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P 4 5 560 -700 560 -510 1350 -510 1350 -700 560 -700 {dash=3}
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P 4 5 820 -920 820 -730 1350 -730 1350 -920 820 -920 {dash=3}
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P 4 5 0 -1160 1840 -1160 1840 0 -0 0 0 -1160 {dash=4}
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P 4 5 0 -1160 1960 -1160 1960 0 -0 0 0 -1160 {dash=4}
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T {These 2 instances
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are equivalent} 260 -310 0 0 0.4 0.4 {}
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are equivalent} 270 -320 0 0 0.4 0.4 {}
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T {Example of using a schematic as a component instance
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instead of the usual symbol. LCC: Local Custom Cell.
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@ -90,19 +135,18 @@ and use arrow keys to zoom / pan waveforms} 10 -1150 0 0 0.3 0.3 {}
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T {Butterfly diagram
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of a sram cell} 460 -980 0 0 0.4 0.4 {layer=8}
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T {@symname
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@name} 1840 -1250 0 1 0.7 0.7 {}
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N 410 -100 410 -80 {lab=HALF}
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N 410 -190 430 -190 {lab=ZZZ}
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N 410 -190 410 -160 {lab=ZZZ}
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N 420 -400 420 -380 {lab=HALF}
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N 420 -490 740 -490 {lab=ZZ}
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N 420 -490 420 -460 {lab=ZZ}
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N 740 -240 1450 -240 {lab=#net1}
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N 320 -190 410 -190 {lab=ZZZ}
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N 330 -490 420 -490 {lab=ZZ}
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N 740 -320 740 -240 {
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@name} 1960 -1250 0 1 0.7 0.7 {}
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T {DC} 1160 -300 0 0 0.4 0.4 {}
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T {TRAN} 1160 -90 0 0 0.4 0.4 {}
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N 340 -90 340 -70 {lab=HALF}
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N 380 -190 400 -190 {lab=ZZZ}
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N 1240 -380 1240 -360 {lab=HALF}
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N 420 -490 1350 -490 {lab=ZZ}
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N 1350 -240 1450 -240 {lab=#net1}
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N 290 -190 380 -190 {lab=ZZZ}
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N 1350 -320 1350 -240 {
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lab=#net1}
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N 740 -490 740 -380 {
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N 1350 -490 1350 -380 {
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lab=ZZ}
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N 50 -280 50 -270 {
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lab=VDD}
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@ -113,34 +157,49 @@ lab=HALF}
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N 660 -860 680 -860 {lab=VDD}
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N 550 -860 600 -860 {
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lab=Z}
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N 570 -890 570 -860 {
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N 570 -910 570 -860 {
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lab=Z}
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N 630 -820 680 -820 {
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lab=VDD}
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N 680 -860 680 -820 {
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lab=VDD}
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C {vsource.sym} 50 -110 0 0 {name=V1 value="dc 0 pwl 0 0 1u 0 5u 3"
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savecurrent=1}
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N 60 -490 110 -490 {
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lab=A}
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N 150 -190 210 -190 {
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lab=A}
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N 1240 -460 1240 -440 {
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lab=#net2}
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N 340 -170 340 -150 {
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lab=#net3}
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N 410 -860 470 -860 {
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lab=A}
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C {vsource.sym} 50 -110 0 0 {name=V1 value="pwl 0 0 10u 3"
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savecurrent=1
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}
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C {lab_pin.sym} 50 -180 0 0 {name=p4 lab=A}
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C {lab_pin.sym} 50 -80 0 0 {name=p5 lab=0}
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C {code_shown.sym} 470 -340 0 0 {name=STIMULI
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C {code_shown.sym} 510 -450 0 0 {name=STIMULI
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only_toplevel=true
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tclcommand="xschem edit_vi_prop"
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value="* .ic v(L) = 3 v(R)=0
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value="* .options SRCSTEPS=0
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.control
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save all
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dc v1 0 3 0.001
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* tran 10n 10u uic
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write LCC_instances.raw
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set appendwrite
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dc v1 3 0 -0.001
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write LCC_instances.raw
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op
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write LCC_instances.raw
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tran 10n 10u uic
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write LCC_instances.raw
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alter V1 pwl = [ 0 3 10u 0 ]
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tran 10n 10u uic
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write LCC_instances.raw
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* quit 0
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.endc
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"}
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C {code.sym} 840 -190 0 0 {name=MODEL
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C {code.sym} 1260 -170 0 0 {name=MODEL
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only_toplevel="true"
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tclcommand="xschem edit_vi_prop"
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value="************************************************
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@ -194,45 +253,56 @@ value="************************************************
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+WD = 0.0 )
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"}
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C {lab_pin.sym} 240 -190 0 0 {name=p6 lab=A}
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C {lab_pin.sym} 430 -190 0 1 {name=p7 lab=ZZZ}
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C {lab_pin.sym} 150 -190 0 0 {name=p6 lab=A}
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C {lab_pin.sym} 400 -190 0 1 {name=p7 lab=ZZZ}
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C {vsource.sym} 50 -240 0 0 {name=V2 value=3
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savecurrent=1}
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C {lab_pin.sym} 50 -210 0 0 {name=p9 lab=0}
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C {res.sym} 410 -130 0 0 {name=R1
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C {res.sym} 340 -120 0 0 {name=R1
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value=80k
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footprint=1206
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device=resistor
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m=1}
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C {lab_pin.sym} 410 -80 0 0 {name=p10 lab=HALF}
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C {lab_pin.sym} 340 -70 0 0 {name=p10 lab=HALF}
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C {vsource.sym} 50 -370 0 0 {name=V3 value=1.5
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savecurrent=1}
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C {lab_pin.sym} 50 -420 0 0 {name=p11 lab=HALF}
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C {lab_pin.sym} 50 -340 0 0 {name=p12 lab=0}
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C {lab_pin.sym} 120 -490 0 0 {name=p13 lab=A}
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C {res.sym} 420 -430 0 0 {name=R2
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C {lab_pin.sym} 60 -490 0 0 {name=p13 lab=A}
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C {res.sym} 1240 -410 0 0 {name=R2
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value=80k
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footprint=1206
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device=resistor
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m=1}
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C {lab_pin.sym} 420 -380 0 0 {name=p15 lab=HALF}
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C {lab_pin.sym} 1240 -360 0 0 {name=p15 lab=HALF}
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C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
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C {cmos_inv.sch} 60 -260 0 0 {name=Xinv WN=15u WP=45u LLN=3u LLP=3u}
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C {cmos_inv.sym} 280 -190 0 0 {name=Xinv2 WN=15u WP=45u LLN=3u LLP=3u}
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C {bus_keeper.sch} 1200 60 0 0 {name=Xkeeper WN_FB=6u WP_FB=12u}
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C {lab_pin.sym} 740 -490 0 1 {name=p1 lab=ZZ}
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C {lab_pin.sym} 470 -860 0 0 {name=p14 lab=A}
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C {lab_pin.sym} 570 -890 0 1 {name=p2 lab=Z}
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C {cmos_inv.sch} 50 -260 0 0 {name=Xinv WN=15u WP=45u LLN=3u LLP=3u}
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C {cmos_inv.sym} 250 -190 0 0 {name=Xinv2 WN=15u WP=45u LLN=3u LLP=3u}
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C {bus_keeper.sch} 1290 60 0 0 {name=Xkeeper WN_FB=6u WP_FB=12u}
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C {lab_pin.sym} 1350 -490 0 1 {name=p1 lab=ZZ}
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C {lab_pin.sym} 410 -860 0 0 {name=p14 lab=A}
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C {lab_pin.sym} 570 -910 0 1 {name=p2 lab=Z}
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C {cmos_inv.sym} 510 -860 0 0 {name=Xinv1 WN=1u WP=1u LLN=2u LLP=2u}
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C {launcher.sym} 655 -1115 0 0 {name=h1
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descr="Select arrow and
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Ctrl-Left-Click to load/unload waveforms"
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descr="load DC sim"
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tclcommand="
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xschem raw_read $netlist_dir/[file tail [file rootname [xschem get current_name]]].raw
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xschem raw_read $netlist_dir/[file tail [file rootname [xschem get current_name]]].raw dc
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"
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}
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C {ammeter.sym} 740 -350 0 1 {name=Vmeas}
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C {ammeter.sym} 1350 -350 0 1 {name=Vmeas}
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C {vdd.sym} 50 -280 0 0 {name=l2 lab=VDD}
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C {nmos4.sym} 630 -840 3 0 {name=M1 model=n w=1u l=2u m=1 net_name=true}
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C {lab_pin.sym} 630 -860 3 1 {name=l4 sig_type=std_logic lab=0}
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C {vdd.sym} 680 -860 0 0 {name=l3 lab=VDD}
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C {launcher.sym} 655 -1045 0 0 {name=h2
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descr="Annotate OP"
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tclcommand="
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xschem annotate_op
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"
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}
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C {launcher.sym} 885 -1115 0 0 {name=h3
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descr="load tran sim"
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tclcommand="
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xschem raw_read $netlist_dir/[file tail [file rootname [xschem get current_name]]].raw tran
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"
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}
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@ -1,4 +1,4 @@
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v {xschem version=3.4.4 file_version=1.2
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v {xschem version=3.4.5 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -26,19 +26,25 @@ template="name=X1 WN_FB=1u WP_FB=2u"}
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V {}
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S {}
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E {}
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P 2 5 250 -930 250 -120 610 -120 610 -930 250 -930 {dash=5}
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P 2 5 160 -930 160 -120 610 -120 610 -930 160 -930 {dash=5}
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T {@name} 250 -965 0 0 0.5 0.5 {}
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T {@symname} 253.75 -115 0 0 0.5 0.5 {}
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N 250 -300 300 -300 {lab=A}
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N 280 -690 300 -690 {lab=A}
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N 280 -690 280 -300 {lab=A}
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N 510 -300 550 -300 {lab=Y}
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N 190 -690 190 -300 {lab=A}
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N 550 -690 550 -300 {lab=Y}
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N 510 -690 550 -690 {lab=Y}
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N 550 -240 550 -200 { lab=GND}
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C {cmos_inv.sch} 240 -70 0 0 {name=X2 WN=15u WP=45u LLN=3u LLP=3u}
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C {cmos_inv.sch} 570 -460 0 1 {name=X1 WN=WN_FB WP=WP_FB LLN=3u LLP=3u}
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C {iopin.sym} 250 -300 0 1 {name=p1 lab=A}
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N 550 -240 550 -200 { lab=0}
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N 190 -300 210 -300 {
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lab=A}
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N 520 -300 550 -300 {
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lab=Y}
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N 520 -690 550 -690 {
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lab=Y}
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N 190 -690 210 -690 {
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lab=A}
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N 160 -300 190 -300 {
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lab=A}
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C {cmos_inv.sch} 150 -70 0 0 {name=X2 WN=15u WP=45u LLN=3u LLP=3u}
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C {cmos_inv.sch} 580 -460 0 1 {name=X1 WN=WN_FB WP=WP_FB LLN=3u LLP=3u}
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C {iopin.sym} 160 -300 0 1 {name=p1 lab=A}
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C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
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C {capa.sym} 550 -270 0 0 {name=C1
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m=1
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@ -1,4 +1,4 @@
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v {xschem version=3.4.4 file_version=1.2
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v {xschem version=3.4.5 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -29,15 +29,13 @@ V {}
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S {}
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E {}
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A 15 90 -410 14.14213562373095 135 360 {dash=2}
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P 2 5 60 -450 270 -450 270 -90 60 -90 60 -450 {dash=5}
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P 2 5 60 -450 370 -450 370 -90 60 -90 60 -450 {dash=5}
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T {@name} 60 -465 0 0 0.2 0.2 {}
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T {@symname} 63.75 -85 0 0 0.2 0.2 {}
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N 80 -350 80 -170 {lab=A}
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N 80 -230 80 -170 {lab=A}
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N 60 -230 80 -230 {lab=A}
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N 140 -400 140 -380 {lab=VDD}
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N 140 -140 140 -120 {lab=0}
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N 240 -230 270 -230 {
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lab=Z}
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N 140 -230 180 -230 {
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lab=D}
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N 140 -320 140 -290 {
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@ -48,20 +46,30 @@ N 80 -350 100 -350 {
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lab=A}
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N 80 -170 100 -170 {
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lab=A}
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C {opin.sym} 270 -230 0 0 {name=p2 lab=Z}
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N 330 -230 370 -230 {
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lab=Z}
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N 240 -230 270 -230 {
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lab=#net2}
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N 140 -350 200 -350 {
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lab=VDD}
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N 140 -170 200 -170 {
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lab=0}
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N 80 -350 80 -230 {lab=A}
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C {opin.sym} 370 -230 0 0 {name=p2 lab=Z}
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C {ipin.sym} 60 -230 0 0 {name=p1 lab=A goto=0}
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C {vdd.sym} 140 -400 0 0 {name=l1 lab=VDD}
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C {lab_pin.sym} 140 -120 0 0 {name=l2 sig_type=std_logic lab=0}
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C {pmos4.sym} 120 -350 0 0 {name=M2 model=p w=WP l=LLP m=1 net_name=true}
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C {nmos4.sym} 120 -170 0 0 {name=M1 model=n w=WN l=LLN m=1 net_name=true}
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C {lab_pin.sym} 140 -170 0 1 {name=l3 sig_type=std_logic lab=0}
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C {lab_pin.sym} 140 -350 0 1 {name=l4 sig_type=std_logic lab=VDD}
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C {lab_pin.sym} 200 -170 0 1 {name=l3 sig_type=std_logic lab=0}
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C {lab_pin.sym} 200 -350 0 1 {name=l4 sig_type=std_logic lab=VDD}
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C {title.sym} 160 -30 0 0 {name=l5 author="Stefan Schippers"}
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C {res.sym} 210 -230 1 0 {name=R1
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value=1k
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value=10
|
||||
footprint=1206
|
||||
device=resistor
|
||||
m=1}
|
||||
C {lab_pin.sym} 140 -220 0 1 {name=l6 sig_type=std_logic lab=D}
|
||||
C {lab_pin.sym} 80 -320 0 1 {name=l7 sig_type=std_logic lab=A}
|
||||
C {ammeter.sym} 140 -260 0 0 {name=V1}
|
||||
C {ammeter.sym} 300 -230 3 0 {name=Vmeas savecurrent=true}
|
||||
|
|
|
|||
Loading…
Reference in New Issue