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0_pcb_top.sch
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allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example
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2020-11-24 02:54:45 +01:00 |
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74ls00-2.sym
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preserve backslashes in instance name after doing an editprop(). get_tok_value() fix: do not eat "\" if called with with_quotes=1
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2020-12-01 12:00:18 +01:00 |
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74ls00.sym
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minor doc/man updates, typo cleanups
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2023-09-19 23:59:01 +02:00 |
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7805.sym
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minor doc/man updates, typo cleanups
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2023-09-19 23:59:01 +02:00 |
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bc817.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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hierarchical_tedax.sch
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allow ! in net names, it got deleted after the parselabel rework.
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2020-12-13 20:26:39 +01:00 |
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hierarchical_tedax.sym
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allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example
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2020-11-24 02:54:45 +01:00 |
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lm358.sym
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removed weird names (spaces etc) in hierarchical_tedax schematic objects. that was used for testing the hiertEDAx export.
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2020-11-24 19:55:45 +01:00 |
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pcb_current_protection.sch
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test schematics update
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2022-10-21 11:28:17 +02:00 |
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pcb_current_protection.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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pcb_current_protection_embed.sch
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test schematics update
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2022-10-21 11:28:17 +02:00 |
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pcb_test1.sch
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revert a change in example schematic pcb_test1.sch so xschemtest will not report a false error
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2023-09-20 12:35:26 +02:00 |
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pcb_test1.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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pcb_test1_embed.sch
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fix pcb_current_protection_embed.sch with up to date embedded symbols (previous had very old symbols with errors), fix pmos.sym (make pin names and verilog_format string consistent). All other schematics with embedded symbols updated with current library symbol. Some code in place for saving/restoring symbols in in-memory undo. This code is not compiled so does not affect xschem operation at all.
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2021-11-25 04:00:01 +01:00 |
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pcb_test2.sch
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preserve backslashes in instance name after doing an editprop(). get_tok_value() fix: do not eat "\" if called with with_quotes=1
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2020-12-01 12:00:18 +01:00 |
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pcb_voltage_protection.sch
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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pcb_voltage_protection.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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pcb_voltage_protection_embed.sch
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Windows does not recognize XPending, fix typo for verilog_format`s port name: g instead of f
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2021-11-26 13:16:52 +01:00 |
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reg.sch
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removed weird names (spaces etc) in hierarchical_tedax schematic objects. that was used for testing the hiertEDAx export.
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2020-11-24 19:55:45 +01:00 |
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si2306.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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voltage_protection.sch
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Added various procedures to select flat / hierarchical instances and re-route a terminal to a different net. reroute_inst -> change a pin connection, reroute_net -> change net updating all connected components. "xschem instances_to_net", "xschem instance_nodemap", "xschem instance_pin_coord" new query commands added. "xschem get expandlabel node" renamed to "xschem expandlabel node".
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2020-11-26 03:46:55 +01:00 |
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voltage_protection.sym
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edit hierarchical_tedax.sch, different ways to instantiate more times same subschematic, as placed sheet or as symbol
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2020-11-24 11:35:46 +01:00 |
ee67a23465