A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

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Stefan Frederik 06fc742e60 doc updates about {verilog,vhdl,spice}_sym_def, fix regression (possible crash) in verilog_block_netlist (thanks to Joanne), fix regression (wrong verilog test netlist) in print_verilog_primitive() (thanks to Joanne)		2022-10-04 00:37:09 +02:00
XSchemWin	(Joanne) update to be clearer on how to compile xschem (from scratch vs using XSchemWin.sln) on Windows using VS2022. font.sch micro edits	2022-09-28 11:33:48 +02:00
doc	doc updates about {verilog,vhdl,spice}_sym_def, fix regression (possible crash) in verilog_block_netlist (thanks to Joanne), fix regression (wrong verilog test netlist) in print_verilog_primitive() (thanks to Joanne)	2022-10-04 00:37:09 +02:00
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tests	added verilog_extra attribute for list of implicit node connections to symbol in verilog netlists. extra attribute still used in verilog as a list of attributes NOT use as component attributes / symbol parameters.	2022-10-03 01:20:33 +02:00
xschem_library	faster jump table in plot_raw_custom_data(), added simulation->add waveform reload launcher	2022-10-03 11:15:14 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions