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xschem
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update version info in some rom8k symbols. Do a xschem remove_symbols in proc cellview_setlabels to force a reload of changed symbols.

This commit is contained in:
stefan schippers 2025-02-10 18:49:11 +01:00
parent 89a8d8b719
commit fe8ef89052
5 changed files with 13 additions and 9 deletions
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2
src/xschem.tcl
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@ -1817,7 +1817,7 @@ proc cellview_setlabels {w symbol derived_symbol} {
xschem set schsymbolprop $newprop
xschem set_modify 3 ;# set only modified flag to force a save, do not update window/tab titles
xschem save fast
# xschem remove_symbols ;# purge all symbols to force a reload from disk
xschem remove_symbols ;# purge all symbols to force a reload from disk
xschem load -keep_symbols -nodraw -noundoreset $current
set netlist_type $save_netlist_type
xschem set netlist_type $netlist_type

5
xschem_library/rom8k/lvnand2.sym
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@ -1,4 +1,4 @@
v {xschem version=3.4.4 file_version=1.2
v {xschem version=3.4.6 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@ -31,7 +31,8 @@ template="name=x1 m=1
+ VCCPIN=VCC VSSPIN=VSS"
extra="VCCPIN VSSPIN"
generic_type="m=integer wna=real lna=real wpa=real lpa=real wnb=real lnb=real wpb=real lpb=real VCCPIN=string VSSPIN=string"
verilog_stop=true}
verilog_stop=true
}
V {}
S {}
E {}

5
xschem_library/rom8k/lvnor2.sym
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@ -1,4 +1,4 @@
v {xschem version=3.4.4 file_version=1.2
v {xschem version=3.4.6 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@ -19,7 +19,8 @@ v {xschem version=3.4.4 file_version=1.2
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {type=subcircuit
G {}
K {type=subcircuit
vhdl_stop=true
verilog_stop=true
format="@name @pinlist @VCCPIN @VSSPIN @symname wna=@wna lna=@lna wpa=@wpa lpa=@lpa wnb=@wnb lnb=@lnb wpb=@wpb lpb=@lpb m=@m"

5
xschem_library/rom8k/lvnot.sym
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@ -1,4 +1,4 @@
v {xschem version=3.4.4 file_version=1.2
v {xschem version=3.4.6 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@ -30,7 +30,8 @@ template="name=x1 m=1
+ VCCPIN=VCC VSSPIN=VSS"
extra="VCCPIN VSSPIN"
generic_type="m=integer wn=real lln=real wp=real lp=real VCCPIN=string VSSPIN=string"
verilog_stop=true}
verilog_stop=true
}
V {}
S {}
E {}

5
xschem_library/rom8k/rom2_predec1.sym
View File

@ -1,4 +1,4 @@
v {xschem version=3.4.4 file_version=1.2
v {xschem version=3.4.6 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@ -19,7 +19,8 @@ v {xschem version=3.4.4 file_version=1.2
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {type=subcircuit
G {}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}