58 lines
1.9 KiB
Plaintext
58 lines
1.9 KiB
Plaintext
v {xschem version=3.4.6 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {type=subcircuit
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function0="1 ~"
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vhdl_stop=true
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verilog_stop=true
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format="@name @pinlist @VCCPIN @VSSPIN @symname wn=@wn lln=@lln wp=@wp lp=@lp m=@m"
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template="name=x1 m=1
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+ wn=10u lln=1.2u wp=10u lp=1.2u
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+ VCCPIN=VCC VSSPIN=VSS"
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extra="VCCPIN VSSPIN"
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generic_type="m=integer wn=real lln=real wp=real lp=real VCCPIN=string VSSPIN=string"
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verilog_stop=true
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}
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V {}
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S {}
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E {}
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L 4 -40 0 -27.5 0 {}
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L 4 -27.5 -20 -27.5 20 {}
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L 4 -27.5 -20 16.25 0 {}
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L 4 -27.5 20 16.25 0 {}
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L 4 16.25 -2.5 16.25 2.5 {}
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L 4 16.25 -2.5 18.75 -5 {}
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L 4 18.75 -5 23.75 -5 {}
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L 4 23.75 -5 26.25 -2.5 {}
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L 4 26.25 -2.5 26.25 2.5 {}
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L 4 23.75 5 26.25 2.5 {}
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L 4 18.75 5 23.75 5 {}
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L 4 16.25 2.5 18.75 5 {}
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L 4 26.25 0 40 0 {}
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B 5 37.5 -2.5 42.5 2.5 {name=y dir=out verilog_type=wire}
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B 5 -42.5 -2.5 -37.5 2.5 {name=a dir=in goto=0}
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T {n:@wn\\/@lln} -35 35 2 1 0.2 0.2 {}
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T {p:@wp\\/@lp} -35 -22.5 2 1 0.2 0.2 {}
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T {@name} -26.25 -5 0 0 0.2 0.2 {}
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T {m=@m} -10 -37.5 2 1 0.25 0.2 {}
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T {@symname} -6.25 10 0 0 0.2 0.2 {}
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