74 lines
2.3 KiB
Plaintext
74 lines
2.3 KiB
Plaintext
v {xschem version=3.4.6 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {type=subcircuit
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function0="1 2 & ~"
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vhdl_stop=true
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verilog_stop=true
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format="@name @pinlist @VCCPIN @VSSPIN @symname wna=@wna lna=@lna wpa=@wpa lpa=@lpa wnb=@wnb lnb=@lnb wpb=@wpb lpb=@lpb m=@m"
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template="name=x1 m=1
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+ wna=8u lna=1.2u wpa=10u lpa=1.2u
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+ wnb=8u lnb=1.2u wpb=10u lpb=1.2u
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+ VCCPIN=VCC VSSPIN=VSS"
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extra="VCCPIN VSSPIN"
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generic_type="m=integer wna=real lna=real wpa=real lpa=real wnb=real lnb=real wpb=real lpb=real VCCPIN=string VSSPIN=string"
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verilog_stop=true
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}
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V {}
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S {}
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E {}
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L 4 -40 -20 -25 -20 {}
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L 4 35 -2.5 35 2.5 {}
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L 4 35 -2.5 37.5 -5 {}
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L 4 37.5 -5 42.5 -5 {}
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L 4 42.5 -5 45 -2.5 {}
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L 4 45 -2.5 45 2.5 {}
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L 4 42.5 5 45 2.5 {}
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L 4 37.5 5 42.5 5 {}
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L 4 35 2.5 37.5 5 {}
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L 4 45 0 60 0 {}
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L 4 -25 -30 -25 30 {}
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L 4 -25 -30 0 -30 {}
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L 4 -25 30 0 30 {}
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L 4 -40 20 -25 20 {}
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L 4 12.5 -27.5 22.5 -22.5 {}
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L 4 0 -30 12.5 -27.5 {}
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L 4 12.5 27.5 22.5 22.5 {}
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L 4 0 30 12.5 27.5 {}
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L 4 22.5 22.5 30 15 {}
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L 4 30 15 33.75 7.5 {}
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L 4 33.75 7.5 35 0 {}
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L 4 22.5 -22.5 30 -15 {}
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L 4 30 -15 33.75 -7.5 {}
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L 4 33.75 -7.5 35 0 {}
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B 5 57.5 -2.5 62.5 2.5 {name=y dir=out verilog_type=wire}
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B 5 -42.5 -22.5 -37.5 -17.5 {name=a dir=in goto=0}
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B 5 -42.5 17.5 -37.5 22.5 {name=b dir=in goto=0}
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T {na:@wna\\/@lna
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nb:@wnb\\/@lnb} -35 65 2 1 0.2 0.2 {}
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T {pa:@wpa\\/@lpa
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pb:@wpb\\/@lpb} -35 -42.5 2 1 0.2 0.2 {}
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T {m=@m} -10 -67.5 2 1 0.25 0.2 {}
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T {@name} -21.25 -5 0 0 0.2 0.2 {}
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T {a} -20 -25 0 0 0.25 0.2 {}
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T {b} -20 15 0 0 0.25 0.2 {}
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