From fe8ef8905272dd41c21da16a165d389053911e90 Mon Sep 17 00:00:00 2001 From: stefan schippers Date: Mon, 10 Feb 2025 18:49:11 +0100 Subject: [PATCH] update version info in some rom8k symbols. Do a xschem remove_symbols in proc cellview_setlabels to force a reload of changed symbols. --- src/xschem.tcl | 2 +- xschem_library/rom8k/lvnand2.sym | 5 +++-- xschem_library/rom8k/lvnor2.sym | 5 +++-- xschem_library/rom8k/lvnot.sym | 5 +++-- xschem_library/rom8k/rom2_predec1.sym | 5 +++-- 5 files changed, 13 insertions(+), 9 deletions(-) diff --git a/src/xschem.tcl b/src/xschem.tcl index 9093b089..807cbcd7 100644 --- a/src/xschem.tcl +++ b/src/xschem.tcl @@ -1817,7 +1817,7 @@ proc cellview_setlabels {w symbol derived_symbol} { xschem set schsymbolprop $newprop xschem set_modify 3 ;# set only modified flag to force a save, do not update window/tab titles xschem save fast - # xschem remove_symbols ;# purge all symbols to force a reload from disk + xschem remove_symbols ;# purge all symbols to force a reload from disk xschem load -keep_symbols -nodraw -noundoreset $current set netlist_type $save_netlist_type xschem set netlist_type $netlist_type diff --git a/xschem_library/rom8k/lvnand2.sym b/xschem_library/rom8k/lvnand2.sym index 2fa69bb9..805f94a1 100644 --- a/xschem_library/rom8k/lvnand2.sym +++ b/xschem_library/rom8k/lvnand2.sym @@ -1,4 +1,4 @@ -v {xschem version=3.4.4 file_version=1.2 +v {xschem version=3.4.6 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -31,7 +31,8 @@ template="name=x1 m=1 + VCCPIN=VCC VSSPIN=VSS" extra="VCCPIN VSSPIN" generic_type="m=integer wna=real lna=real wpa=real lpa=real wnb=real lnb=real wpb=real lpb=real VCCPIN=string VSSPIN=string" -verilog_stop=true} +verilog_stop=true +} V {} S {} E {} diff --git a/xschem_library/rom8k/lvnor2.sym b/xschem_library/rom8k/lvnor2.sym index 28cea362..95672ee9 100644 --- a/xschem_library/rom8k/lvnor2.sym +++ b/xschem_library/rom8k/lvnor2.sym @@ -1,4 +1,4 @@ -v {xschem version=3.4.4 file_version=1.2 +v {xschem version=3.4.6 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -19,7 +19,8 @@ v {xschem version=3.4.4 file_version=1.2 * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA } -G {type=subcircuit +G {} +K {type=subcircuit vhdl_stop=true verilog_stop=true format="@name @pinlist @VCCPIN @VSSPIN @symname wna=@wna lna=@lna wpa=@wpa lpa=@lpa wnb=@wnb lnb=@lnb wpb=@wpb lpb=@lpb m=@m" diff --git a/xschem_library/rom8k/lvnot.sym b/xschem_library/rom8k/lvnot.sym index 59321d63..2f4980f0 100644 --- a/xschem_library/rom8k/lvnot.sym +++ b/xschem_library/rom8k/lvnot.sym @@ -1,4 +1,4 @@ -v {xschem version=3.4.4 file_version=1.2 +v {xschem version=3.4.6 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -30,7 +30,8 @@ template="name=x1 m=1 + VCCPIN=VCC VSSPIN=VSS" extra="VCCPIN VSSPIN" generic_type="m=integer wn=real lln=real wp=real lp=real VCCPIN=string VSSPIN=string" -verilog_stop=true} +verilog_stop=true +} V {} S {} E {} diff --git a/xschem_library/rom8k/rom2_predec1.sym b/xschem_library/rom8k/rom2_predec1.sym index 630760ce..524d5cc4 100644 --- a/xschem_library/rom8k/rom2_predec1.sym +++ b/xschem_library/rom8k/rom2_predec1.sym @@ -1,4 +1,4 @@ -v {xschem version=3.4.4 file_version=1.2 +v {xschem version=3.4.6 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit @@ -19,7 +19,8 @@ v {xschem version=3.4.4 file_version=1.2 * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA } -G {type=subcircuit +G {} +K {type=subcircuit format="@name @pinlist @symname" template="name=x1" }