2023-10-09 12:49:11 +02:00
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v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2023 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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2022-10-19 10:37:43 +02:00
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}
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2020-10-11 01:38:28 +02:00
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G {}
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K {type=opin
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2020-08-08 15:47:34 +02:00
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format="*.opin @lab"
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template="name=p1 lab=xxx"
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2023-05-27 11:20:49 +02:00
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net_name=true}
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2020-08-08 15:47:34 +02:00
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V {}
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S {}
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E {}
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2022-10-19 10:37:43 +02:00
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L 5 0 0 8.75 0 {}
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B 5 -1.25 -1.25 1.25 1.25 {name=p dir=in}
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P 5 7 17.5 0 13.75 -5 5 -5 8.75 0 5 5 13.75 5 17.5 0 {fill=true}
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2020-10-11 01:38:28 +02:00
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T {@lab} 20 -8.75 0 0 0.33 0.33 {}
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2023-06-05 12:58:19 +02:00
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T {@spice_get_voltage} -1.875 3.90625 0 1 0.2 0.2 {layer=15}
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