2023-10-09 12:49:11 +02:00
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v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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2024-11-12 20:23:18 +01:00
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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2023-10-09 12:49:11 +02:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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2020-08-08 15:47:34 +02:00
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G {type=primitive
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format="@name @pinlist @symname"
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template="name=x1"
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}
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V {}
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S {}
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E {}
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L 4 -60 -20 60 -20 {}
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L 4 -60 20 60 20 {}
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L 4 -60 -20 -60 20 {}
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L 4 60 -20 60 20 {}
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L 4 -80 -10 -60 -10 {}
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L 4 60 -10 80 -10 {}
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L 4 0 -40 0 -20 {}
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B 5 -82.5 -12.5 -77.5 -7.5 {name=IN dir=in }
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B 5 -2.5 -42.5 2.5 -37.5 {name=ADJ dir=in }
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B 5 77.5 -12.5 82.5 -7.5 {name=OUT dir=out }
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T {@symname} -37.5 24 0 0 0.3 0.3 {}
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T {@name} 65 -32 0 0 0.2 0.2 {}
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T {IN} -55 -14 0 0 0.2 0.2 {}
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T {OUT} 55 -14 0 1 0.2 0.2 {}
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T {ADJ} -10 -19 0 0 0.2 0.2 {}
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