stefan schippers edcd141a22 updates for Vacask netlister		2025-07-25 14:53:15 +02:00
..
binto7seg	update license info. Remove unneeded newline saving in version line of .sch/.sym files, remove c89 flag based on lib versions	2024-11-12 20:23:18 +01:00
devices	updates for Vacask netlister	2025-07-25 14:53:15 +02:00
examples	more comments in new examples	2025-04-11 18:56:06 +02:00
generators	update license info. Remove unneeded newline saving in version line of .sch/.sym files, remove c89 flag based on lib versions	2024-11-12 20:23:18 +01:00
gschem_import	update license info. Remove unneeded newline saving in version line of .sch/.sym files, remove c89 flag based on lib versions	2024-11-12 20:23:18 +01:00
inst_sch_select	update license info. Remove unneeded newline saving in version line of .sch/.sym files, remove c89 flag based on lib versions	2024-11-12 20:23:18 +01:00
logic	update license info. Remove unneeded newline saving in version line of .sch/.sym files, remove c89 flag based on lib versions	2024-11-12 20:23:18 +01:00
ngspice	circuit examples updates	2025-04-20 13:59:12 +02:00
ngspice_verilog_cosim	simplify vectored capacitance attribute in ccap.sym used in sar_adc.sch	2025-05-16 23:43:34 +02:00
pcb	update license info. Remove unneeded newline saving in version line of .sch/.sym files, remove c89 flag based on lib versions	2024-11-12 20:23:18 +01:00
rom8k	update version info in some rom8k symbols. Do a xschem remove_symbols in proc cellview_setlabels to force a reload of changed symbols.	2025-02-10 18:49:11 +01:00
rulz-r8c33	update license info. Remove unneeded newline saving in version line of .sch/.sym files, remove c89 flag based on lib versions	2024-11-12 20:23:18 +01:00
symgen	modernization of symgen.awk, fine tuning of create_symbol.tcl	2024-04-12 01:44:48 +02:00
viewdraw_import	…
xTAG	update license info. Remove unneeded newline saving in version line of .sch/.sym files, remove c89 flag based on lib versions	2024-11-12 20:23:18 +01:00
xschem_simulator	update simulate_ff.sch (better looking 7-segment digit)	2024-12-12 01:09:42 +01:00
Makefile	add ngspice_verilog_cosim examples	2025-04-11 18:37:55 +02:00