v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {type=primitive
format="@name @pinlist @symname"
template="name=x1"
}
V {}
S {}
E {}
L 4 -60 -20 60 -20 {}
L 4 -60 20 60 20 {}
L 4 -60 -20 -60 20 {}
L 4 60 -20 60 20 {}
L 4 -80 -10 -60 -10 {}
L 4 60 -10 80 -10 {}
L 4 0 -40 0 -20 {}
B 5 -82.5 -12.5 -77.5 -7.5 {name=IN dir=in }
B 5 -2.5 -42.5 2.5 -37.5 {name=ADJ dir=in }
B 5 77.5 -12.5 82.5 -7.5 {name=OUT dir=out }
T {@symname} -37.5 24 0 0 0.3 0.3 {}
T {@name} 65 -32 0 0 0.2 0.2 {}
T {IN} -55 -14 0 0 0.2 0.2 {}
T {OUT} 55 -14 0 1 0.2 0.2 {}
T {ADJ} -10 -19 0 0 0.2 0.2 {}