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Geza Lore
d4a18d4dfb
The OrderGraph used during V3Order step deliberately omits some variable accesses from the dependency graph. E.g.: a read of a variable that is in the reading block's own hybrid sensitivity list emits no edge, nor does a read ignored due to a force/release, nor an access to a variable marked 'ignoreSchedWrite' and friends. For serial mode that is fine, the logic runs one block at a time. In parallel mode two such blocks can run concurrently, and if one writes what the other reads, that is a data race at runtime. These accesses cannot be recovered from the graph edges. They are now collected from the AST while the OrderGraph is built, and held by the OrderLogicVertex performing them. FixDataHazards is reworked around these access lists stored in OrderLogicVertex, so it is now aware of all variable accesses the logic makes, including those not encoded by the dependency graph edges. The previous heuristic of fixing data hazards by merging same-rank MTasks is removed. Additional edges are inserted instead to prescribe a fixed ordering of conflicting MTasks. To insert edges without unduly increasing the critical path, or introducing cycles, new edges are added such that they preserve topological ordering, and they are inserted between vertices sorted by critical path length. See algorithm details in the code. Also add a data hazard checker under '--debug-partition', reporting every unordered accessor pair left in the final MTask graph. This fixes the race demonstrated by t_sched_hybrid_hazard (#7913), which is no longer expected to fail. Under ThreadSanitizer over the vltmt tests: 17 failing before, 3 after, with no regressions. The 3 remaining are different defects.
..
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Welcome to Verilator
====================
.. list-table::
- - **Welcome to Verilator, the fastest Verilog/SystemVerilog simulator.**
- Accepts Verilog or SystemVerilog
- Performs lint code-quality checks
- Compiles into multithreaded C++, or SystemC
- Creates JSON to front-end your own tools
- |Logo|
- - |verilator multithreaded performance|
- **Fast**
- Outperforms many closed-source commercial simulators
- Single- and multithreaded output models
- - **Widely Used**
- Wide industry and academic deployment
- Out-of-the-box support from Arm and RISC-V vendor IP
- Over 700 contributors
- |verilator usage|
- - |verilator community|
- **Community Driven & Openly Licensed**
- Guided by the `CHIPS Alliance`_ and `Linux Foundation`_
- Open, and free as in both speech and beer
- More simulation for your verification budget
- - **Commercial Support Available**
- Commercial support contracts
- Design support contracts
- Enhancement contracts
- |verilator support|
What Verilator Does
===================
Verilator is invoked with parameters similar to GCC or Synopsys's VCS. It
"Verilates" the specified Verilog or SystemVerilog code by reading it,
performing lint checks, and optionally inserting assertion checks and
coverage-analysis points. It outputs single- or multithreaded .cpp and .h
files, the "Verilated" code.
Verilator can automatically generate a simulator executable (using
``--binary``), or users can write their own C++/SystemC wrapper to
instantiate the model. The resulting Verilated executable performs the
design simulation. Verilator also supports linking Verilator-generated
libraries, optionally encrypted, into other simulators.
Verilator supports all design constructs, most verification constructs,
intra-assignment delays (e.g, `#10`), and events. Tristate-bus (`z`) and
unknowns (`x`) are handled in limited contexts, in a special manor for
performance. It currently may not be the best choice if you are expecting a
full-featured replacement for a closed-source Verilog simulator, performing
SDF annotation, or mixed-signal simulation. However, if you are looking for
a path to migrate SystemVerilog to C++/SystemC, or want high-speed
simulation, Verilator is the tool for you.
Performance
===========
Verilator does not directly translate Verilog HDL to C++ or SystemC.
Rather, Verilator compiles your code into a much faster optimized and
optionally thread-partitioned model, which is in turn wrapped inside a
C++/SystemC module. The results are a compiled Verilog model that executes
even on a single thread over 10x faster than standalone SystemC, and on a
single thread is about 100 times faster than interpreted Verilog simulators
such as `Icarus Verilog`_. Another 2-10x speedup might be gained from
multithreading (yielding 200-1000x total over interpreted simulators).
Verilator has typically similar or better performance versus closed-source
Verilog simulators (e.g., Aldec Riviera-Pro, Cadence Incisive/NC-Verilog,
Mentor ModelSim/Questa, Synopsys VCS, VTOC, and Pragmatic CVer/CVC). But,
Verilator is open-sourced, so you can spend on computes rather than
licenses. Thus, Verilator gives you the best simulation cycles/dollar.
Installation & Documentation
============================
For more information:
- `Verilator installation and package directory structure
<https://verilator.org/install>`_
- `Verilator manual (HTML) <https://verilator.org/verilator_doc.html>`_, or
`Verilator manual (PDF) <https://verilator.org/verilator_doc.pdf>`_
- `Subscribe to Verilator announcements
<https://github.com/verilator/verilator-announce>`_
- `Verilator forum <https://verilator.org/forum>`_
- `Verilator issues <https://verilator.org/issues>`_
Support
=======
Verilator is a community project, guided by the `CHIPS Alliance`_ under the
`Linux Foundation`_.
We appreciate and welcome your contributions in whatever form; please see
`Contributing to Verilator
<https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst>`_.
Thanks to our `Contributors and Sponsors
<https://verilator.org/guide/latest/contributors.html>`_.
Verilator also supports and encourages commercial support models and
organizations; please see `Verilator Commercial Support
<https://verilator.org/verilator_commercial_support>`_.
Related Projects
================
- `Cocotb <https://www.cocotb.org/>`_ - A coroutine-based cosimulation
library for writing testbenches in Python which officially supports
Verilator.
- `GTKwave <https://gtkwave.sourceforge.net/>`_ - Waveform viewer for
Verilator traces.
- `Icarus Verilog`_ - Icarus is a highly-featured interpreted Verilog
simulator. If Verilator does not support your needs, perhaps Icarus may.
- `Surfer <https://surfer-project.org/>`_ - Web or offline waveform viewer
for Verilator traces.
Open License
============
Verilator is Copyright 2003-2026 by Wilson Snyder. (Report bugs to
`Verilator Issues <https://verilator.org/issues>`_.)
Verilator is free software; you can redistribute it and/or modify it under
the terms of either the GNU Lesser General Public License Version 3 or the
Perl Artistic License Version 2.0. See the documentation for more details.
.. _chips alliance: https://chipsalliance.org
.. _icarus verilog: https://steveicarus.github.io/iverilog
.. _linux foundation: https://www.linuxfoundation.org
.. |Logo| image:: https://www.veripool.org/img/verilator_256_200_min.png
.. |verilator multithreaded performance| image:: https://www.veripool.org/img/verilator_multithreaded_performance_bg-min.png
.. |verilator usage| image:: https://www.veripool.org/img/verilator_usage_400x200-min.png
.. |verilator community| image:: https://www.veripool.org/img/verilator_community_400x125-min.png
.. |verilator support| image:: https://www.veripool.org/img/verilator_support_400x125-min.png