Tests: Reformat some recent tests to mostly verilog-format standard. No test functional change.

nodist/verilog_format

@@ -12,6 +12,8 @@
 # SPDX-FileCopyrightText: 2026 Wilson Snyder
 # SPDX-License-Identifier: CC0-1.0
 
+# These flags tested against verible-v0.0-4080-ga0a8d8eb
+
 verible-verilog-format \
     --inplace \
     --wrap_end_else_clauses  \

test_regress/t/t_class_diamond.v

@@ -5,32 +5,32 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module class_tb ();
-interface class Ibase;
-  pure virtual function int fn();
-endclass
+  interface class Ibase;
+    pure virtual function int fn();
+  endclass
 
-interface class Ic1 extends Ibase;
-  pure virtual function int fn1();
-endclass
+  interface class Ic1 extends Ibase;
+    pure virtual function int fn1();
+  endclass
 
-interface class Ic2 extends Ibase;
-  pure virtual function int fn2();
-endclass
+  interface class Ic2 extends Ibase;
+    pure virtual function int fn2();
+  endclass
 
-interface class Ic3 extends Ic1, Ic2;
-endclass
+  interface class Ic3 extends Ic1, Ic2;
+  endclass
 
-class Cls implements Ic3;
-  virtual function int fn();
-    return 10;
-  endfunction
-  virtual function int fn1();
-    return 1;
-  endfunction
-  virtual function int fn2();
-    return 2;
-  endfunction
-endclass
+  class Cls implements Ic3;
+    virtual function int fn();
+      return 10;
+    endfunction
+    virtual function int fn1();
+      return 1;
+    endfunction
+    virtual function int fn2();
+      return 2;
+    endfunction
+  endclass
 
   initial begin
     Cls cls;

test_regress/t/t_class_imp2.v

@@ -26,7 +26,9 @@ module t;
     virtual function void deliver();
       $display("fast delivery");
     endfunction
-    virtual function int seats(); return 4; endfunction
+    virtual function int seats();
+      return 4;
+    endfunction
   endclass
 
   class MetaCar extends Car;

test_regress/t/t_class_new_this.v

@@ -39,7 +39,7 @@ module t;
     cloned = test.clone();
     if (cloned.cls.name != "test_class") $stop;
 
-    test.cls.icls = null; // Prevent leak
+    test.cls.icls = null;  // Prevent leak
 
     $write("*-* All Finished *-*\n");
     $finish;

test_regress/t/t_class_type_param_upcast.v

@@ -6,7 +6,9 @@
 
 // Output arg of class type-parameter accepts a base handle (upcast).
 
-class Fifo #(type T = int);
+class Fifo #(
+    type T = int
+);
   T m_val;
   task get(output T t);
     t = m_val;

test_regress/t/t_constraint_json_only.v

@@ -7,7 +7,7 @@
 class Packet;
   rand int header;  // 0..7
   rand int length;  // 0..15
-  rand int sublength; // 0..15
+  rand int sublength;  // 0..15
   rand bit if_4;
   rand bit iff_5_6;
   rand bit if_state_ok;

test_regress/t/t_constraint_unpacked_array.v

@@ -40,7 +40,8 @@ class con_rand_1d_array_test;
       `check_rand(this, data[i])
       if (data[i] inside {8'h10, 8'h20, 8'h30, 8'h40, 8'h50}) begin
         $display("data[%0d] = %h is valid", i, data[i]);
-      end else begin
+      end
+      else begin
         $display("Error: data[%0d] = %h is out of bounds", i, data[i]);
         $stop;
       end
@@ -70,7 +71,8 @@ class con_rand_2d_array_test;
       `check_rand(this, data[i][j])
       if (data[i][j] >= 8'h10 && data[i][j] <= 8'h50) begin
         $display("data[%0d][%0d] = %h is valid", i, j, data[i][j]);
-      end else begin
+      end
+      else begin
         $display("Error: data[%0d][%0d] = %h is out of bounds", i, j, data[i][j]);
         $stop;
       end
@@ -136,21 +138,21 @@ module t_constraint_unpacked_array;
     // Test 1: Randomization for 1D array
     $display("Test 1: Randomization for 1D array:");
     rand_test_1 = new();
-    repeat(2) begin
+    repeat (2) begin
       rand_test_1.check_randomization();
     end
 
     // Test 2: Randomization for 2D array
     $display("Test 2: Randomization for 2D array:");
     rand_test_2 = new();
-    repeat(2) begin
+    repeat (2) begin
       rand_test_2.check_randomization();
     end
 
     // Test 3: Randomization for 3D array
     $display("Test 3: Randomization for 3D array:");
     rand_test_3 = new();
-    repeat(2) begin
+    repeat (2) begin
       rand_test_3.check_randomization();
     end
 

test_regress/t/t_cover_assert.v

@@ -5,7 +5,7 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t (
-  input clk
+    input clk
 );
 
   int cyc;

test_regress/t/t_flag_build_jobs_and_j.py

@@ -18,6 +18,6 @@ test.compile(verilator_flags2=[
 
 test.execute()
 
-test.file_grep(test.stats, r'Build jobs: 2')
+test.file_grep(test.stats, r'Build jobs: (\d+)', 2)
 
 test.passes()

test_regress/t/t_for_assign.v

@@ -4,10 +4,10 @@
 // SPDX-FileCopyrightText: 2023 Wilson Snyder
 // SPDX-License-Identifier: CC0-1.0
 
-// verilog_format: on
+// verilog_format: off
 `define stop $stop
 `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
-// verilog_format: off
+// verilog_format: on
 
 module t;
 

test_regress/t/t_force_wide_sel.v

@@ -14,7 +14,7 @@ module t (
 );
   integer cyc = 0;
   logic [127:0] sig;
-  logic [127:0] publicSig /*verilator public_flat_rw*/;
+  logic [127:0] publicSig  /*verilator public_flat_rw*/;
 
   always @(posedge clk) begin
     cyc <= cyc + 1;
@@ -40,14 +40,14 @@ module t (
       `checkh(sig[100:5], (96'h1 << 26) | (96'h1 << 27));  // width > 64
       `checkh(sig[70:6], (65'h1 << 25) | (65'h1 << 26));
 
-      `checkh(publicSig[33:26], 8'h60);      // width <= 8
-      `checkh(publicSig[39:24], 16'h180);    // 8 < width <= 16
-      `checkh(publicSig[40:20], 21'h1800);   // 16 < width <= 32
+      `checkh(publicSig[33:26], 8'h60);  // width <= 8
+      `checkh(publicSig[39:24], 16'h180);  // 8 < width <= 16
+      `checkh(publicSig[40:20], 21'h1800);  // 16 < width <= 32
       `checkh(publicSig[51:20], 32'h1800);
       `checkh(publicSig[29:0], 30'h0);
-      `checkh(publicSig[50:10], 41'h600000); // 32 < width <= 64
+      `checkh(publicSig[50:10], 41'h600000);  // 32 < width <= 64
       `checkh(publicSig[73:10], 64'h600000);
-      `checkh(publicSig[100:5], (96'h1 << 26) | (96'h1 << 27)); // width > 64
+      `checkh(publicSig[100:5], (96'h1 << 26) | (96'h1 << 27));  // width > 64
       `checkh(publicSig[70:6], (65'h1 << 25) | (65'h1 << 26));
       $write("*-* All Finished *-*\n");
       $finish;

test_regress/t/t_forceable_unpacked_assign.v

@@ -10,7 +10,7 @@
 // verilog_format: on
 
 module t;
-  logic var_en [0:1] /*verilator forceable*/;
+  logic var_en[0:1]  /*verilator forceable*/;
   logic sig;
 
   initial begin

test_regress/t/t_implements_collision_bad.v

@@ -13,7 +13,7 @@ interface class Icls2;
 endclass
 
 interface class IclsBoth extends Icls1, Icls2;
-  // Bad collision on icfboth
+// Bad collision on icfboth
 endclass
 
 class Cls implements IclsBoth;

test_regress/t/t_implements_noinherit_bad.out

@@ -1,5 +1,5 @@
 %Error: t/t_implements_noinherit_bad.v:14:14: Can't find definition of variable: 'IP'
-   14 |     $display(IP);  
+   14 |     $display(IP);   
       |              ^~
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_implements_noinherit_bad.v

@@ -11,7 +11,7 @@ endclass
 
 class Cls implements Icls;
   function void f;
-    $display(IP); // Bad
+    $display(IP);  // Bad
   endfunction
 endclass
 

test_regress/t/t_math_const.v

@@ -5,12 +5,12 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t (
-  input clk
-  );
+    input clk
+);
 
-  reg [39:0] con1,con2, con3;
+  reg [39:0] con1, con2, con3;
   reg [31:0] w32;
-  reg [31:0] v32 [2];
+  reg [31:0] v32[2];
 
   // surefire lint_off UDDSCN
   reg [200:0] conw3, conw4;

test_regress/t/t_opt_gate_blow_up.py

@@ -18,6 +18,6 @@ memUsageMB = int(test.file_grep(test.stats, r'Peak Memory Usage \(MB\) +(\d+)')[
 if memUsageMB > 128 and not test.have_dev_asan:
     test.error("Consumed over 128MB memory")
 
-test.file_grep(test.stats, r'Verilate jobs: 2')
+test.file_grep(test.stats, r'Verilate jobs: (\d+)', 2)
 
 test.passes()

test_regress/t/t_rand_undefined_var.v

@@ -10,9 +10,7 @@
 `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 // verilog_format: on
 
-typedef struct{
-  rand bit [31:0] x;
-} Bar;
+typedef struct {rand bit [31:0] x;} Bar;
 
 class Foo;
   rand Bar bar0[];
@@ -40,7 +38,7 @@ module t;
     `checkd(foo.bar1.size(), 1);
     `checkd(foo.bar0[0].x, 0);
     `checkd(foo.bar1[0].x, 0);
-    repeat(100) begin
+    repeat (100) begin
       `checkd(foo.randomize(), 1);
       `checkd(foo.bar0.size(), 1);
       `checkd(foo.bar1.size(), 1);

test_regress/t/t_sequence_bool_ops.v

@@ -27,8 +27,7 @@ module t (
 
   always_ff @(posedge clk) begin
 `ifdef TEST_VERBOSE
-    $write("[%0t] cyc==%0d crc=%x a=%b b=%b c=%b d=%b\n",
-           $time, cyc, crc, a, b, c, d);
+    $write("[%0t] cyc==%0d crc=%x a=%b b=%b c=%b d=%b\n", $time, cyc, crc, a, b, c, d);
 `endif
     cyc <= cyc + 1;
     crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
@@ -37,9 +36,11 @@ module t (
     if (cyc == 0) begin
       crc <= 64'h5aef0c8d_d70a4497;
       sum <= '0;
-    end else if (cyc < 10) begin
+    end
+    else if (cyc < 10) begin
       sum <= '0;
-    end else if (cyc == 99) begin
+    end
+    else if (cyc == 99) begin
       `checkh(crc, 64'hc77bb9b3784ea091);
       `checkh(sum, 64'hdb7bc8bfe61f987e);
       $write("*-* All Finished *-*\n");

test_regress/t/t_sequence_intersect.v

@@ -10,7 +10,7 @@
 // verilog_format: on
 
 module t (
-  input clk
+    input clk
 );
   integer cyc = 0;
   reg [63:0] crc = '0;
@@ -26,8 +26,7 @@ module t (
 
   always_ff @(posedge clk) begin
 `ifdef TEST_VERBOSE
-    $write("[%0t] cyc==%0d crc=%x a=%b b=%b c=%b d=%b\n",
-           $time, cyc, crc, a, b, c, d);
+    $write("[%0t] cyc==%0d crc=%x a=%b b=%b c=%b d=%b\n", $time, cyc, crc, a, b, c, d);
 `endif
     cyc <= cyc + 1;
     crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
@@ -36,9 +35,11 @@ module t (
     if (cyc == 0) begin
       crc <= 64'h5aef0c8d_d70a4497;
       sum <= '0;
-    end else if (cyc < 10) begin
+    end
+    else if (cyc < 10) begin
       sum <= '0;
-    end else if (cyc == 99) begin
+    end
+    else if (cyc == 99) begin
       `checkh(crc, 64'hc77bb9b3784ea091);
       `checkh(sum, 64'hdb7bc8bfe61f987e);
       $write("*-* All Finished *-*\n");

test_regress/t/t_std_randomize.v

@@ -63,7 +63,7 @@ module t_scope_std_randomize;
     old_addr = addr;
     old_data = data;
     old_ready = ready;
-    success = randomize(addr, ready); // std::randomize
+    success = randomize(addr, ready);  // std::randomize
     if (success == 0) return 0;
     if (addr == old_addr && data != old_data && ready == old_ready) begin
       return 0;

test_regress/t/t_subclass_nonconstrained_enum.v

@@ -11,18 +11,17 @@
 
 class Sub;
   typedef enum bit [1:0] {
-    one,
-    two,
-    three,
-    four
+    ONE,
+    TWO,
+    THREE,
+    FOUR
   } enum_t;
 
   rand bit num;
   rand enum_t en;
 
-  constraint c {
-    num == 0;
-  };
+  constraint c {num == 0;}
+
 endclass
 
 class Top;

test_regress/t/t_vthread.py

@@ -46,6 +46,6 @@ test.compile(
 
 test.execute()
 
-test.file_grep(test.stats, r'Verilate jobs: 2')
+test.file_grep(test.stats, r'Verilate jobs: (\d+)', 2)
 
 test.passes()