Version bump

Allow arbitrary characters in symbols (to make '-' work.)
Final merge from negative_lsb branch.

Changes

@@ -3,6 +3,20 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilator 3.680 2008/10/08
+
+**   Support negative bit indexes. [Stephane Laurent]
+     Tracing negative indexes requires latest Verilog-Perl and SystemPerl.
+
+***  Suppress width warnings between constant strings and wider vectors.
+     [Rodney Sinclair]
+
+**** Expand environment variables in -f input files.  [Lawrence Butcher]
+
+**** Report error if port declaration is missing; bug32. [Guy-Armand Kamendje]
+
+**** Fix genvars causing link error when using --public.  [Chris Candler]
+
 * Verilator 3.671 2008/09/19
 
 **   SystemC uint64_t pins are now the default instead of sc_bv<64>.

bin/verilator

@@ -974,11 +974,10 @@ Verilator will convert the top level module to a SC_MODULE.  This module
 will plug directly into a SystemC netlist.
 
 The SC_MODULE gets the same pinout as the Verilog module, with the
-following type conversions: Pins of a single bit become bool, unless they
-are marked with `systemc_clock, in which case they become sc_clock's (for
-SystemC 1.2, not needed in SystemC 2.0).  Pins 2-32 bits wide become
-uint32_t's.  Pins 33-64 bits wide become sc_bv's or uint64_t's depending on
-the --no-pins64 switch.  Wider pins become sc_bv's.
+following type conversions: Pins of a single bit become bool.  Pins 2-32
+bits wide become uint32_t's.  Pins 33-64 bits wide become sc_bv's or
+uint64_t's depending on the --no-pins64 switch.  Wider pins become sc_bv's.
+(Uints simulate the fastest so are used where possible.)
 
 Lower modules are not pure SystemC code.  This is a feature, as using the
 SystemC pin interconnect scheme everywhere would reduce performance by an
@@ -1341,7 +1340,9 @@ using the --public switch.
 =item /*verilator sc_clock*/
 
 Used after a input declaration to indicate the signal should be declared in
-SystemC as a sc_clock instead of a bool.
+SystemC as a sc_clock instead of a bool.  This was needed in SystemC 1.1
+and 1.2 only; versions 2.0 and later do not require clock pins to be
+sc_clocks and this is no longer needed.
 
 =item /*verilator tracing_off*/
 

src/V3Ast.cpp

@@ -111,6 +111,14 @@ string AstNode::encodeName(const string& namein) {
     return out;
 }
 
+string AstNode::encodeNumber(vlsint64_t num) {
+    if (num < 0) {
+	return "__2D"+cvtToStr(-num);  // 2D=-
+    } else {
+	return cvtToStr(num);
+    }
+}
+
 string AstNode::shortName() const {
     string pretty = name();
     string::size_type pos;

src/V3Ast.h

@@ -579,6 +579,7 @@ public:
     static string dedotName(const string& namein);	// Name with dots removed
     static string prettyName(const string& namein);	// Name for printing out to the user
     static string encodeName(const string& namein);	// Encode user name into internal C representation
+    static string encodeNumber(vlsint64_t numin);	// Encode number into internal C representation
     string	prettyName() const { return prettyName(name()); }
     FileLine*	fileline() const { return m_fileline; }
     int		width() const { return m_width; }

src/V3AstNodes.cpp

@@ -43,11 +43,11 @@ void AstNodeVarRef::cloneRelink() {
 }
 
 int AstNodeSel::bitConst() const {
-    AstConst* constp=bitp()->castConst(); return (constp?constp->asInt():0);
+    AstConst* constp=bitp()->castConst(); return (constp?constp->toSInt():0);
 }
 
 bool AstVar::isSigPublic() const {
-    return (m_sigPublic || (v3Global.opt.allPublic() && !isTemp()));
+    return (m_sigPublic || (v3Global.opt.allPublic() && !isTemp() && !isGenVar()));
 }
 
 bool AstVar::isScQuad() const {

src/V3AstNodes.h

@@ -50,8 +50,8 @@ public:
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual string name()	const { return num().ascii(); }		// * = Value
     virtual const V3Number& num()	const { return m_num; }		// * = Value
-    uint32_t asInt()  const { return num().asInt(); } // Old, should be removed
     uint32_t toUInt()  const { return num().toUInt(); }
+    vlsint32_t toSInt()  const { return num().toSInt(); }
     vluint64_t toUQuad() const { return num().toUQuad(); }
     virtual string emitVerilog() { V3ERROR_NA; return ""; }  // Implemented specially
     virtual string emitC() { V3ERROR_NA; return ""; }
@@ -79,8 +79,8 @@ struct AstRange : public AstNode {
     AstRange*	cloneTree(bool cloneNextLink) { return AstNode::cloneTree(cloneNextLink)->castRange(); }
     AstNode* msbp()		const { return op2p()->castNode(); }	// op2 = Msb expression
     AstNode* lsbp()		const { return op3p()->castNode(); }	// op3 = Lsb expression
-    int	     msbConst()	const { AstConst* constp=msbp()->castConst(); return (constp?constp->asInt():0); }
-    int	     lsbConst()	const { AstConst* constp=lsbp()->castConst(); return (constp?constp->asInt():0); }
+    int	     msbConst()	const { AstConst* constp=msbp()->castConst(); return (constp?constp->toSInt():0); }
+    int	     lsbConst()	const { AstConst* constp=lsbp()->castConst(); return (constp?constp->toSInt():0); }
     int	     elementsConst() const { return msbConst()-lsbConst()+1; }
     virtual string emitC() { V3ERROR_NA; return ""; }
     virtual V3Hash sameHash() const { return V3Hash(); }
@@ -193,7 +193,7 @@ struct AstSel : public AstNodeTriop {
     // Children: varref|arraysel, math, constant math
     AstSel(FileLine* fl, AstNode* fromp, AstNode* lsbp, AstNode* widthp)
 	:AstNodeTriop(fl, fromp, lsbp, widthp) {
-	if (widthp->castConst()) width(widthp->castConst()->asInt(), widthp->castConst()->asInt());
+	if (widthp->castConst()) width(widthp->castConst()->toUInt(), widthp->castConst()->toUInt());
     }
     AstSel(FileLine* fl, AstNode* fromp, int lsbp, int bitwidth)
 	:AstNodeTriop(fl, fromp,
@@ -205,7 +205,7 @@ struct AstSel : public AstNodeTriop {
     virtual AstNode* clone() { return new AstSel(*this); }
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void numberOperate(V3Number& out, const V3Number& from, const V3Number& bit, const V3Number& width) {
-	out.opRange(from, bit.asInt()+width.asInt()-1, bit.asInt()); }
+	out.opRange(from, bit.toUInt()+width.toUInt()-1, bit.toUInt()); }
     virtual string emitVerilog() { V3ERROR_NA; return ""; }  // Implemented specially
     virtual string emitC() {
 	return this->widthp()->isOne()
@@ -222,9 +222,9 @@ struct AstSel : public AstNodeTriop {
     AstNode* fromp()		const { return op1p()->castNode(); }	// op1 = Extracting what (NULL=TBD during parsing)
     AstNode* lsbp()		const { return op2p()->castNode(); }	// op2 = Msb selection expression
     AstNode* widthp()		const { return op3p()->castNode(); }	// op3 = Width
-    uint32_t	lsbConst()   const { return lsbp()->castConst()->asInt(); }
-    uint32_t	widthConst() const { return widthp()->castConst()->toUInt(); }
-    uint32_t	msbConst()   const { return lsbConst()+widthConst()-1; }
+    int		widthConst() const { return widthp()->castConst()->toSInt(); }
+    int		lsbConst()   const { return lsbp()->castConst()->toSInt(); }
+    int		msbConst()   const { return lsbConst()+widthConst()-1; }
 };
 
 struct AstVar : public AstNode {
@@ -363,8 +363,9 @@ public:
     bool	attrIsolateAssign() const { return m_attrIsolateAssign; }
     int		widthAlignBytes() const;	// Structure alignment 1,2,4 or 8 bytes (arrays affect this)
     int		widthTotalBytes() const;	// Width in bytes rounding up 1,2,4,8,12,...
-    uint32_t	msb() const { if (!rangep()) return 0; return rangep()->msbConst(); }
-    uint32_t	lsb() const { if (!rangep()) return 0; return rangep()->lsbConst(); }
+    int		msb() const { if (!rangep()) return 0; return rangep()->msbConst(); }
+    int		lsb() const { if (!rangep()) return 0; return rangep()->lsbConst(); }
+    int		msbMaxSelect() const { return (lsb()<0 ? msb()-lsb() : msb()); } // Maximum value a [] select may index
     uint32_t	arrayElements() const;	// 1, or total multiplication of all dimensions
     virtual string verilogKwd() const;
     void	propagateAttrFrom(AstVar* fromp) {
@@ -1694,8 +1695,8 @@ struct AstTraceDecl : public AstNodeStmt {
 private:
     string	m_showname;	// Name of variable
     uint32_t	m_code;		// Trace identifier code; converted to ASCII by trace routines
-    uint32_t	m_lsb;		// Property of var the trace details
-    uint32_t	m_msb;		// Property of var the trace details
+    int		m_lsb;		// Property of var the trace details
+    int		m_msb;		// Property of var the trace details
     uint32_t	m_arrayLsb;	// Property of var the trace details
     uint32_t	m_arrayMsb;	// Property of var the trace details
     uint32_t	m_codeInc;	// Code increment
@@ -1723,8 +1724,8 @@ public:
     uint32_t	code() const { return m_code; }
     void	code(uint32_t code) { m_code=code; }
     uint32_t	codeInc() const { return m_codeInc; }
-    uint32_t	msb() const { return m_msb; }
-    uint32_t	lsb() const { return m_lsb; }
+    int		msb() const { return m_msb; }
+    int		lsb() const { return m_lsb; }
     uint32_t	arrayMsb() const { return m_arrayMsb; }
     uint32_t	arrayLsb() const { return m_arrayLsb; }
     uint32_t	arrayWidth() const { if (!arrayMsb()) return 0; return arrayMsb()-arrayLsb()+1; }

src/V3Const.cpp

@@ -134,11 +134,11 @@ private:
     }
     bool operandHugeShiftL(AstNodeBiop* nodep) {
 	return (nodep->rhsp()->castConst()
-		&& nodep->rhsp()->castConst()->asInt() >= (uint32_t)(nodep->width()));
+		&& nodep->rhsp()->castConst()->toUInt() >= (uint32_t)(nodep->width()));
     }
     bool operandHugeShiftR(AstNodeBiop* nodep) {
 	return (nodep->rhsp()->castConst()
-		&& nodep->rhsp()->castConst()->asInt() >= (uint32_t)(nodep->lhsp()->width()));
+		&& nodep->rhsp()->castConst()->toUInt() >= (uint32_t)(nodep->lhsp()->width()));
     }
     bool operandIsTwo(AstNode* nodep) {
 	return (nodep->castConst()
@@ -215,15 +215,18 @@ private:
     bool warnSelect(AstSel* nodep) {
 	AstNode* basefromp = AstArraySel::baseFromp(nodep->fromp());
 	if (AstNodeVarRef* varrefp = basefromp->castNodeVarRef()) {
+	    AstVar* varp = varrefp->varp();
 	    if (m_warn
 		&& nodep->lsbp()->castConst()
 		&& nodep->widthp()->castConst()
-		&& (!varrefp->varp()->rangep() || varrefp->varp()->msb())  // else it's non-resolvable parameterized
-		&& ( (  (nodep->msbConst() > varrefp->varp()->msb())
-			|| (nodep->lsbConst() > varrefp->varp()->msb())))) {
+		&& (!varp->rangep() || varp->msb())  // else it's non-resolvable parameterized
+		&& ( (  (nodep->msbConst() > varp->msbMaxSelect())
+			|| (nodep->lsbConst() > varp->msbMaxSelect())))) {
 		nodep->v3error("Selection index out of range: "
 			       <<nodep->msbConst()<<":"<<nodep->lsbConst()
-			       <<" outside "<<varrefp->varp()->msb()<<":0");
+			       <<" outside "<<varp->msbMaxSelect()<<":0"
+			       <<(varp->lsb()>=0 ? ""
+				  :" (adjusted +"+cvtToStr(-varp->lsb())+" to account for negative lsb)"));
 	    }
 	}
 	return false;  // Not a transform, so NOP
@@ -432,8 +435,8 @@ private:
 	    nodep->accept(*this);	// Further reduce, either node may have more reductions.
 	} else {
 	    // We know shift amounts are constant, but might be a mixed left/right shift
-	    int shift1 = shift1p->castConst()->asInt(); if (lhsp->castShiftR())  shift1=-shift1;
-	    int shift2 = shift2p->castConst()->asInt(); if (nodep->castShiftR()) shift2=-shift2;
+	    int shift1 = shift1p->castConst()->toUInt(); if (lhsp->castShiftR())  shift1=-shift1;
+	    int shift2 = shift2p->castConst()->toUInt(); if (nodep->castShiftR()) shift2=-shift2;
 	    int newshift = shift1+shift2;
 	    shift1p->deleteTree(); shift1p=NULL;
 	    shift2p->deleteTree(); shift1p=NULL;
@@ -490,9 +493,9 @@ private:
 	if (!varNotReferenced(nodep->rhsp(), varref1p->varp())) return false;
 	if (!varNotReferenced(nextp->rhsp(), varref2p->varp())) return false;
 	// Swap?
-	if ((  con1p->asInt() != con2p->asInt() + sel2p->width())
-	    &&(con2p->asInt() != con1p->asInt() + sel1p->width())) return false;
-	bool lsbFirstAssign = (con1p->asInt() < con2p->asInt());
+	if ((  con1p->toSInt() != con2p->toSInt() + sel2p->width())
+	    &&(con2p->toSInt() != con1p->toSInt() + sel1p->width())) return false;
+	bool lsbFirstAssign = (con1p->toUInt() < con2p->toUInt());
 	// If the user already has nice 32-bit divisions, keep them to aid later subdivision
 	//if (VL_BITBIT_I(con1p->toUInt()) == 0) return false;
 	UINFO(4,"replaceAssignMultiSel "<<nodep<<endl);
@@ -648,7 +651,7 @@ private:
 	if (!nodep->castAnd()->rhsp()->castShiftR()) return false;
 	AstShiftR* shiftp = nodep->castAnd()->rhsp()->castShiftR();
 	if (!shiftp->rhsp()->castConst()) return false;
-	if ((uint32_t)(nodep->width()) <= shiftp->rhsp()->castConst()->asInt()) return false;
+	if ((uint32_t)(nodep->width()) <= shiftp->rhsp()->castConst()->toUInt()) return false;
 	return true;
     }
     void replaceBoolShift(AstNode* nodep) {
@@ -784,7 +787,7 @@ private:
 	AstNode* newlsbp;
 	if (lsb1p->castConst() && lsb2p->castConst()) {
 	    newlsbp = new AstConst(lsb1p->fileline(),
-				   lsb1p->castConst()->asInt() + lsb2p->castConst()->asInt());
+				   lsb1p->castConst()->toUInt() + lsb2p->castConst()->toUInt());
 	    lsb1p->deleteTree(); lsb1p=NULL;
 	    lsb2p->deleteTree(); lsb2p=NULL;
 	} else {
@@ -851,7 +854,7 @@ private:
 	AstNode* widthp = nodep->widthp()->unlinkFrBack();
 	AstSel* newp = new AstSel(nodep->fileline(),
 				  fromp,
-				  new AstConst(lsbp->fileline(), lsbp->asInt() % fromp->width()),
+				  new AstConst(lsbp->fileline(), lsbp->toUInt() % fromp->width()),
 				  widthp);
 	newp->widthSignedFrom(nodep);
 	nodep->replaceWith(newp); nodep->deleteTree(); nodep=NULL;

src/V3EmitV.cpp

@@ -362,11 +362,11 @@ public:
 	    if (nodep->widthp()->isOne()) {
 		nodep->lsbp()->iterateAndNext(*this);
 	    } else {
-		puts(cvtToStr(nodep->lsbp()->castConst()->asInt()
-			      +nodep->widthp()->castConst()->asInt()
+		puts(cvtToStr(nodep->lsbp()->castConst()->toSInt()
+			      +nodep->widthp()->castConst()->toSInt()
 			      -1));
 		puts(":");
-		nodep->lsbp()->iterateAndNext(*this);
+		puts(cvtToStr(nodep->lsbp()->castConst()->toSInt()));
 	    }
 	} else {
 	    nodep->lsbp()->iterateAndNext(*this); puts("+:");

src/V3Expand.cpp

@@ -172,7 +172,7 @@ private:
 	// Return equation to get the VL_BITWORD of a constant or non-constant
 	if (lsbp->castConst()) {
 	    return new AstConst (lsbp->fileline(),
-				 wordAdder + VL_BITWORD_I(lsbp->castConst()->asInt()));
+				 wordAdder + VL_BITWORD_I(lsbp->castConst()->toUInt()));
 	} else {
 	    AstNode* shiftp = new AstShiftR (lsbp->fileline(),
 					     lsbp->cloneTree(true),
@@ -203,7 +203,7 @@ private:
 	// Return equation to get the VL_BITBIT of a constant or non-constant
 	if (lsbp->castConst()) {
 	    return new AstConst (lsbp->fileline(),
-				 VL_BITBIT_I(lsbp->castConst()->asInt()));
+				 VL_BITBIT_I(lsbp->castConst()->toUInt()));
 	} else {
 	    return new AstAnd   (lsbp->fileline(),
 				 new AstConst(lsbp->fileline(), VL_WORDSIZE-1),

src/V3Link.cpp

@@ -50,6 +50,7 @@ private:
     //   AstNodeFTask::userp()	// V3SymTable*    Local Symbol table
     //   AstBegin::userp()	// V3SymTable*    Local Symbol table
     //   AstVar::userp()	// V3SymTable*    Table used to create this variable
+    //   AstVar::user2p()	// bool		  True if port set for this variable
 
     // ENUMS
     enum IdState {		// Which loop through the tree
@@ -60,6 +61,7 @@ private:
     // STATE
     // Below state needs to be preserved between each module call.
     AstModule*	m_modp;		// Current module
+    AstNodeFTask* m_ftaskp;	// Current function/task
     IdState	m_idState;	// Id linking mode (find or resolve)
     int		m_paramNum;	// Parameter number, for position based connection
     V3SymTable* m_curVarsp;	// Symbol table of variables and tasks under table we're inserting into
@@ -106,6 +108,7 @@ private:
     // VISITs
     virtual void visit(AstNetlist* nodep, AstNUser*) {
 	AstNode::userClearTree();
+	AstNode::user2ClearTree();
 	// Look at all modules, and store pointers to all module names
 	for (AstModule* modp = v3Global.rootp()->modulesp(); modp; modp=modp->nextp()->castModule()) {
 	    V3SymTable* symp = new V3SymTable(NULL);
@@ -189,6 +192,11 @@ private:
 		}
 	    }
 	}
+	if (m_idState==ID_RESOLVE) {
+	    if (nodep->isIO() && !m_ftaskp && !nodep->user2()) {
+		nodep->v3error("Input/output/inout does not appear in port list: "<<nodep->prettyName());
+	    }
+	}
     }
     virtual void visit(AstVarRef* nodep, AstNUser*) {
 	// VarRef: Resolve its reference
@@ -236,7 +244,9 @@ private:
 		    m_curVarsp->insert(newvarp->name(), newvarp);
 		}
 	    }
+	    m_ftaskp = nodep;
 	    nodep->iterateChildren(*this);
+	    m_ftaskp = NULL;
 	}
 	m_curVarsp = upperVarsp;
 	if (m_idState==ID_FIND) {
@@ -336,6 +346,7 @@ private:
 		nodep->v3error("Pin is not a in/out/inout: "<<nodep->prettyName());
 	    } else {
 		m_curVarsp->insert("__pinNumber"+cvtToStr(nodep->pinNum()), refp);
+		refp->user2(true);
 	    }
 	    // Ports not needed any more
 	    nodep->unlinkFrBack()->deleteTree();  nodep=NULL;
@@ -422,6 +433,7 @@ public:
 	m_curVarsp = NULL;
 	m_cellVarsp = NULL;
 	m_modp = NULL;
+	m_ftaskp = NULL;
 	m_paramNum = 0;
 	m_beginNum = 0;
 	//

src/V3LinkParse.cpp

@@ -160,7 +160,8 @@ private:
 		m_dotText = "";
 		nodep->lhsp()->iterateAndNext(*this);
 		if (AstConst* constp = nodep->rhsp()->castConst()) {
-		    m_dotText = m_dotText+"__BRA__"+cvtToStr(constp->asInt())+"__KET__";
+		    string index = AstNode::encodeNumber(constp->toSInt());
+		    m_dotText = m_dotText+"__BRA__"+index+"__KET__";
 		} else {
 		    nodep->v3error("Unsupported: Non-constant inside []'s in the cell part of a dotted reference");
 		}

src/V3LinkResolve.cpp

@@ -223,7 +223,7 @@ private:
 	AstNode* widthp;
 	if (msbp->castConst() && lsbp->castConst()) {
 	    // Quite common, save V3Const some effort
-	    V3Number widnum (msbp->fileline(),32,msbp->castConst()->asInt() +1-lsbp->castConst()->asInt());
+	    V3Number widnum (msbp->fileline(),32,msbp->castConst()->toSInt() +1-lsbp->castConst()->toSInt());
 	    widnum.width(32,false);  // Unsized so width from user
 	    widthp = new AstConst (msbp->fileline(), widnum);
 	    pushDeletep(msbp);

src/V3Number.cpp

@@ -45,6 +45,7 @@ void V3Number::init (FileLine* fileline, int swidth) {
     m_fileline = fileline;
     m_signed = false;
     m_autoExtend = false;
+    m_fromString = false;
     width(swidth);
     for (int i=0; i<words(); i++) m_value[i]=m_valueX[i] = 0;
 }
@@ -52,6 +53,7 @@ void V3Number::init (FileLine* fileline, int swidth) {
 V3Number::V3Number(VerilogString, FileLine* fileline, const string& str) {
     // Create a number using a verilog string as the value, thus 8 bits per character.
     init(fileline, str.length()*8);
+    m_fromString = true;
     for (unsigned pos=0; pos<str.length(); ++pos) {
 	int topos = str.length()-1-pos;
 	for (int bit=0; bit<8; ++bit) {
@@ -468,10 +470,16 @@ uint32_t V3Number::toUInt() const {
 }
 
 vlsint32_t V3Number::toSInt() const {
-    uint32_t v = toUInt();
-    uint32_t signExtend = (-(v & (1UL<<(width()-1))));
-    uint32_t extended = v | signExtend;
-    return (vlsint32_t)(extended);
+    if (isSigned()) {
+	uint32_t v = toUInt();
+	uint32_t signExtend = (-(v & (1UL<<(width()-1))));
+	uint32_t extended = v | signExtend;
+	return (vlsint32_t)(extended);
+    } else {
+	// Where we use this (widths, etc) and care about signedness,
+	// we can reasonably assume the MSB isn't set on unsigned numbers.
+	return (vlsint32_t)toUInt();
+    }
 }
 
 vluint64_t V3Number::toUQuad() const {

src/V3Number.h

@@ -34,6 +34,7 @@ class V3Number {
     int		m_width;	// Width as specified/calculated.
     bool	m_sized:1;	// True if the user specified the width, else we track it.
     bool	m_signed:1;	// True if signed value
+    bool	m_fromString:1;	// True if from string
     bool	m_autoExtend:1;	// True if SystemVerilog extend-to-any-width
     FileLine*	m_fileline;
     vector<uint32_t>	m_value;	// The Value, with bit 0 being in bit 0 of this vector (unless X/Z)
@@ -124,6 +125,7 @@ public:
     int minWidth() const;	// Minimum width that can represent this number (~== log2(num)+1)
     bool sized() const { return m_sized; }
     bool autoExtend() const { return m_autoExtend; }
+    bool isFromString() const { return m_fromString; }
     bool isSigned() const { return m_signed; }	// Only correct for parsing of numbers from strings, otherwise not used (use AstConst::isSigned())
     bool isNegative() const { return bitIs1(width()-1); }
     bool isFourState() const { for (int i=0;i<words();i++) {if (m_valueX[i]) return true;} return false; }
@@ -135,7 +137,6 @@ public:
     void width(int width, bool sized=true);
     void isSigned(bool ssigned) { m_signed=ssigned; }
     bool isUnknown() const;
-    uint32_t asInt() const { return toUInt(); }  // Deprecated, use toUInt/toSInt
     uint32_t toUInt() const;
     vlsint32_t toSInt() const;
     vluint64_t toUQuad() const;

src/V3Options.cpp

@@ -132,7 +132,7 @@ string V3Options::allArgsString() {
 
 V3LangCode::V3LangCode (const char* textp) {
     // Return code for given string, or ERROR, which is a bad code
-    for (int codei=V3LangCode::ERROR; codei<V3LangCode::MAX; codei++) {
+    for (int codei=V3LangCode::ERROR; codei<V3LangCode::MAX; ++codei) {
 	V3LangCode code = (V3LangCode)codei;
 	if (0==strcasecmp(textp,code.ascii())) {
 	    m_e = code; return;
@@ -177,6 +177,30 @@ string V3Options::filenameNonExt (const string& filename) {
     return base;
 }
 
+string V3Options::filenameSubstitute (const string& filename) {
+    string out;
+    for (string::size_type pos = 0; pos < filename.length(); ++pos) {
+	if (filename[pos] == '$') {
+	    string::size_type endpos = pos+1;
+	    while ((endpos+1) < filename.length()
+		   && (isalnum(filename[endpos+1]) || filename[endpos+1]=='_'))
+		++endpos;
+	    string envvar = filename.substr(pos+1,endpos-pos);
+	    const char* envvalue = NULL;
+	    if (envvar != "") envvalue = getenv(envvar.c_str());
+	    if (envvalue) {
+		out += envvalue;
+		pos = endpos;
+	    } else {
+		out += filename[pos];  // *pos == '$'
+	    }
+	} else {
+	    out += filename[pos];
+	}
+    }
+    return out;
+}
+
 bool V3Options::fileStatDir(const string& filename) {
     struct stat	m_stat;		// Stat information
     int err = stat(filename.c_str(), &m_stat);
@@ -281,12 +305,12 @@ void V3Options::unlinkRegexp(const string& dir, const string& regexp) {
 // Environment
 
 string V3Options::getenvStr(const char* envvar, const char* defaultValue) {
-	if (const char* envvalue = getenv(envvar)) {
-	    return envvalue;
-	} else {
-	    return defaultValue;
-	}
+    if (const char* envvalue = getenv(envvar)) {
+	return envvalue;
+    } else {
+	return defaultValue;
     }
+}
 string V3Options::getenvSYSTEMC() {
     string var = getenvStr("SYSTEMC","");
     if (var == "" && string(DEFENV_SYSTEMC) != "") {
@@ -406,7 +430,7 @@ bool V3Options::wildmatch(const char* s, const char* p) {
 
 string V3Options::downcase(const string& str) {
     string out = str;
-    for (string::iterator pos = out.begin(); pos != out.end(); pos++) {
+    for (string::iterator pos = out.begin(); pos != out.end(); ++pos) {
 	*pos = tolower(*pos);
     }
     return out;
@@ -430,7 +454,7 @@ string V3Options::version() {
 string V3Options::argString (int argc, char** argv) {
     // Return list of arguments as simple string
     string opts;
-    for (int i=0; i<argc; i++)  {
+    for (int i=0; i<argc; ++i)  {
 	if (i!=0) opts += " ";
 	opts += string(argv[i]);
     }
@@ -478,7 +502,7 @@ void V3Options::parseOptsList(FileLine* fl, int argc, char** argv) {
     // Parse parameters
     // Note argc and argv DO NOT INCLUDE the filename in [0]!!!
     // May be called recursively when there are -f files.
-    for (int i=0; i<argc; i++)  {
+    for (int i=0; i<argc; ++i)  {
 	addArg(argv[i]);	// -f's really should be inserted in the middle, but this is for debug
     }
 #define shift { ++i; }
@@ -490,7 +514,7 @@ void V3Options::parseOptsList(FileLine* fl, int argc, char** argv) {
 		addDefine (string (sw+strlen("+define+")));
 	    }
 	    else if ( !strncmp (sw, "+incdir+", 8)) {
-		addIncDir (string (sw+strlen("+incdir+")));
+		addIncDir (filenameSubstitute(string (sw+strlen("+incdir+"))));
 	    }
 	    else if ( !strncmp (sw, "+libext+", 8)) {
 		string exts = string(sw+strlen("+libext+"));
@@ -512,7 +536,7 @@ void V3Options::parseOptsList(FileLine* fl, int argc, char** argv) {
 	    char *sw = argv[i];
 	    bool flag = true;
 	    // Allow gnu -- switches
-	    if (sw[0]=='-' && sw[1]=='-') sw++;
+	    if (sw[0]=='-' && sw[1]=='-') ++sw;
 	    // Switch tests
 	    if ( !strcmp (sw, "-debug") ) {
 		setDebugMode(3);
@@ -560,7 +584,7 @@ void V3Options::parseOptsList(FileLine* fl, int argc, char** argv) {
 	    }
 	    else if ( !strcmp (sw, "-v") ) {
 		shift;
-		V3Options::addLibraryFile(argv[i]);
+		V3Options::addLibraryFile(filenameSubstitute(argv[i]));
 	    }
 	    else if ( !strcmp (sw, "-version") ) {
 		cout <<version();
@@ -599,7 +623,7 @@ void V3Options::parseOptsList(FileLine* fl, int argc, char** argv) {
 	    else if ( onoff   (sw, "-underline-zero", flag/*ref*/) )	{ m_underlineZero = flag; }
 	    // Optimization
 	    else if ( !strncmp (sw, "-O", 2) ) {
-		for (char* cp=sw+strlen("-O"); *cp; cp++) {
+		for (char* cp=sw+strlen("-O"); *cp; ++cp) {
 		    flag = isupper(*cp);
 		    switch (tolower(*cp)) {
 		    case '0': optimize(0); break; // 0=all off
@@ -694,7 +718,7 @@ void V3Options::parseOptsList(FileLine* fl, int argc, char** argv) {
 	    }
 	    else if ( !strcmp (sw, "-f") && (i+1)<argc ) {
 		shift;
-		parseOptsFile(fl, argv[i]);
+		parseOptsFile(fl, filenameSubstitute(argv[i]));
 	    }
 	    else if ( !strcmp (sw, "-gdb") && (i+1)<argc ) {
 		shift; // Used only in perl shell
@@ -729,14 +753,14 @@ void V3Options::parseOptsList(FileLine* fl, int argc, char** argv) {
 	} // - options
 	else {
 	    // Filename
-	    string filename = argv[i];
+	    string filename = filenameSubstitute(argv[i]);
 	    if (filename.find(".cpp") != string::npos
 		|| filename.find(".cxx") != string::npos
 		|| filename.find(".cc") != string::npos
 		|| filename.find(".sp") != string::npos) {
-		V3Options::addCppFile(argv[i]);
+		V3Options::addCppFile(filename);
 	    } else {
-		V3Options::addVFile(argv[i]);
+		V3Options::addVFile(filename);
 	    }
 	    shift;
 	}
@@ -764,17 +788,17 @@ void V3Options::parseOptsFile(FileLine* fl, const string& filename) {
 	getline(*ifp, line);
 	// Strip simple comments
 	string oline;
-	for (string::const_iterator pos = line.begin(); pos != line.end(); pos++) {
+	for (string::const_iterator pos = line.begin(); pos != line.end(); ++pos) {
 	    if (inCmt) {
 		if (*pos=='*' && *(pos+1)=='/') {
 		    inCmt = false;
-		    pos++;
+		    ++pos;
 		}
 	    } else if (*pos=='/' && *(pos+1)=='/') {
 		break;  // Ignore to EOL
 	    } else if (*pos=='/' && *(pos+1)=='*') {
 		inCmt = true;
-		pos++;
+		++pos;
 	    } else {
 		oline += *pos;
 	    }
@@ -797,9 +821,9 @@ void V3Options::parseOptsFile(FileLine* fl, const string& filename) {
     vector<string> args;
     string::size_type startpos = 0;
     while (startpos < whole_file.length()) {
-	while (isspace(whole_file[startpos])) startpos++;
+	while (isspace(whole_file[startpos])) ++startpos;
 	string::size_type endpos = startpos;
-	while (endpos < whole_file.length() && !isspace(whole_file[endpos])) endpos++;
+	while (endpos < whole_file.length() && !isspace(whole_file[endpos])) ++endpos;
 	if (startpos != endpos) {
 	    string arg (whole_file, startpos, endpos-startpos);
 	    args.reserve(args.size()+1);
@@ -810,7 +834,7 @@ void V3Options::parseOptsFile(FileLine* fl, const string& filename) {
 
     // Convert to argv style arg list and parse them
     char* argv [args.size()+1];
-    for (unsigned i=0; i<args.size(); i++) {
+    for (unsigned i=0; i<args.size(); ++i) {
 	argv[i] = (char*)args[i].c_str();
     }
     parseOptsList(fl, args.size(), argv);

src/V3Options.h

@@ -266,6 +266,7 @@ class V3Options {
     static string filenameNonExt (const string& filename);	///< Return non-extensioned (no .) part of filename
     static string filenameNonDirExt (const string& filename) { return filenameNonExt(filenameNonDir(filename)); }	///< Return basename of filename
     static string filenameDir (const string& filename);	///< Return directory part of filename
+    static string filenameSubstitute (const string& filename);	///< Return filename with env vars removed
     static void   unlinkRegexp(const string& dir, const string& regexp);
 
     // METHODS (environment)

src/V3Unroll.cpp

@@ -76,6 +76,11 @@ private:
 	return false;
     }
 
+    int unrollCount() {
+	return m_generate ? v3Global.opt.unrollCount()*16
+	    : v3Global.opt.unrollCount();
+    }
+
     bool forUnrollCheck(AstNode* nodep,
 			AstNode* initp,	// Maybe under nodep (no nextp), or standalone (ignore nextp)
 			AstNode* precondsp, AstNode* condp,
@@ -158,16 +163,16 @@ private:
 	    || constStopp->width()>32 || constStopp->num().isFourState()
 	    || constIncp->width()>32  || constIncp->num().isFourState())
 	    return cantUnroll(nodep, "init/final/increment too large or four state");
-	vlsint32_t valInit = constInitp->num().toUInt();  // Extract as unsigned, then make signed
-	vlsint32_t valStop = constStopp->num().toUInt();  // Extract as unsigned, then make signed
+	vlsint32_t valInit = constInitp->num().toSInt();
+	vlsint32_t valStop = constStopp->num().toSInt();
 	if (lte) valStop++;  if (gte) valStop--;
 	vlsint32_t valInc  = constIncp->num().toSInt();
 	if (subtract) valInc = -valInc;
 	UINFO(8,"     In Numbers: for (v="<<valInit<<"; v<"<<valStop<<"; v=v+"<<valInc<<")\n");
 	//
 	if (!m_generate) {
-	    UINFO(8, "         ~Iters: "<<((valStop - valInit)/valInc)<<" c="<<v3Global.opt.unrollCount()<<endl);
-	    if (((valStop - valInit)/valInc) > v3Global.opt.unrollCount())
+	    UINFO(8, "         ~Iters: "<<((valStop - valInit)/valInc)<<" c="<<unrollCount()<<endl);
+	    if (((valStop - valInit)/valInc) > unrollCount())
 		return cantUnroll(nodep, "too many iterations");
 
 	    // Less than 10 statements in the body?
@@ -253,8 +258,8 @@ private:
 		    else newbodysp = oneloopp;
 
 		    m_statIters++;
-		    if (++times > v3Global.opt.unrollCount()*3) {
-			nodep->v3error("Loop unrolling took too long; probably this is an infinite loop.");
+		    if (++times > unrollCount()*3) {
+			nodep->v3error("Loop unrolling took too long; probably this is an infinite loop, or set --unroll-count above "<<unrollCount());
 			break;
 		    }
 
@@ -347,9 +352,10 @@ private:
 	    ) {
 	    // Rename it, as otherwise we may get a conflict
 	    // V3Begin sees these DOTs and makes CellInlines for us.
-	    string nname = (string)"genfor"+cvtToStr(m_varValuep->asInt())+"__DOT__"+nodep->name();
+	    string index = AstNode::encodeNumber(m_varValuep->toSInt());
+	    string nname = (string)"genfor"+index+"__DOT__"+nodep->name();
 	    // Verilog seems to drop the for loop name and tack on [#]
-	    nname = nodep->name() + "__BRA__" + cvtToStr(m_varValuep->asInt()) + "__KET__";
+	    nname = nodep->name() + "__BRA__" + index + "__KET__";
 	    //UINFO(8,"   Rename begin "<<nname<<" "<<nodep<<endl);
 	    nodep->name(nname);
 	}

src/V3Width.cpp

@@ -238,9 +238,9 @@ private:
 		if (!lsbConstp) nodep->v3error("LSB of bit range isn't a constant");
 		nodep->width(1,1); return;
 	    }
-	    uint32_t msb = msbConstp->asInt();
-	    uint32_t lsb = lsbConstp->asInt();
-	    if (msb > (1UL<<28)) nodep->v3error("MSB of bit range is huge; vector of over 1billion bits: 0x"<<hex<<msb);
+	    int msb = msbConstp->toSInt();
+	    int lsb = lsbConstp->toSInt();
+	    if (msb > (1<<28)) nodep->v3error("MSB of bit range is huge; vector of over 1billion bits: 0x"<<hex<<msb);
 	    if (msb<lsb) {
 		// If it's a array, ok to have either ordering, we'll just correct
 		// So, see if we're sitting under a variable's arrayp.
@@ -296,7 +296,7 @@ private:
 	    int fromlsb = 0;
 	    AstNodeVarRef* varrp = nodep->fromp()->castNodeVarRef();
 	    if (varrp && varrp->varp()->rangep()) {	// Selecting a bit from a multibit register
-		frommsb = varrp->varp()->msb();
+		frommsb = varrp->varp()->msbMaxSelect();  // Corrected for negative lsb
 		fromlsb = varrp->varp()->lsb();
 	    }
 	    int selwidth = V3Number::log2b(frommsb+1-1)+1;	// Width to address a bit
@@ -332,6 +332,8 @@ private:
 		frommsb = varrp->varp()->arrayp(dimension)->msbConst();
 		fromlsb = varrp->varp()->arrayp(dimension)->lsbConst();
 		if (fromlsb>frommsb) {int t=frommsb; frommsb=fromlsb; fromlsb=t; }
+		// However, if the lsb<0 we may go negative, so need more bits!
+		if (fromlsb < 0) frommsb += -fromlsb;
 		nodep->width(outwidth,outwidth);		// Width out = width of array
 	    }
 	    int selwidth = V3Number::log2b(frommsb+1-1)+1;	// Width to address a bit
@@ -911,6 +913,13 @@ void WidthVisitor::widthCheck (AstNode* nodep, const char* side,
     if (expWidthMin==0) expWidthMin = expWidth;
     bool bad = widthBad(underp,expWidth,expWidthMin);
     if (bad && fixAutoExtend(underp/*ref*/,expWidth)) bad=false;  // Changes underp
+    if (underp->castConst() && underp->castConst()->num().isFromString()
+	&& expWidth > underp->width()
+	&& (((expWidth - underp->width()) % 8) == 0)) {  // At least it's character sized
+	// reg [31:0] == "foo" we'll consider probably fine.
+	// Maybe this should be a special warning?  Not for now.
+	ignoreWarn = true;
+    }
     if (bad && !ignoreWarn) {
 	if (debug()>4) nodep->backp()->dumpTree(cout,"  back: ");
 	nodep->v3warn(WIDTH,"Operator "<<nodep->typeName()

src/config_build.h.in

@@ -24,7 +24,7 @@
 //**********************************************************************
 //**** Version and host name
 
-#define DTVERSION	"Verilator 3.671 2008/07/23"
+#define DTVERSION	"Verilator 3.680 2008/10/08"
 
 //**********************************************************************
 //**** Functions

src/verilog.y

@@ -1486,7 +1486,7 @@ pslDirOne<nodep>:
 	;
 
 pslDecl<nodep>:
-		yDEFAULT yPSL_CLOCK '=' senitemEdge ';'		{ $$ = new AstPslDefClock($3, $4); UINFO(0,"CRE "<<$$<<endl)}
+		yDEFAULT yPSL_CLOCK '=' senitemEdge ';'		{ $$ = new AstPslDefClock($3, $4); }
 	|	yDEFAULT yPSL_CLOCK '=' '(' senitemEdge ')' ';'	{ $$ = new AstPslDefClock($3, $5); }
 	;
 

test_regress/Makefile

@@ -33,7 +33,7 @@ endif
 PRODUCTS += --v3
 
 ifeq ($(VERILATOR_AUTHOR_SITE),1)
- DRIVER_FLAGS += -j 4
+ DRIVER_FLAGS += -j 0
 endif
 
 ######################################################################

test_regress/driver.pl

@@ -28,6 +28,7 @@ use Pod::Usage;
 use Data::Dumper;
 use strict;
 use vars qw ($Debug %Vars $Driver $Fork);
+use POSIX qw(strftime);
 
 $::Driver = 1;
 
@@ -74,6 +75,9 @@ if (! GetOptions (
 		  )) {
     usage();
 }
+
+$opt_jobs = calc_jobs() if defined $opt_jobs && $opt_jobs==0;
+
 $Fork->max_proc($opt_jobs);
 
 if (!$opt_vcs && !$opt_nc && !$opt_v3) {
@@ -81,7 +85,7 @@ if (!$opt_vcs && !$opt_nc && !$opt_v3) {
 }
 
 if ($#opt_tests<0) {
-    push @opt_tests, glob ("t/*.pl");
+    push @opt_tests, glob ("t/t_*.pl");
 }
 
 mkdir "obj_dir";
@@ -125,8 +129,8 @@ sub one_test {
 		 $test->oprint("FAILED: ","*"x60,"\n");
 		 push @fails, "\t#".$test->soprint("%Error: $test->{errors}\n");
 		 my $j = ($opt_jobs>1?" -j 2":"");
-		 push @fails, "\t\tmake$j && ( cd test_regress ; "
-		     .$test->{pl_filename}." ".join(' ',@Orig_ARGV_Sw)." )\n";
+		 push @fails, "\t\tmake$j && test_regress/"
+		     .$test->{pl_filename}." ".join(' ',@Orig_ARGV_Sw)."\n";
 		 $failcnt++;
 		 if ($opt_stop) { die "%Error: --stop and errors found\n"; }
 	     }
@@ -134,14 +138,9 @@ sub one_test {
 	 )->ready();
 }
 
-print "\n";
-print "="x70,"\n";
-print "TESTS Passed $okcnt Failed $failcnt\n";
-foreach my $f (@fails) {
-    chomp $f;
-    print "$f\n";
-}
-print "TESTS Passed $okcnt Failed $failcnt\n";
+report(\@fails, undef);
+report(\@fails, "obj_dir/driver_".strftime("%Y%m%d_%H%M%S.log", localtime));
+
 exit(10) if $failcnt;
 
 #----------------------------------------------------------------------
@@ -164,6 +163,35 @@ sub parameter {
     }
 }
 
+sub calc_jobs {
+    my $ok = eval "
+	use Unix::Processors;
+	return Unix::Processors->new->max_online;
+    ";
+    $ok && !$@ or die "%Error: Can't use -j: $@\n";
+    print "driver.pl: Found $ok cores, using -j ",$ok+1,"\n";
+    return $ok + 1;
+}
+
+sub report {
+    my $fails = shift;
+    my $filename = shift;
+
+    my $fh = \*STDOUT;
+    if ($filename) {
+	$fh = IO::File->new(">$filename") or die "%Error: $! writing $filename,";
+    }
+
+    $fh->print("\n");
+    $fh->print("="x70,"\n");
+    $fh->print("TESTS Passed $okcnt Failed $failcnt\n");
+    foreach my $f (@$fails) {
+	chomp $f;
+	$fh->print("$f\n");
+    }
+    $fh->print("TESTS Passed $okcnt Failed $failcnt\n");
+}
+
 #######################################################################
 #######################################################################
 #######################################################################
@@ -896,7 +924,8 @@ Displays this message and program version and exits.
 
 =item --j #
 
-Run number of parallel tests.  Requires Parallel::Forker project.
+Run number of parallel tests, or 0 to determine the count based on the
+number of cores installed.  Requires Parallel::Forker project.
 
 =item --optimize
 

test_regress/t/bootstrap.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/perl
+# DESCRIPTION: Verilator: Verilog Test driver bootstrapper
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+# This is exec'ed by every test that is run standalone (called from the
+# shell as ./t_test_name.pl)
+
+use FindBin;
+use Cwd qw(chdir);
+
+my @args = @ARGV;
+chdir("$FindBin::Bin/..");
+
+@args = map { s!.*test_regress/!!; $_; } @args;
+
+print "cd $ENV{PWD} && $FindBin::Bin/bootstrap.pl ",join(' ',@args),"\n";
+exec("./driver.pl", @args);
+die;

test_regress/t/t_EXAMPLE.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_alw_combdly.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2004 by Wilson Snyder. This program is free software; you can

test_regress/t/t_alw_dly.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_alw_split.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_alw_splitord.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_assert_basic.pl

@@ -1,8 +1,8 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 

test_regress/t/t_assert_basic_cover.pl

@@ -1,8 +1,8 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 

test_regress/t/t_assert_basic_fail.pl

@@ -1,8 +1,8 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 

test_regress/t/t_assert_basic_off.pl

@@ -1,8 +1,8 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 

test_regress/t/t_assert_cover.pl

@@ -1,8 +1,8 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 

test_regress/t/t_assert_cover_off.pl

@@ -1,8 +1,8 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 

test_regress/t/t_assert_synth.pl

@@ -1,8 +1,8 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 

test_regress/t/t_assert_synth_full.pl

@@ -1,8 +1,8 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 

test_regress/t/t_assert_synth_off.pl

@@ -1,8 +1,8 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 

test_regress/t/t_assert_synth_parallel.pl

@@ -1,8 +1,8 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 

test_regress/t/t_blocking.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2004 by Wilson Snyder. This program is free software; you can

test_regress/t/t_case_66bits.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 
 compile (
 	 );

test_regress/t/t_case_auto1.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_case_deep.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_case_default_bad.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_case_genx_bad.pl

@@ -1,8 +1,8 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 

test_regress/t/t_case_huge.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_case_itemwidth.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_case_nest.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_case_wild.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_case_write1.pl

@@ -1,8 +1,8 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 

test_regress/t/t_case_write2.pl

@@ -1,8 +1,8 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 

test_regress/t/t_case_x.pl

@@ -1,8 +1,8 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 

test_regress/t/t_case_x_bad.pl

@@ -1,8 +1,8 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 

test_regress/t/t_case_zx_bad.pl

@@ -1,8 +1,8 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 

test_regress/t/t_clk_condflop.pl

@@ -1,8 +1,8 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 

test_regress/t/t_clk_dpulse.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_clk_dsp.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_clk_gen.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_clk_latch.pl

@@ -1,8 +1,8 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 

test_regress/t/t_clk_latch_edgestyle.pl

@@ -1,8 +1,8 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 

test_regress/t/t_clk_powerdn.pl

@@ -1,8 +1,8 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 

test_regress/t/t_delay.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_delay_stmtdly_bad.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_display.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_display_bad.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_display_noopt.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_display_signed.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_display_signed_noopt.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_display_time.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_dist_manifest.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_dos.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_emit_constw.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_extend.pl

@@ -1,8 +1,8 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 

test_regress/t/t_extend_class.pl

@@ -1,8 +1,8 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 

test_regress/t/t_flag_f.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2008 by Wilson Snyder. This program is free software; you can

test_regress/t/t_flag_f.vc

@@ -1,10 +1,2 @@
-
-+define+GOT_DEF1
-
-  // -DNON_DEF
-  /*
-   +define+NON_DEF
-   */
-
-+define+GOT_DEF2=1
-
+// Test that environment substitutions work
+-f $VERILATOR_ROOT/test_regress/t/t_flag_f__2.vc

test_regress/t/t_flag_f__2.vc

@@ -0,0 +1,10 @@
+
++define+GOT_DEF1
+
+  // -DNON_DEF
+  /*
+   +define+NON_DEF
+   */
+
++define+GOT_DEF2=1
+

test_regress/t/t_flag_future.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2008 by Wilson Snyder. This program is free software; you can

test_regress/t/t_flag_language.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 
 compile (
 	 verilator_flags2 => ['--language 1364-2001'],

test_regress/t/t_flag_lib.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 
 compile (
 	 v_flags2 => ['-v', 't/t_flag_libinc.v'],

test_regress/t/t_flag_nomod_bad.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2008 by Wilson Snyder. This program is free software; you can

test_regress/t/t_flag_skipidentical.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_flag_topmodule.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2008 by Wilson Snyder. This program is free software; you can

test_regress/t/t_flag_topmodule_bad.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2008 by Wilson Snyder. This program is free software; you can

test_regress/t/t_flag_topmodule_bad2.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2008 by Wilson Snyder. This program is free software; you can

test_regress/t/t_flag_werror_bad1.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_flag_werror_bad2.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_for_count.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2004 by Wilson Snyder. This program is free software; you can

test_regress/t/t_for_funcbound.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2004 by Wilson Snyder. This program is free software; you can

test_regress/t/t_func.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_func_bad.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_func_bad2.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_func_bad_width.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_func_check.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_func_crc.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_func_dotted_inl0.pl

@@ -1,8 +1,8 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 

test_regress/t/t_func_dotted_inl1.pl

@@ -1,8 +1,8 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 

test_regress/t/t_func_dotted_inl2.pl

@@ -1,8 +1,8 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
 

test_regress/t/t_func_endian.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_func_flip.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_func_graphcirc.pl

@@ -1,5 +1,5 @@
 #!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can