Support negative bit indexes.
Allow arbitrary characters in symbols (to make '-' work.) Final merge from negative_lsb branch.
This commit is contained in:
Wilson Snyder
parent
cdd6ea8e60
commit
3b1929259a
3
Changes
3
Changes
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@ -5,6 +5,9 @@ indicates the contributor was also the author of the fix; Thanks!
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* Verilator 3.67**
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** Support negative bit indexes. [Stephane Laurent]
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Tracing negative indexes requires latest Verilog-Perl and SystemPerl.
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*** Suppress width warnings between constant strings and wider vectors.
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[Rodney Sinclair]
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@ -111,6 +111,14 @@ string AstNode::encodeName(const string& namein) {
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return out;
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}
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string AstNode::encodeNumber(vlsint64_t num) {
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if (num < 0) {
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return "__2D"+cvtToStr(-num); // 2D=-
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} else {
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return cvtToStr(num);
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}
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}
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string AstNode::shortName() const {
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string pretty = name();
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string::size_type pos;
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@ -579,6 +579,7 @@ public:
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static string dedotName(const string& namein); // Name with dots removed
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static string prettyName(const string& namein); // Name for printing out to the user
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static string encodeName(const string& namein); // Encode user name into internal C representation
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static string encodeNumber(vlsint64_t numin); // Encode number into internal C representation
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string prettyName() const { return prettyName(name()); }
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FileLine* fileline() const { return m_fileline; }
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int width() const { return m_width; }
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@ -43,7 +43,7 @@ void AstNodeVarRef::cloneRelink() {
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}
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int AstNodeSel::bitConst() const {
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AstConst* constp=bitp()->castConst(); return (constp?constp->asInt():0);
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AstConst* constp=bitp()->castConst(); return (constp?constp->toSInt():0);
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}
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bool AstVar::isSigPublic() const {
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@ -50,8 +50,8 @@ public:
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virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
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virtual string name() const { return num().ascii(); } // * = Value
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virtual const V3Number& num() const { return m_num; } // * = Value
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uint32_t asInt() const { return num().asInt(); } // Old, should be removed
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uint32_t toUInt() const { return num().toUInt(); }
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vlsint32_t toSInt() const { return num().toSInt(); }
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vluint64_t toUQuad() const { return num().toUQuad(); }
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virtual string emitVerilog() { V3ERROR_NA; return ""; } // Implemented specially
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virtual string emitC() { V3ERROR_NA; return ""; }
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@ -79,8 +79,8 @@ struct AstRange : public AstNode {
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AstRange* cloneTree(bool cloneNextLink) { return AstNode::cloneTree(cloneNextLink)->castRange(); }
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AstNode* msbp() const { return op2p()->castNode(); } // op2 = Msb expression
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AstNode* lsbp() const { return op3p()->castNode(); } // op3 = Lsb expression
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int msbConst() const { AstConst* constp=msbp()->castConst(); return (constp?constp->asInt():0); }
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int lsbConst() const { AstConst* constp=lsbp()->castConst(); return (constp?constp->asInt():0); }
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int msbConst() const { AstConst* constp=msbp()->castConst(); return (constp?constp->toSInt():0); }
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int lsbConst() const { AstConst* constp=lsbp()->castConst(); return (constp?constp->toSInt():0); }
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int elementsConst() const { return msbConst()-lsbConst()+1; }
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virtual string emitC() { V3ERROR_NA; return ""; }
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virtual V3Hash sameHash() const { return V3Hash(); }
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@ -193,7 +193,7 @@ struct AstSel : public AstNodeTriop {
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// Children: varref|arraysel, math, constant math
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AstSel(FileLine* fl, AstNode* fromp, AstNode* lsbp, AstNode* widthp)
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:AstNodeTriop(fl, fromp, lsbp, widthp) {
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if (widthp->castConst()) width(widthp->castConst()->asInt(), widthp->castConst()->asInt());
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if (widthp->castConst()) width(widthp->castConst()->toUInt(), widthp->castConst()->toUInt());
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}
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AstSel(FileLine* fl, AstNode* fromp, int lsbp, int bitwidth)
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:AstNodeTriop(fl, fromp,
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@ -205,7 +205,7 @@ struct AstSel : public AstNodeTriop {
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virtual AstNode* clone() { return new AstSel(*this); }
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virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
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virtual void numberOperate(V3Number& out, const V3Number& from, const V3Number& bit, const V3Number& width) {
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out.opRange(from, bit.asInt()+width.asInt()-1, bit.asInt()); }
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out.opRange(from, bit.toUInt()+width.toUInt()-1, bit.toUInt()); }
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virtual string emitVerilog() { V3ERROR_NA; return ""; } // Implemented specially
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virtual string emitC() {
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return this->widthp()->isOne()
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@ -222,9 +222,9 @@ struct AstSel : public AstNodeTriop {
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AstNode* fromp() const { return op1p()->castNode(); } // op1 = Extracting what (NULL=TBD during parsing)
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AstNode* lsbp() const { return op2p()->castNode(); } // op2 = Msb selection expression
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AstNode* widthp() const { return op3p()->castNode(); } // op3 = Width
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uint32_t lsbConst() const { return lsbp()->castConst()->asInt(); }
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uint32_t widthConst() const { return widthp()->castConst()->toUInt(); }
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uint32_t msbConst() const { return lsbConst()+widthConst()-1; }
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int widthConst() const { return widthp()->castConst()->toSInt(); }
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int lsbConst() const { return lsbp()->castConst()->toSInt(); }
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int msbConst() const { return lsbConst()+widthConst()-1; }
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};
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struct AstVar : public AstNode {
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@ -363,8 +363,9 @@ public:
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bool attrIsolateAssign() const { return m_attrIsolateAssign; }
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int widthAlignBytes() const; // Structure alignment 1,2,4 or 8 bytes (arrays affect this)
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int widthTotalBytes() const; // Width in bytes rounding up 1,2,4,8,12,...
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uint32_t msb() const { if (!rangep()) return 0; return rangep()->msbConst(); }
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uint32_t lsb() const { if (!rangep()) return 0; return rangep()->lsbConst(); }
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int msb() const { if (!rangep()) return 0; return rangep()->msbConst(); }
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int lsb() const { if (!rangep()) return 0; return rangep()->lsbConst(); }
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int msbMaxSelect() const { return (lsb()<0 ? msb()-lsb() : msb()); } // Maximum value a [] select may index
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uint32_t arrayElements() const; // 1, or total multiplication of all dimensions
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virtual string verilogKwd() const;
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void propagateAttrFrom(AstVar* fromp) {
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@ -1694,8 +1695,8 @@ struct AstTraceDecl : public AstNodeStmt {
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private:
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string m_showname; // Name of variable
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uint32_t m_code; // Trace identifier code; converted to ASCII by trace routines
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uint32_t m_lsb; // Property of var the trace details
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uint32_t m_msb; // Property of var the trace details
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int m_lsb; // Property of var the trace details
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int m_msb; // Property of var the trace details
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uint32_t m_arrayLsb; // Property of var the trace details
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uint32_t m_arrayMsb; // Property of var the trace details
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uint32_t m_codeInc; // Code increment
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@ -1723,8 +1724,8 @@ public:
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uint32_t code() const { return m_code; }
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void code(uint32_t code) { m_code=code; }
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uint32_t codeInc() const { return m_codeInc; }
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uint32_t msb() const { return m_msb; }
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uint32_t lsb() const { return m_lsb; }
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int msb() const { return m_msb; }
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int lsb() const { return m_lsb; }
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uint32_t arrayMsb() const { return m_arrayMsb; }
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uint32_t arrayLsb() const { return m_arrayLsb; }
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uint32_t arrayWidth() const { if (!arrayMsb()) return 0; return arrayMsb()-arrayLsb()+1; }
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@ -134,11 +134,11 @@ private:
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}
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bool operandHugeShiftL(AstNodeBiop* nodep) {
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return (nodep->rhsp()->castConst()
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&& nodep->rhsp()->castConst()->asInt() >= (uint32_t)(nodep->width()));
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&& nodep->rhsp()->castConst()->toUInt() >= (uint32_t)(nodep->width()));
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}
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bool operandHugeShiftR(AstNodeBiop* nodep) {
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return (nodep->rhsp()->castConst()
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&& nodep->rhsp()->castConst()->asInt() >= (uint32_t)(nodep->lhsp()->width()));
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&& nodep->rhsp()->castConst()->toUInt() >= (uint32_t)(nodep->lhsp()->width()));
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}
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bool operandIsTwo(AstNode* nodep) {
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return (nodep->castConst()
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@ -215,15 +215,18 @@ private:
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bool warnSelect(AstSel* nodep) {
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AstNode* basefromp = AstArraySel::baseFromp(nodep->fromp());
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if (AstNodeVarRef* varrefp = basefromp->castNodeVarRef()) {
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AstVar* varp = varrefp->varp();
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if (m_warn
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&& nodep->lsbp()->castConst()
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&& nodep->widthp()->castConst()
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&& (!varrefp->varp()->rangep() || varrefp->varp()->msb()) // else it's non-resolvable parameterized
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&& ( ( (nodep->msbConst() > varrefp->varp()->msb())
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|| (nodep->lsbConst() > varrefp->varp()->msb())))) {
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&& (!varp->rangep() || varp->msb()) // else it's non-resolvable parameterized
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&& ( ( (nodep->msbConst() > varp->msbMaxSelect())
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|| (nodep->lsbConst() > varp->msbMaxSelect())))) {
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nodep->v3error("Selection index out of range: "
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<<nodep->msbConst()<<":"<<nodep->lsbConst()
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<<" outside "<<varrefp->varp()->msb()<<":0");
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<<" outside "<<varp->msbMaxSelect()<<":0"
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<<(varp->lsb()>=0 ? ""
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:" (adjusted +"+cvtToStr(-varp->lsb())+" to account for negative lsb)"));
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}
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}
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return false; // Not a transform, so NOP
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@ -432,8 +435,8 @@ private:
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nodep->accept(*this); // Further reduce, either node may have more reductions.
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} else {
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// We know shift amounts are constant, but might be a mixed left/right shift
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int shift1 = shift1p->castConst()->asInt(); if (lhsp->castShiftR()) shift1=-shift1;
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int shift2 = shift2p->castConst()->asInt(); if (nodep->castShiftR()) shift2=-shift2;
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int shift1 = shift1p->castConst()->toUInt(); if (lhsp->castShiftR()) shift1=-shift1;
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int shift2 = shift2p->castConst()->toUInt(); if (nodep->castShiftR()) shift2=-shift2;
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int newshift = shift1+shift2;
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shift1p->deleteTree(); shift1p=NULL;
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shift2p->deleteTree(); shift1p=NULL;
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@ -490,9 +493,9 @@ private:
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if (!varNotReferenced(nodep->rhsp(), varref1p->varp())) return false;
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if (!varNotReferenced(nextp->rhsp(), varref2p->varp())) return false;
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// Swap?
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if (( con1p->asInt() != con2p->asInt() + sel2p->width())
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&&(con2p->asInt() != con1p->asInt() + sel1p->width())) return false;
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bool lsbFirstAssign = (con1p->asInt() < con2p->asInt());
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if (( con1p->toSInt() != con2p->toSInt() + sel2p->width())
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&&(con2p->toSInt() != con1p->toSInt() + sel1p->width())) return false;
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bool lsbFirstAssign = (con1p->toUInt() < con2p->toUInt());
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// If the user already has nice 32-bit divisions, keep them to aid later subdivision
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//if (VL_BITBIT_I(con1p->toUInt()) == 0) return false;
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UINFO(4,"replaceAssignMultiSel "<<nodep<<endl);
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@ -648,7 +651,7 @@ private:
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if (!nodep->castAnd()->rhsp()->castShiftR()) return false;
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AstShiftR* shiftp = nodep->castAnd()->rhsp()->castShiftR();
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if (!shiftp->rhsp()->castConst()) return false;
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if ((uint32_t)(nodep->width()) <= shiftp->rhsp()->castConst()->asInt()) return false;
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if ((uint32_t)(nodep->width()) <= shiftp->rhsp()->castConst()->toUInt()) return false;
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return true;
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}
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void replaceBoolShift(AstNode* nodep) {
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@ -784,7 +787,7 @@ private:
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AstNode* newlsbp;
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if (lsb1p->castConst() && lsb2p->castConst()) {
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newlsbp = new AstConst(lsb1p->fileline(),
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lsb1p->castConst()->asInt() + lsb2p->castConst()->asInt());
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lsb1p->castConst()->toUInt() + lsb2p->castConst()->toUInt());
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lsb1p->deleteTree(); lsb1p=NULL;
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lsb2p->deleteTree(); lsb2p=NULL;
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} else {
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@ -851,7 +854,7 @@ private:
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AstNode* widthp = nodep->widthp()->unlinkFrBack();
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AstSel* newp = new AstSel(nodep->fileline(),
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fromp,
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new AstConst(lsbp->fileline(), lsbp->asInt() % fromp->width()),
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new AstConst(lsbp->fileline(), lsbp->toUInt() % fromp->width()),
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widthp);
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newp->widthSignedFrom(nodep);
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nodep->replaceWith(newp); nodep->deleteTree(); nodep=NULL;
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@ -362,11 +362,11 @@ public:
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if (nodep->widthp()->isOne()) {
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nodep->lsbp()->iterateAndNext(*this);
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} else {
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puts(cvtToStr(nodep->lsbp()->castConst()->asInt()
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+nodep->widthp()->castConst()->asInt()
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puts(cvtToStr(nodep->lsbp()->castConst()->toSInt()
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+nodep->widthp()->castConst()->toSInt()
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-1));
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puts(":");
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nodep->lsbp()->iterateAndNext(*this);
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puts(cvtToStr(nodep->lsbp()->castConst()->toSInt()));
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}
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} else {
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nodep->lsbp()->iterateAndNext(*this); puts("+:");
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@ -172,7 +172,7 @@ private:
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// Return equation to get the VL_BITWORD of a constant or non-constant
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if (lsbp->castConst()) {
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return new AstConst (lsbp->fileline(),
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wordAdder + VL_BITWORD_I(lsbp->castConst()->asInt()));
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wordAdder + VL_BITWORD_I(lsbp->castConst()->toUInt()));
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} else {
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AstNode* shiftp = new AstShiftR (lsbp->fileline(),
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lsbp->cloneTree(true),
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@ -203,7 +203,7 @@ private:
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// Return equation to get the VL_BITBIT of a constant or non-constant
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if (lsbp->castConst()) {
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return new AstConst (lsbp->fileline(),
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VL_BITBIT_I(lsbp->castConst()->asInt()));
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VL_BITBIT_I(lsbp->castConst()->toUInt()));
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} else {
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return new AstAnd (lsbp->fileline(),
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new AstConst(lsbp->fileline(), VL_WORDSIZE-1),
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@ -160,7 +160,8 @@ private:
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m_dotText = "";
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nodep->lhsp()->iterateAndNext(*this);
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if (AstConst* constp = nodep->rhsp()->castConst()) {
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m_dotText = m_dotText+"__BRA__"+cvtToStr(constp->asInt())+"__KET__";
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string index = AstNode::encodeNumber(constp->toSInt());
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m_dotText = m_dotText+"__BRA__"+index+"__KET__";
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} else {
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nodep->v3error("Unsupported: Non-constant inside []'s in the cell part of a dotted reference");
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}
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@ -223,7 +223,7 @@ private:
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AstNode* widthp;
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if (msbp->castConst() && lsbp->castConst()) {
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// Quite common, save V3Const some effort
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V3Number widnum (msbp->fileline(),32,msbp->castConst()->asInt() +1-lsbp->castConst()->asInt());
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V3Number widnum (msbp->fileline(),32,msbp->castConst()->toSInt() +1-lsbp->castConst()->toSInt());
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widnum.width(32,false); // Unsized so width from user
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widthp = new AstConst (msbp->fileline(), widnum);
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pushDeletep(msbp);
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@ -470,10 +470,16 @@ uint32_t V3Number::toUInt() const {
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}
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vlsint32_t V3Number::toSInt() const {
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uint32_t v = toUInt();
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uint32_t signExtend = (-(v & (1UL<<(width()-1))));
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uint32_t extended = v | signExtend;
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return (vlsint32_t)(extended);
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if (isSigned()) {
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uint32_t v = toUInt();
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uint32_t signExtend = (-(v & (1UL<<(width()-1))));
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uint32_t extended = v | signExtend;
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return (vlsint32_t)(extended);
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} else {
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// Where we use this (widths, etc) and care about signedness,
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// we can reasonably assume the MSB isn't set on unsigned numbers.
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return (vlsint32_t)toUInt();
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}
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}
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vluint64_t V3Number::toUQuad() const {
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@ -137,7 +137,6 @@ public:
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void width(int width, bool sized=true);
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void isSigned(bool ssigned) { m_signed=ssigned; }
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bool isUnknown() const;
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uint32_t asInt() const { return toUInt(); } // Deprecated, use toUInt/toSInt
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uint32_t toUInt() const;
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vlsint32_t toSInt() const;
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vluint64_t toUQuad() const;
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@ -76,6 +76,11 @@ private:
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return false;
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}
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int unrollCount() {
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return m_generate ? v3Global.opt.unrollCount()*16
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: v3Global.opt.unrollCount();
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}
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bool forUnrollCheck(AstNode* nodep,
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AstNode* initp, // Maybe under nodep (no nextp), or standalone (ignore nextp)
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AstNode* precondsp, AstNode* condp,
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@ -158,16 +163,16 @@ private:
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|| constStopp->width()>32 || constStopp->num().isFourState()
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|| constIncp->width()>32 || constIncp->num().isFourState())
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return cantUnroll(nodep, "init/final/increment too large or four state");
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vlsint32_t valInit = constInitp->num().toUInt(); // Extract as unsigned, then make signed
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vlsint32_t valStop = constStopp->num().toUInt(); // Extract as unsigned, then make signed
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vlsint32_t valInit = constInitp->num().toSInt();
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vlsint32_t valStop = constStopp->num().toSInt();
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if (lte) valStop++; if (gte) valStop--;
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vlsint32_t valInc = constIncp->num().toSInt();
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if (subtract) valInc = -valInc;
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UINFO(8," In Numbers: for (v="<<valInit<<"; v<"<<valStop<<"; v=v+"<<valInc<<")\n");
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//
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if (!m_generate) {
|
||||
UINFO(8, " ~Iters: "<<((valStop - valInit)/valInc)<<" c="<<v3Global.opt.unrollCount()<<endl);
|
||||
if (((valStop - valInit)/valInc) > v3Global.opt.unrollCount())
|
||||
UINFO(8, " ~Iters: "<<((valStop - valInit)/valInc)<<" c="<<unrollCount()<<endl);
|
||||
if (((valStop - valInit)/valInc) > unrollCount())
|
||||
return cantUnroll(nodep, "too many iterations");
|
||||
|
||||
// Less than 10 statements in the body?
|
||||
|
|
@ -253,8 +258,8 @@ private:
|
|||
else newbodysp = oneloopp;
|
||||
|
||||
m_statIters++;
|
||||
if (++times > v3Global.opt.unrollCount()*3) {
|
||||
nodep->v3error("Loop unrolling took too long; probably this is an infinite loop.");
|
||||
if (++times > unrollCount()*3) {
|
||||
nodep->v3error("Loop unrolling took too long; probably this is an infinite loop, or set --unroll-count above "<<unrollCount());
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -347,9 +352,10 @@ private:
|
|||
) {
|
||||
// Rename it, as otherwise we may get a conflict
|
||||
// V3Begin sees these DOTs and makes CellInlines for us.
|
||||
string nname = (string)"genfor"+cvtToStr(m_varValuep->asInt())+"__DOT__"+nodep->name();
|
||||
string index = AstNode::encodeNumber(m_varValuep->toSInt());
|
||||
string nname = (string)"genfor"+index+"__DOT__"+nodep->name();
|
||||
// Verilog seems to drop the for loop name and tack on [#]
|
||||
nname = nodep->name() + "__BRA__" + cvtToStr(m_varValuep->asInt()) + "__KET__";
|
||||
nname = nodep->name() + "__BRA__" + index + "__KET__";
|
||||
//UINFO(8," Rename begin "<<nname<<" "<<nodep<<endl);
|
||||
nodep->name(nname);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -238,9 +238,9 @@ private:
|
|||
if (!lsbConstp) nodep->v3error("LSB of bit range isn't a constant");
|
||||
nodep->width(1,1); return;
|
||||
}
|
||||
uint32_t msb = msbConstp->asInt();
|
||||
uint32_t lsb = lsbConstp->asInt();
|
||||
if (msb > (1UL<<28)) nodep->v3error("MSB of bit range is huge; vector of over 1billion bits: 0x"<<hex<<msb);
|
||||
int msb = msbConstp->toSInt();
|
||||
int lsb = lsbConstp->toSInt();
|
||||
if (msb > (1<<28)) nodep->v3error("MSB of bit range is huge; vector of over 1billion bits: 0x"<<hex<<msb);
|
||||
if (msb<lsb) {
|
||||
// If it's a array, ok to have either ordering, we'll just correct
|
||||
// So, see if we're sitting under a variable's arrayp.
|
||||
|
|
@ -296,7 +296,7 @@ private:
|
|||
int fromlsb = 0;
|
||||
AstNodeVarRef* varrp = nodep->fromp()->castNodeVarRef();
|
||||
if (varrp && varrp->varp()->rangep()) { // Selecting a bit from a multibit register
|
||||
frommsb = varrp->varp()->msb();
|
||||
frommsb = varrp->varp()->msbMaxSelect(); // Corrected for negative lsb
|
||||
fromlsb = varrp->varp()->lsb();
|
||||
}
|
||||
int selwidth = V3Number::log2b(frommsb+1-1)+1; // Width to address a bit
|
||||
|
|
@ -332,6 +332,8 @@ private:
|
|||
frommsb = varrp->varp()->arrayp(dimension)->msbConst();
|
||||
fromlsb = varrp->varp()->arrayp(dimension)->lsbConst();
|
||||
if (fromlsb>frommsb) {int t=frommsb; frommsb=fromlsb; fromlsb=t; }
|
||||
// However, if the lsb<0 we may go negative, so need more bits!
|
||||
if (fromlsb < 0) frommsb += -fromlsb;
|
||||
nodep->width(outwidth,outwidth); // Width out = width of array
|
||||
}
|
||||
int selwidth = V3Number::log2b(frommsb+1-1)+1; // Width to address a bit
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@ module t (
|
|||
output reg RESET
|
||||
);
|
||||
|
||||
neg neg (.clk(CLK));
|
||||
glbl glbl;
|
||||
|
||||
initial RESET = 1'b1;
|
||||
|
|
@ -28,3 +29,19 @@ module glbl();
|
|||
wire GSR /*verilator public*/;
|
||||
`endif
|
||||
endmodule
|
||||
|
||||
module neg (
|
||||
input clk
|
||||
);
|
||||
|
||||
reg [0:-7] i8; initial i8 = '0;
|
||||
reg [-1:-48] i48; initial i48 = '0;
|
||||
reg [63:-64] i128; initial i128 = '0;
|
||||
|
||||
always @ (posedge clk) begin
|
||||
i8 <= ~i8;
|
||||
i48 <= ~i48;
|
||||
i128 <= ~i128;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -1,16 +1,22 @@
|
|||
$version Generated by SpTraceVcd $end
|
||||
$date Wed Jun 11 19:43:32 2008
|
||||
$date Thu Sep 18 07:54:41 2008
|
||||
$end
|
||||
$timescale 1ns $end
|
||||
|
||||
$scope module TOP $end
|
||||
$var wire 1 $ CLK $end
|
||||
$var wire 1 % RESET $end
|
||||
$var wire 1 , CLK $end
|
||||
$var wire 1 - RESET $end
|
||||
$scope module v $end
|
||||
$var wire 1 $ CLK $end
|
||||
$var wire 1 , CLK $end
|
||||
$var wire 1 # RESET $end
|
||||
$scope module glbl $end
|
||||
$var wire 1 & GSR $end
|
||||
$var wire 1 + GSR $end
|
||||
$upscope $end
|
||||
$scope module neg $end
|
||||
$var wire 1 , clk $end
|
||||
$var wire 128 ' i128 [63:-64] $end
|
||||
$var wire 48 % i48 [-1:-48] $end
|
||||
$var wire 8 $ i8 [0:-7] $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
|
|
@ -19,35 +25,47 @@ $enddefinitions $end
|
|||
|
||||
#0
|
||||
1#
|
||||
0$
|
||||
1%
|
||||
1&
|
||||
b00000000 $
|
||||
b000000000000000000000000000000000000000000000000 %
|
||||
b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '
|
||||
1+
|
||||
1-
|
||||
0,
|
||||
#1
|
||||
#2
|
||||
#3
|
||||
1$
|
||||
b11111111 $
|
||||
b111111111111111111111111111111111111111111111111 %
|
||||
b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 '
|
||||
1,
|
||||
#4
|
||||
#5
|
||||
#6
|
||||
0$
|
||||
0,
|
||||
#7
|
||||
0&
|
||||
0+
|
||||
#8
|
||||
#9
|
||||
0#
|
||||
1$
|
||||
0%
|
||||
b00000000 $
|
||||
b000000000000000000000000000000000000000000000000 %
|
||||
b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '
|
||||
0-
|
||||
1,
|
||||
#10
|
||||
#11
|
||||
#12
|
||||
0$
|
||||
0,
|
||||
#13
|
||||
#14
|
||||
#15
|
||||
1$
|
||||
b11111111 $
|
||||
b111111111111111111111111111111111111111111111111 %
|
||||
b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 '
|
||||
1,
|
||||
#16
|
||||
#17
|
||||
#18
|
||||
0$
|
||||
0,
|
||||
#19
|
||||
#20
|
||||
|
|
|
|||
|
|
@ -1,16 +1,22 @@
|
|||
$version Generated by SpTraceVcd $end
|
||||
$date Wed Jun 11 19:43:32 2008
|
||||
$date Thu Sep 18 07:55:56 2008
|
||||
$end
|
||||
$timescale 1ns $end
|
||||
|
||||
$scope module TOP $end
|
||||
$var wire 1 $ CLK $end
|
||||
$var wire 1 % RESET $end
|
||||
$var wire 1 + CLK $end
|
||||
$var wire 1 , RESET $end
|
||||
$scope module v $end
|
||||
$var wire 1 $ CLK $end
|
||||
$var wire 1 + CLK $end
|
||||
$var wire 1 # RESET $end
|
||||
$scope module glbl $end
|
||||
$var wire 1 & GSR $end
|
||||
$var wire 1 - GSR $end
|
||||
$upscope $end
|
||||
$scope module neg $end
|
||||
$var wire 1 + clk $end
|
||||
$var wire 128 ' i128 [63:-64] $end
|
||||
$var wire 48 % i48 [-1:-48] $end
|
||||
$var wire 8 $ i8 [0:-7] $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
|
|
@ -19,35 +25,47 @@ $enddefinitions $end
|
|||
|
||||
#0
|
||||
1#
|
||||
0$
|
||||
1%
|
||||
1&
|
||||
b00000000 $
|
||||
b000000000000000000000000000000000000000000000000 %
|
||||
b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '
|
||||
1,
|
||||
0+
|
||||
1-
|
||||
#1
|
||||
#2
|
||||
#3
|
||||
1$
|
||||
b11111111 $
|
||||
b111111111111111111111111111111111111111111111111 %
|
||||
b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 '
|
||||
1+
|
||||
#4
|
||||
#5
|
||||
#6
|
||||
0$
|
||||
0+
|
||||
#7
|
||||
0&
|
||||
0-
|
||||
#8
|
||||
#9
|
||||
0#
|
||||
1$
|
||||
0%
|
||||
b00000000 $
|
||||
b000000000000000000000000000000000000000000000000 %
|
||||
b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '
|
||||
0,
|
||||
1+
|
||||
#10
|
||||
#11
|
||||
#12
|
||||
0$
|
||||
0+
|
||||
#13
|
||||
#14
|
||||
#15
|
||||
1$
|
||||
b11111111 $
|
||||
b111111111111111111111111111111111111111111111111 %
|
||||
b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 '
|
||||
1+
|
||||
#16
|
||||
#17
|
||||
#18
|
||||
0$
|
||||
0+
|
||||
#19
|
||||
#20
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@ our $Rerun_Args = $0." ".join(' ',@Orig_ARGV);
|
|||
|
||||
use vars qw (@Blocks
|
||||
%Vars
|
||||
%VarAttrs
|
||||
%VarsBlock
|
||||
%Tree
|
||||
@Commit
|
||||
|
|
@ -40,6 +41,7 @@ use vars qw (@Blocks
|
|||
# width=> Number of bits the output size is, 0=you tell me.
|
||||
# func=> What to put in output file
|
||||
# signed=> 0=unsigned output, 1=signed output, '%1'=signed if op1 signed
|
||||
# lsb=> LSB for variable declarations
|
||||
# em=> How to calculate emulated return value
|
||||
# %w Width of this output op ($treeref->{width})
|
||||
# %v Output value ($treeref->{val})
|
||||
|
|
@ -118,13 +120,31 @@ my %ops2 =
|
|||
(
|
||||
'VCONST'=> {pl=>'', rnd=>'rnd_const(%tr);'},
|
||||
'VIDNEW'=> {pl=>'%tv=$Vars{%i}{val};',
|
||||
rnd=>'%i=next_id(%tw); $Vars{%i}=gen_leaf(width=>%tw,trunc=>1,signed=>%tg); id_commit(%tr,"%i");1;',},
|
||||
rnd=>'%i=next_id(%tw);'
|
||||
.' $Vars{%i}=gen_leaf(width=>%tw,trunc=>1,signed=>%tg);'
|
||||
.' $VarAttrs{%i}{lsb} = rnd_lsb();'
|
||||
.' id_commit(%tr,"%i");1;',},
|
||||
'VIDOLD'=> {pl=>'%tv=$Vars{%i}{val};', rnd=>'%i=id_old(%tr);', ok_id_width=>1,},
|
||||
'VIDSAME'=> {pl=>'%tv=$Vars{%i}{val};', rnd=>'%i=id_same(%tr);', ok_id_width=>1,},
|
||||
'VRANGE'=> {pl=>'VRANGE(%tr,$Vars{%i}{val},%2v,%3v);', rnd=>'%i=next_id(%tw); my $lsb=rnd(128-%tw); my $msb=$lsb+%tw-1; %2r=val_leaf($msb); %3r=val_leaf($lsb); $Vars{%i}=gen_leaf(width=>($msb+1));'},
|
||||
'VBITSEL'=> {pl=>'VRANGE(%tr,$Vars{%i}{val},%2v,%2v);', rnd=>'%i=next_id(%tw); my $wid=min(128,rnd_width()|3); %2r=gen_leaf(width=>(log2($wid)-1),signed=>0); $Vars{%i}=gen_leaf(width=>$wid);'},
|
||||
'VBITSELP'=> {pl=>'VBITSELP(%tr,$Vars{%i}{val},%2v,%3v);', rnd=>'%i=next_id(%tw); my $wid=min(128,(%tw+rnd_width()|3)); %3r=val_leaf(%tw); my $maxval = $wid-%tw; %2r=(($maxval<4)?val_leaf($maxval):gen_leaf(width=>(log2($maxval)-1),signed=>0)); $Vars{%i}=gen_leaf(width=>$wid);'},
|
||||
'VBITSELM'=> {pl=>'VBITSELM(%tr,$Vars{%i}{val},%2v,%3v);', rnd=>'%i=next_id(%tw); my $wid=min(128,(%tw+rnd_width()|3)); %3r=val_leaf(%tw); my $maxval = $wid-1; my $minval=%tw-1; %2r=val_leaf(rnd($maxval-$minval)+$minval); $Vars{%i}=gen_leaf(width=>$wid);'}, # No easy way to make expr with specified minimum
|
||||
# These create IDs they then extract from
|
||||
'VRANGE'=> {pl=>'VRANGE(%tr,$Vars{%i}{val},%2v,%3v,$VarAttrs{%i}{lsb});',
|
||||
rnd=>'%i=next_id(%tw); $VarAttrs{%i}{lsb} = 0&&rnd_lsb();'
|
||||
.' my $lsb=rnd(128-%tw); my $msb=$lsb+%tw-1;'
|
||||
.' %2r=val_leaf($msb); %3r=val_leaf($lsb);'
|
||||
.' $Vars{%i}=gen_leaf(width=>($msb+1));'},
|
||||
'VBITSEL'=> {pl=>'VRANGE(%tr,$Vars{%i}{val},%2v,%2v,$VarAttrs{%i}{lsb});',
|
||||
rnd=>'%i=next_id(%tw); $VarAttrs{%i}{lsb} = 0&&rnd_lsb();'
|
||||
.' my $wid=min(128,rnd_width()|3);'
|
||||
.' %2r=gen_leaf(width=>(log2($wid)-1),signed=>0);'
|
||||
.' $Vars{%i}=gen_leaf(width=>$wid);'},
|
||||
'VBITSELP'=> {pl=>'VBITSELP(%tr,$Vars{%i}{val},%2v,%3v,$VarAttrs{%i}{lsb});',
|
||||
rnd=>'%i=next_id(%tw); $VarAttrs{%i}{lsb} = 0&&rnd_lsb();'
|
||||
.' my $wid=min(128,(%tw+rnd_width()|3)); %3r=val_leaf(%tw); my $maxval = $wid-%tw; %2r=(($maxval<4)?val_leaf($maxval):gen_leaf(width=>(log2($maxval)-1),signed=>0));'
|
||||
.' $Vars{%i}=gen_leaf(width=>$wid);'},
|
||||
'VBITSELM'=> {pl=>'VBITSELM(%tr,$Vars{%i}{val},%2v,%3v,$VarAttrs{%i}{lsb});',
|
||||
rnd=>'%i=next_id(%tw); $VarAttrs{%i}{lsb} = 0&&rnd_lsb();'
|
||||
.' my $wid=min(128,(%tw+rnd_width()|3)); %3r=val_leaf(%tw); my $maxval = $wid-1; my $minval=%tw-1; %2r=val_leaf(rnd($maxval-$minval)+$minval);'
|
||||
.' $Vars{%i}=gen_leaf(width=>$wid);'}, # No easy way to make expr with specified minimum
|
||||
# Unary
|
||||
'VEXTEND'=> {pl=>'VRESIZE (%tr,%1v);', rnd=>'%1r=gen_leaf(width=>rnd_width(%tw-1));'},
|
||||
'VLOGNOT'=> {pl=>'VLOGNOT (%tr,%1v);', rnd=>'%1r=gen_leaf(width=>0);'},
|
||||
|
|
@ -388,6 +408,11 @@ sub rnd_int {
|
|||
return rnd32();
|
||||
}
|
||||
|
||||
sub rnd_lsb {
|
||||
return 0;
|
||||
#return rnd(8)-4; # Not working yet
|
||||
}
|
||||
|
||||
sub rnd {
|
||||
return (int(rand($_[0]))) if ($_[0] < (1<<15));
|
||||
return (rnd32() % $_[0]);
|
||||
|
|
@ -818,12 +843,14 @@ sub decl_text {
|
|||
return sprintf " %s<%s> %s; //=%s"
|
||||
, $decl_with, $type, $var, $varref->{val}->to_Hex;
|
||||
} else {
|
||||
return sprintf " reg %s [%3d:0] %s %s; //=%s"
|
||||
return sprintf " reg %s [%3d:%3d] %s %s; //=%d'h%s"
|
||||
, ($varref->{signed}?"signed":" ")
|
||||
, ($varref->{val}->Size)-1,
|
||||
, ($varref->{val}->Size)-1+$VarAttrs{$var}{lsb},
|
||||
, $VarAttrs{$var}{lsb}
|
||||
, $var
|
||||
, (rnd(100)<30 ? "/*verilator public*/":(" "x length("/*verilator public*/")))
|
||||
, $varref->{val}->to_Hex;
|
||||
, $varref->{val}->Size
|
||||
, lc $varref->{val}->to_Hex;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -948,29 +975,35 @@ sub VPOW { # Power is a signed operation
|
|||
print "VV = $o\n";
|
||||
}
|
||||
sub VRANGE { #print "RANGE ",$_[1]->to_Hex,' ',$_[2]->to_Hex,' ',$_[3]->to_Hex," \n";
|
||||
return VRANGE_CONST($_[0],$_[1],$_[2]->Word_Read(0),$_[3]->Word_Read(0)); }
|
||||
return VRANGE_CONST($_[0],$_[1],$_[2]->Word_Read(0),$_[3]->Word_Read(0), $_[4]); }
|
||||
sub VBITSELP {
|
||||
return VRANGE_CONST($_[0],$_[1],$_[2]->Word_Read(0)+$_[3]->Word_Read(0)-1, $_[2]->Word_Read(0)); }
|
||||
return VRANGE_CONST($_[0],$_[1],$_[2]->Word_Read(0)+$_[3]->Word_Read(0)-1, $_[2]->Word_Read(0), $_[4]); }
|
||||
sub VBITSELM {
|
||||
return VRANGE_CONST($_[0],$_[1],$_[2]->Word_Read(0), $_[2]->Word_Read(0)-$_[3]->Word_Read(0)+1); }
|
||||
sub VRANGE_CONST { #print "RANGE ",$_[1]->to_Hex,' ',$_[2],' ',$_[3]," \n";
|
||||
my $size = $_[2] - $_[3] + 1;
|
||||
my $o=Bit::Vector->new($size);
|
||||
if ($_[3] < $_[1]->Size) {
|
||||
$o->Interval_Copy($_[1],0,$_[3],$size);
|
||||
}
|
||||
$_[0]{val}=$o; }
|
||||
sub VCONCAT { my $o=Bit::Vector->new($_[1]->Size + $_[2]->Size);
|
||||
$o->Interval_Copy($_[1],$_[2]->Size,0,$_[1]->Size);
|
||||
$o->Interval_Copy($_[2],0,0,$_[2]->Size);
|
||||
$_[0]{val}=$o; }
|
||||
sub VREPLIC { my $o=Bit::Vector->new($_[1]->Word_Read(0) * $_[2]->Size);
|
||||
my $pos = 0;
|
||||
for (my $time=0; $time<($_[1]->Word_Read(0)); $time++) {
|
||||
$o->Interval_Copy($_[2],$pos,0,$_[2]->Size);
|
||||
$pos += $_[2]->Size;
|
||||
}
|
||||
$_[0]{val}=$o; }
|
||||
return VRANGE_CONST($_[0],$_[1],$_[2]->Word_Read(0), $_[2]->Word_Read(0)-$_[3]->Word_Read(0)+1, $_[4]); }
|
||||
sub VRANGE_CONST {
|
||||
# to, from, msb, lsb, variable_lsb_to_subtract
|
||||
#print "RANGE ",$_[1]->to_Hex,' ',$_[2],' ',$_[3],' ',$_[4]," \n";
|
||||
my $size = $_[2] - $_[3] + 1;
|
||||
my $o=Bit::Vector->new($size);
|
||||
if ($_[3] < $_[1]->Size) {
|
||||
$o->Interval_Copy($_[1],0,$_[3]-$_[4],$size);
|
||||
}
|
||||
$_[0]{val}=$o; }
|
||||
sub VCONCAT {
|
||||
my $o=Bit::Vector->new($_[1]->Size + $_[2]->Size);
|
||||
$o->Interval_Copy($_[1],$_[2]->Size,0,$_[1]->Size);
|
||||
$o->Interval_Copy($_[2],0,0,$_[2]->Size);
|
||||
$_[0]{val}=$o;
|
||||
}
|
||||
sub VREPLIC {
|
||||
my $o=Bit::Vector->new($_[1]->Word_Read(0) * $_[2]->Size);
|
||||
my $pos = 0;
|
||||
for (my $time=0; $time<($_[1]->Word_Read(0)); $time++) {
|
||||
$o->Interval_Copy($_[2],$pos,0,$_[2]->Size);
|
||||
$pos += $_[2]->Size;
|
||||
}
|
||||
$_[0]{val}=$o;
|
||||
}
|
||||
|
||||
#######################################################################
|
||||
#######################################################################
|
||||
|
|
|
|||
Loading…
Reference in New Issue