Report error if port declaration is missing; bug32.

Changes

@@ -8,6 +8,8 @@ indicates the contributor was also the author of the fix; Thanks!
 ***  Suppress width warnings between constant strings and wider vectors.
      [Rodney Sinclair]
 
+**** Report error if port declaration is missing; bug32. [Guy-Armand Kamendje]
+
 * Verilator 3.671 2008/09/19
 
 **   SystemC uint64_t pins are now the default instead of sc_bv<64>.

src/V3Link.cpp

@@ -50,6 +50,7 @@ private:
     //   AstNodeFTask::userp()	// V3SymTable*    Local Symbol table
     //   AstBegin::userp()	// V3SymTable*    Local Symbol table
     //   AstVar::userp()	// V3SymTable*    Table used to create this variable
+    //   AstVar::user2p()	// bool		  True if port set for this variable
 
     // ENUMS
     enum IdState {		// Which loop through the tree
@@ -60,6 +61,7 @@ private:
     // STATE
     // Below state needs to be preserved between each module call.
     AstModule*	m_modp;		// Current module
+    AstNodeFTask* m_ftaskp;	// Current function/task
     IdState	m_idState;	// Id linking mode (find or resolve)
     int		m_paramNum;	// Parameter number, for position based connection
     V3SymTable* m_curVarsp;	// Symbol table of variables and tasks under table we're inserting into
@@ -106,6 +108,7 @@ private:
     // VISITs
     virtual void visit(AstNetlist* nodep, AstNUser*) {
 	AstNode::userClearTree();
+	AstNode::user2ClearTree();
 	// Look at all modules, and store pointers to all module names
 	for (AstModule* modp = v3Global.rootp()->modulesp(); modp; modp=modp->nextp()->castModule()) {
 	    V3SymTable* symp = new V3SymTable(NULL);
@@ -189,6 +192,11 @@ private:
 		}
 	    }
 	}
+	if (m_idState==ID_RESOLVE) {
+	    if (nodep->isIO() && !m_ftaskp && !nodep->user2()) {
+		nodep->v3error("Input/output/inout does not appear in port list: "<<nodep->prettyName());
+	    }
+	}
     }
     virtual void visit(AstVarRef* nodep, AstNUser*) {
 	// VarRef: Resolve its reference
@@ -236,7 +244,9 @@ private:
 		    m_curVarsp->insert(newvarp->name(), newvarp);
 		}
 	    }
+	    m_ftaskp = nodep;
 	    nodep->iterateChildren(*this);
+	    m_ftaskp = NULL;
 	}
 	m_curVarsp = upperVarsp;
 	if (m_idState==ID_FIND) {
@@ -336,6 +346,7 @@ private:
 		nodep->v3error("Pin is not a in/out/inout: "<<nodep->prettyName());
 	    } else {
 		m_curVarsp->insert("__pinNumber"+cvtToStr(nodep->pinNum()), refp);
+		refp->user2(true);
 	    }
 	    // Ports not needed any more
 	    nodep->unlinkFrBack()->deleteTree();  nodep=NULL;
@@ -422,6 +433,7 @@ public:
 	m_curVarsp = NULL;
 	m_cellVarsp = NULL;
 	m_modp = NULL;
+	m_ftaskp = NULL;
 	m_paramNum = 0;
 	m_beginNum = 0;
 	//

test_regress/t/t_func_lib_sub.v

@@ -5,7 +5,7 @@
 
 `define zednkw 200
 
-module BreadAddrDP (zfghtn, cjtmau, knquim, kqxkkr);
+module BreadAddrDP (zfghtn, cjtmau, vipmpg, knquim, kqxkkr);
 input zfghtn;
 input [4:0] cjtmau;
 input vipmpg;

test_regress/t/t_var_pinsizes.v

@@ -7,8 +7,10 @@
 // verilator lint_on IMPERFECTSCH
 
 module t (/*AUTOARG*/
+   // Outputs
+   o1, o8, o16, o32, o64, o65,
    // Inputs
-   clk
+   clk, i1, i8, i16, i32, i64, i65
    );
 
    input clk;

test_regress/t/t_var_port_bad.pl

@@ -0,0 +1,17 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 fails=>1,
+	 expect=>
+'%Error: t/t_var_port_bad.v:\d+: Input/output/inout does not appear in port list: b
+%Error: Exiting due to.*',
+	 );
+
+ok(1);
+1;

test_regress/t/t_var_port_bad.v

@@ -0,0 +1,16 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2008 by Wilson Snyder.
+
+module t;
+   subok subok (.a(1'b1), .b(1'b0));
+   sub sub (.a(1'b1), .b(1'b0));
+endmodule
+
+module subok (input a,b);
+endmodule
+
+module sub (a);
+   input a, b;
+endmodule