Veripool API Bot
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1f67080a1f
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Tests: Verilog format
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2026-03-09 21:39:16 -04:00 |
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Veripool API Bot
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ce4d35aa85
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Verilog format
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2026-03-03 07:21:24 -05:00 |
Wilson Snyder
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7c6c6a684b
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Add SPDX copyright identifiers, and get 'reuse' clean. No functional change.
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2026-01-26 20:24:34 -05:00 |
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Wilson Snyder
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e5b94046aa
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Tests: t_lint_width.v update
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2026-01-09 19:31:35 -05:00 |
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Wilson Snyder
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3b1a7af74d
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Fix WIDTHEXTEND suppression on add/sub with single-bit signal.
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2026-01-09 00:25:12 -05:00 |
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Wilson Snyder
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77e68acf54
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Suppress WIDTH warning on negate using carry bit (#2395). [Peter Monsson]
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2022-02-13 15:27:31 -05:00 |
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Wilson Snyder
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1ce360ed5b
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Add SPDX license identifiers. No functional change.
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2020-03-21 11:24:24 -04:00 |
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Wilson Snyder
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d4614c290e
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Fix WIDTH warning on </<= of narrower value, #2141.
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2020-01-28 20:10:10 -05:00 |
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Wilson Snyder
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cfd07ccd34
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Suppress WIDTH warnings when adding/subtracting 1'b1.
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2010-12-02 14:00:43 -05:00 |