Commit Graph

8649 Commits

Author SHA1 Message Date
Sergey Fedorov ece4469869
Fix PowerPC support (#6292) 2025-08-15 11:25:32 -07:00
Geza Lore 9c11f5e05d Fix DFG circular driver tracing 2025-08-15 10:20:20 +01:00
Mateusz Gancarz e753480b19
Fix no matching function calls for randomized `VlWide` in unpacked and dynamic arrays (#6290) 2025-08-14 05:19:33 -07:00
Wilson Snyder 047a12cc62 Fix variables hiding package imports (#6289). 2025-08-13 18:05:37 -04:00
Wilson Snyder 75c6745868 Test driver.py: Pass-through +verilator+ arguments to runtime 2025-08-12 19:32:56 -04:00
Wilson Snyder 60cbbf0ec1 Add error on mismatching prototypes (#6207). 2025-08-11 19:50:47 -04:00
Geza Lore 762c5f573c Improve DFG to enable breaking more combinational cycles 2025-08-11 09:44:31 +01:00
Geza Lore 7696b0651c Internals: Improve DFG dumping functions 2025-08-10 16:48:40 +01:00
Wilson Snyder e6e52dd60a Tests: Fix t_constraint_nosolver_bad.py (#6273) 2025-08-10 08:43:04 -04:00
Wilson Snyder eb80db9397 Clarify extern error message 2025-08-10 08:38:26 -04:00
Wilson Snyder 641dd756c0 Add check for mis-assignment of dynamic/automatics per IEEE 2025-08-10 07:23:28 -04:00
Wilson Snyder a74a3bb689 Internals: No need for 'if' before VL_FFLUSH_I 2025-08-10 06:13:18 -04:00
Geza Lore d28436dccc
Fix stray ']' in Verilog code output for non-constant select (#6277) 2025-08-09 14:59:58 +01:00
Wilson Snyder 3ca1c9b6dd Internals: Fix and enforce brace new constructors. No functional change intended. 2025-08-08 18:21:12 -04:00
Wilson Snyder 1eccfa64b5 Commentary 2025-08-08 17:54:48 -04:00
Wilson Snyder 1d05028087 Add compiler warning disable '-Wno-int-in-bool-context' 2025-08-08 17:54:48 -04:00
Geza Lore 16d32cdd4a
Internals: Refactor Ast to Dfg conversion for reusability. (#6276)
This is mainly code motion, with minimal algorithmic changes to
facilitate reusing parts in future code. No functional change intended.
2025-08-08 22:53:12 +01:00
Wilson Snyder d1f851e1e1 Internals: Optimize empty 'if' into StmtExpr 2025-08-08 05:10:40 -04:00
Wilson Snyder 6a225d5d00 Internals: Remove AstSysFuncAsTask 2025-08-08 05:09:54 -04:00
Wilson Snyder b12b1c9658 Commentary: Changes update 2025-08-08 05:09:16 -04:00
Geza Lore dbb8cbece2 CI: Improve RTLMeter failure issue body (#6275) 2025-08-08 09:13:29 +01:00
Geza Lore 9ddbf5f4b8 CI: Only raise RTLMeter failure issue on failure 2025-08-08 08:07:55 +01:00
Geza Lore b2388faa5e
CI: Add running RTLMeter workflow on selective PRs (#6271)
Runs RTLMeter on PRs if the PR has the 'pr: rtlmeter' label applied to
it. This should make it easy to selectively require the RTLMeter
workflows to pass on a PR that is potentially invasive, per our own
judgement.
2025-08-07 19:30:43 +01:00
Geza Lore 188a12f609
CI: Add raising GitHub issue on failure of scheduled RTLMeter job (#6270) 2025-08-07 18:17:00 +01:00
Todd Strader 6bd6663dc9
Fix spurious VPI value change callbacks (#6274) 2025-08-07 16:37:33 +01:00
Artur Bieniek 5b7188fcaf
Fix same variable on the RHS forced to two different LHSs. (#6269) 2025-08-06 17:37:00 -04:00
github action dc049fdd74 Apply 'make format' 2025-08-06 21:30:37 +00:00
Michael Bedford Taylor 218659f4e8
Support parameter resolution of 1D unpacked array slices (#6257) (#6268) 2025-08-06 17:29:40 -04:00
Igor Zaworski 6c1cfc68cf
Fix dynamic cast purity (#6267)
Signed-off-by: Igor Zaworski <izaworski@internships.antmicro.com>
2025-08-06 07:09:44 -04:00
Wilson Snyder fbaff52668 Change runtime to exit() instead of abort(), unless under +verilated+debug. 2025-08-05 18:43:29 -04:00
Wilson Snyder 06c570e159 Commentary 2025-08-05 17:56:12 -04:00
Wilson Snyder c005486acf Support by ignoring delay2 on UDPs 2025-08-05 17:34:42 -04:00
Wilson Snyder 6467351752 Add error on class 'function static'. 2025-08-05 17:12:00 -04:00
Wilson Snyder 4bd17f0a6f Commentary: Changes update 2025-08-05 17:08:09 -04:00
Wilson Snyder 870c398094 Fix incorrect Non-ANSI I/O declaration conflict error (#6258) broke with #bd1ac038 2025-08-05 16:33:28 -04:00
Geza Lore 86c56e8e14 Fix true cycle detection in DFG 2025-08-05 15:04:07 +01:00
Geza Lore 25d968b833 Fix infinite loop in VString::replaceSubstr
If the replaced string was a suffix of the replacement, we used to get
an infinite loop.
2025-08-05 14:41:38 +01:00
Geza Lore 2c41a7bbf6 Adjust make test-snap / make test-diff rules 2025-08-05 14:41:38 +01:00
Geza Lore 158a54a7ff
Defer deletion of eliminated Ast variables until end of Dfg pass. (#6263)
This is currently unnecessary but future patch will depend on it.
2025-08-05 14:29:33 +01:00
Geza Lore 8c9a4fec83 Emit memory addresses of vertices in Dfg dumps 2025-08-05 13:03:57 +01:00
Geza Lore 53332ae03e
Unify the two DFG cycle finding algorithms. (#6262)
Both V3DfgBreakCycles.cpp and V3DfgDecomposition.cpp used to contain an
implementation of the same algorithm to color strongly connected
components. Now there is only one, and it lives in V3DfgColorSCCs.cpp.
2025-08-05 13:03:30 +01:00
Geza Lore 4a5935d248
Merge DFG components made acyclic into the original acyclic sub-graph. (#6261)
After making a cyclic DFG component acyclic, merge that component back
into the acyclic sub-graph of the input graph. This enables optimizing
through the components that were made acyclic in their larger context.
2025-08-05 12:11:02 +01:00
Geza Lore 78c9e7773a
Allow more variable removal in scoped DFG (#6260) 2025-08-05 11:18:33 +01:00
Geza Lore d2edab458e
Refactor Dfg variable flags (#6259)
Store all flags in a DfgVertexVar relating to the underlying
AstVar/AstVarScope stored via AstNode::user1(). user2/user3/user4 are
then usable by DFG algorithms as needed.
2025-08-05 10:24:54 +01:00
Geza Lore d415757b0e Remove unhelpful DFG debug dumps 2025-08-05 05:06:44 +01:00
Ryszard Rozak 7d2b6bd921
Internals: Optimize updates of Vtogcov signals. No functional change intended. (#6110) 2025-08-04 13:29:56 +01:00
Wilson Snyder 52ac3b3a0d Add error on too many pattern members for structure 2025-08-03 17:26:51 -04:00
Wilson Snyder f106c1eaec Fix genvar check to be more strict about generate-for usage only 2025-08-03 16:57:12 -04:00
Wilson Snyder 309129ebcf Add PARAMNODEFAULT error, for parameters without defaults. 2025-08-03 15:27:37 -04:00
Geza Lore deed20fb78
Fix partial DFG conversion of concat assignments (#6255)
When we had a `{a, b} = ...`, and the DFG conversion of `a = ...`
succeeded, but `b = ...` failed, we still used to include `a = ...` in
the DFG, which then caused a spurious multi-driver error for `a` on
a subsequent DFG pass, as the original `{a, b} = ...` was still present
in the Ast, but we also had the extra `a = ...` from converting out of
DFG on the previous pass.

In this patch we only convert assignments with a concatenation on the
LHS, if all target LValues can be converted into DFG.

This is the proper fix for #4231
2025-08-03 14:52:20 +01:00