Commit Graph

798 Commits

Author SHA1 Message Date
Wilson Snyder a9f95f2f08 Fix false CONSTVAR error on initializers (#4992). 2025-09-09 19:27:43 -04:00
Wilson Snyder f8f5f8f84b Commentary: Fix warning documentation, add consistency test. 2025-09-09 19:14:48 -04:00
Wilson Snyder 1fd9f3ce92 Commentary: Changes update 2025-09-09 17:47:26 -04:00
Geza Lore 056c3ee331
Testing: Add --enable-asan configure option to compile with AddressSanitizer (#6404) 2025-09-09 08:55:49 +01:00
Wilson Snyder aa28a8d1e1 Fix cell scoping performance (#6059). 2025-09-06 08:35:07 -04:00
Wilson Snyder f41e36b99f Commentary: Convert docs examples to 2 space indents. 2025-09-06 07:51:49 -04:00
Jakub Wasilewski a364704e3a
Improve `covergroup with function sample` handling (#6387) 2025-09-05 13:16:30 -04:00
Wilson Snyder 7d3c58d21c Docs: Notes about `--x-initial-edge` (#6377 comment) 2025-09-04 09:09:54 -04:00
Wilson Snyder 7a4049b683 Fix docs HTML format from last commit 2025-09-03 19:28:17 -04:00
Wilson Snyder e2b9cadb1d Commentary: Changes update 2025-09-03 18:55:41 -04:00
Wilson Snyder 98c7089f5b Commentary: CONTRIBUTORS for dependabot 2025-09-03 14:59:20 -04:00
Lan Zongwei 2aa260a03b
Fix V3Hash MacOS ambiguity again (#6350) 2025-08-31 09:54:13 -04:00
Wilson Snyder 7bb38d21b9 Commentary: Changes update 2025-08-30 17:58:12 -04:00
Congcong Cai ca2c40347b
Fix undefined weak link for Apple GCC etc (#6348) 2025-08-30 14:25:20 -04:00
Wilson Snyder ac2859bf24
Internals: Upgrade to clang-format-18 (#6333) 2025-08-25 20:47:48 -04:00
Wilson Snyder 703f0d8c5d Commentary: spelling 2025-08-25 18:47:08 -04:00
Geza Lore 636a6b8cd2
Optimize complex combinational logic in DFG (#6298)
This patch adds DfgLogic, which is a vertex that represents a whole,
arbitrarily complex combinational AstAlways or AstAssignW in the
DfgGraph.

Implementing this requires computing the variables live at entry to the
AstAlways (variables read by the block), so there is a new
ControlFlowGraph data structure and a classical data-flow analysis based
live variable analysis to do that at the variable level (as opposed to
bit/element level).

The actual CFG construction and live variable analysis is best effort,
and might fail for currently unhandled constructs or data types. This
can be extended later.

V3DfgAstToDfg is changed to convert the Ast into an initial DfgGraph
containing only DfgLogic, DfgVertexSplice and DfgVertexVar vertices.

The DfgLogic are then subsequently synthesized into primitive operations
by the new V3DfgSynthesize pass, which is a combination of the old
V3DfgAstToDfg conversion and new code to handle AstAlways blocks with
complex flow control.

V3DfgSynthesize by default will synthesize roughly the same constructs
as V3DfgAstToDfg used to handle before, plus any logic that is part of a
combinational cycle within the DfgGraph. This enables breaking up these
cycles, for which there are extensions to V3DfgBreakCycles in this patch
as well. V3DfgSynthesize will then delete all non synthesized or non
synthesizable DfgLogic vertices and the rest of the Dfg pipeline is
identical, with minor changes to adjust for the changed representation.

Because with this change we can now eliminate many more UNOPTFLAT, DFG
has been disabled in all the tests that specifically target testing the
scheduling and reporting of circular combinational logic.
2025-08-19 15:06:38 +01:00
Geza Lore 0bf9fc270f
Iternals: Remove AstAssignPre/AstAssignPost (#6307)
Replace with AstAlwaysPre/AstAlwaysPost with AstAssign under them.

Step towards #6280
2025-08-19 09:27:59 +01:00
Wilson Snyder c90f9e53b7
Add ALWNEVER warning, for `always @*` that never execute (#6291) (#6303) 2025-08-18 12:00:53 -04:00
Wilson Snyder 48a12fb0f4 Document and test `+verilator+rand+reset+2` usage (#6285 partial) 2025-08-16 11:47:19 -04:00
Wilson Snyder 000d697b51 Commentary: Changes update 2025-08-16 09:08:09 -04:00
Sergey Fedorov ece4469869
Fix PowerPC support (#6292) 2025-08-15 11:25:32 -07:00
Wilson Snyder 75c6745868 Test driver.py: Pass-through +verilator+ arguments to runtime 2025-08-12 19:32:56 -04:00
Wilson Snyder 60cbbf0ec1 Add error on mismatching prototypes (#6207). 2025-08-11 19:50:47 -04:00
Michael Bedford Taylor 218659f4e8
Support parameter resolution of 1D unpacked array slices (#6257) (#6268) 2025-08-06 17:29:40 -04:00
Wilson Snyder 06c570e159 Commentary 2025-08-05 17:56:12 -04:00
Wilson Snyder 4bd17f0a6f Commentary: Changes update 2025-08-05 17:08:09 -04:00
Wilson Snyder 309129ebcf Add PARAMNODEFAULT error, for parameters without defaults. 2025-08-03 15:27:37 -04:00
Rodrigo Batista de Moraes d0f0919830
Fix write of 0 in '%c' (#6248) (#6249) 2025-08-01 07:54:18 +02:00
Wilson Snyder 5faaa7ec58 Commentary (#6246) 2025-07-31 18:09:43 -04:00
Wilson Snyder 833c31b031 Add `-DVERILATOR=1` definition to compiler flags when using verilated.mk. 2025-07-28 18:01:50 -04:00
Wilson Snyder 7c71bdf2d6 Commentary 2025-07-27 15:55:59 -04:00
Wilson Snyder 55b836e25a Commentary: Changes update 2025-07-27 09:44:51 -04:00
George Polack f1826a7c20
Support Verilog real to SystemC double (#6136) (#6158) 2025-07-25 20:05:36 +02:00
Danny Oler 74d4b0c0ea
Fix automatic task variables in unrolled loops with forks (#6194) (#6201). 2025-07-21 19:28:50 -04:00
Max Wipfli a50ea2a1a6
Optimize 2 ** X to 1 << X if base is signed (#6203) 2025-07-20 09:56:34 -04:00
Wilson Snyder 078bb21a89 Add wire data type checking per IEEE. 2025-07-20 07:21:30 -04:00
Wilson Snyder f535a73ea7 Commentary: Changes update 2025-07-19 21:12:23 -04:00
Ibrahim Burak Yorulmaz 9d146eae16
Fix VPI signal range order (#6189) (#6200) 2025-07-19 20:22:02 -04:00
Wilson Snyder 7d43a935bd Add SPECIFYIGN warning for specify constructs that were previously silently ignored. 2025-07-18 19:32:34 -04:00
Wilson Snyder 7a32771c7e Commentary: Changes update 2025-07-16 17:26:01 -04:00
Wilson Snyder 1f0357ba93 Add NOEFFECT warning, replacing previous `foreach` error. 2025-07-16 08:18:57 -04:00
Wilson Snyder 2f199f20cf Add ENUMITEMWIDTH error, and apply to X-extended and ranged values. 2025-07-12 14:14:17 -04:00
Wilson Snyder cefe1845df Commentary: Changes update 2025-07-11 21:53:29 -04:00
Artur Bieniek 4dc6a31276
Fix omitting error when assigning to an input (#6169) 2025-07-10 20:37:55 -04:00
Geza Lore ce77bac99a
Break some combinational cycles in DFG (#6168)
Added an algorithm that can break some combinational cycles in DFG, by
attempting to trace driver logic until we escape the cycle. This can
eliminate a decent portion of UNOPTFLAT warnings. E.g. due to this code:

```systemverilog
assign a[0] = .....;
assign a[1] = ~a[0];
```
2025-07-10 18:46:45 +01:00
Wilson Snyder 1f0e767b61 Commentary: Changes update 2025-07-08 17:37:21 -04:00
Igor Zaworski 5777ab75c7
Fix crash with --dumpi-V3LinkDot without --debug (#6159) 2025-07-08 10:28:17 -04:00
Wilson Snyder f77af4e6f6 Important: Change `--assert` to be the default; use `--no-assert` for legacy behavior and faster runtimes. 2025-07-03 19:36:28 -04:00
Geza Lore 7a3f1f16ca
Optimize DFG before V3Gate (#6141) 2025-07-01 17:55:08 -04:00