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Commentary: Convert docs examples to 2 space indents.

This commit is contained in:
Wilson Snyder 2025-09-06 07:51:49 -04:00
parent 85454f6083
commit f41e36b99f
37 changed files with 305 additions and 305 deletions
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2
docs/gen/ex_BADVLTPRAGMA_faulty.rst
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@ -2,4 +2,4 @@
.. code-block:: sv
:emphasize-lines: 1
// verilator lintt_off WIDTH //<--- Warning (lint_off misspelled)
// verilator lintt_off WIDTH //<--- Warning (lint_off misspelled)

6
docs/gen/ex_BADVLTPRAGMA_msg.rst
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@ -2,6 +2,6 @@
.. code-block::
:emphasize-lines: 1,2
%Error-BADVLTPRAGMA: example.v:1:4 Unknown verilator comment: '/*verilator lintt_off WIDTH <--- Warning (lint_off misspelled)*/'
7 | /*verilator lintt_off WIDTH <--- Warning (lint_off misspelled)*/
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
%Error-BADVLTPRAGMA: example.v:1:3 Unknown verilator comment: '/*verilator lintt_off WIDTH <--- Warning (lint_off misspelled)*/'
7 | /*verilator lintt_off WIDTH <--- Warning (lint_off misspelled)*/
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

4
docs/gen/ex_DIDNOTCONVERGE_faulty.rst
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@ -2,5 +2,5 @@
.. code-block:: sv
:linenos:
always_comb b = ~a;
always_comb a = b;
always_comb b = ~a;
always_comb a = b;

12
docs/gen/ex_MULTIDRIVEN_faulty.rst
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@ -3,9 +3,9 @@
:linenos:
:emphasize-lines: 2,5
always @(posedge clk) begin
out2[7:0] <= d0; // <--- Warning
end
always @(negedge clk) begin
out2[15:8] <= d0; // <--- Warning
end
always @(posedge clk) begin
out2[7:0] <= d0; // <--- Warning
end
always @(negedge clk) begin
out2[15:8] <= d0; // <--- Warning
end

6
docs/gen/ex_MULTIDRIVEN_msg.rst
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@ -1,6 +1,6 @@
.. comment: generated by t_lint_multidriven_bad
.. code-block::
%Warning-MULTIDRIVEN: example.v:1:22 Signal has multiple driving blocks with different clocking: 'out2'
example.v:1:7 ... Location of first driving block
example.v:1:7 ... Location of other driving block
%Warning-MULTIDRIVEN: example.v:1:21 Signal has multiple driving blocks with different clocking: 'out2'
example.v:1:5 ... Location of first driving block
example.v:1:5 ... Location of other driving block

12
docs/gen/ex_PROCASSINIT_faulty.rst
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@ -3,10 +3,10 @@
:linenos:
:emphasize-lines: 1,5
logic flop_out = 1; // <--- Warning
logic flop_out = 1; // <--- Warning
always @(posedge clk, negedge reset_l) begin
if (enable) begin
flop_out <= ~in; // <--- Use of initialized
end
end
always @(posedge clk, negedge reset_l) begin
if (enable) begin
flop_out <= ~in; // <--- Use of initialized
end
end

18
docs/gen/ex_PROCASSINIT_fixed.rst
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@ -3,13 +3,13 @@
:linenos:
:emphasize-lines: 5
logic flop2_out;
logic flop2_out;
always @(posedge clk, negedge reset_l) begin
if (!reset_l) begin
flop2_out <= '1; // <--- Added reset init
end
else if (enable) begin
flop2_out <= ~in;
end
end
always @(posedge clk, negedge reset_l) begin
if (!reset_l) begin
flop2_out <= '1; // <--- Added reset init
end
else if (enable) begin
flop2_out <= ~in;
end
end

14
docs/gen/ex_PROCASSINIT_msg.rst
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@ -1,12 +1,12 @@
.. comment: generated by t_lint_procassinit_bad
.. code-block::
%Warning-PROCASSINIT: example.v:1:21 Procedural assignment to declaration with initial value: 'flop_out'
%Warning-PROCASSINIT: example.v:1:20 Procedural assignment to declaration with initial value: 'flop_out'
: ... note: In instance 't'
: ... Location of variable initialization
26 | logic flop_out = 1;
| ^
example.v:1:10 ... Location of variable process write
: ... Perhaps should initialize instead using a reset in this process
30 | flop_out <= ~in;
| ^~~~~~~~
26 | logic flop_out = 1;
| ^
example.v:1:7 ... Location of variable process write
: ... Perhaps should initialize instead using a reset in this process
30 | flop_out <= ~in;
| ^~~~~~~~

2
docs/gen/ex_STMTDLY_faulty.rst
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@ -2,4 +2,4 @@
.. code-block:: sv
:emphasize-lines: 1
#100 $finish; //<--- Warning
#100 $finish; //<--- Warning

2
docs/gen/ex_STMTDLY_msg.rst
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@ -1,4 +1,4 @@
.. comment: generated by t_lint_stmtdly_bad
.. code-block::
%Warning-STMTDLY: example.v:1:7 Ignoring delay on this statement due to --no-timing
%Warning-STMTDLY: example.v:1:5 Ignoring delay on this statement due to --no-timing

2
docs/gen/ex_USERERROR_faulty.rst
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@ -1,4 +1,4 @@
.. comment: generated by t_assert_comp_bad
.. code-block:: sv
$error("User elaboration-time error");
$error("User elaboration-time error");

2
docs/gen/ex_USERERROR_msg.rst
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@ -1,4 +1,4 @@
.. comment: generated by t_assert_comp_bad
.. code-block::
%Warning-USERERROR: example.v:1:7 User elaboration-time error
%Warning-USERERROR: example.v:1:5 User elaboration-time error

2
docs/gen/ex_USERFATAL_faulty.rst
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@ -1,4 +1,4 @@
.. comment: generated by t_assert_comp_bad
.. code-block:: sv
$fatal(0, "User elaboration-time fatal");
$fatal(0, "User elaboration-time fatal");

2
docs/gen/ex_USERFATAL_msg.rst
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@ -1,4 +1,4 @@
.. comment: generated by t_assert_comp_bad
.. code-block::
%Warning-USERFATAL: example.v:1:7 User elaboration-time fatal
%Warning-USERFATAL: example.v:1:5 User elaboration-time fatal

2
docs/gen/ex_USERINFO_faulty.rst
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@ -1,4 +1,4 @@
.. comment: generated by t_assert_comp_bad
.. code-block:: sv
$info("User elaboration-time info");
$info("User elaboration-time info");

2
docs/gen/ex_USERINFO_msg.rst
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@ -1,4 +1,4 @@
.. comment: generated by t_assert_comp_bad
.. code-block::
-Info: example.v:1:7 User elaboration-time info
-Info: example.v:1:5 User elaboration-time info

2
docs/gen/ex_USERWARN_faulty.rst
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@ -1,4 +1,4 @@
.. comment: generated by t_assert_comp_bad
.. code-block:: sv
$warning("User elaboration-time warning");
$warning("User elaboration-time warning");

2
docs/gen/ex_USERWARN_msg.rst
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@ -1,4 +1,4 @@
.. comment: generated by t_assert_comp_bad
.. code-block::
%Warning-USERWARN: example.v:1:7 User elaboration-time warning
%Warning-USERWARN: example.v:1:5 User elaboration-time warning

2
docs/gen/ex_VARHIDDEN_faulty.rst
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@ -4,5 +4,5 @@
:emphasize-lines: 2
module t;
integer t; //<--- Warning ('t' hidden by module 't')
integer t; //<--- Warning ('t' hidden by module 't')
endmodule

2
docs/gen/ex_VARHIDDEN_msg.rst
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@ -1,5 +1,5 @@
.. comment: generated by t_var_bad_hide_docs
.. code-block::
%Warning-VARHIDDEN: example.v:2:12 Declaration of signal hides declaration in upper scope: 't'
%Warning-VARHIDDEN: example.v:2:11 Declaration of signal hides declaration in upper scope: 't'
example.v:1:8 ... Location of original declaration

12
docs/guide/connecting.rst
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@ -184,7 +184,7 @@ Verilog, put in our.v:
import "DPI-C" function int add (input int a, input int b);
initial begin
$display("%x + %x = %x", 1, 2, add(1,2));
$display("%x + %x = %x", 1, 2, add(1,2));
endtask
Then after Verilating, Verilator will create a file Vour__Dpi.h with the
@ -225,8 +225,8 @@ called from C++:
export "DPI-C" task publicSetBool;
task publicSetBool;
input bit in_bool;
var_bool = in_bool;
input bit in_bool;
var_bool = in_bool;
endtask
Then after Verilating, Verilator will create a file Vour__Dpi.h with the
@ -294,11 +294,11 @@ wrapper:
import "DPI-C" context function void dpi_that_accesses_din();
always @(...)
dpi_din_args(din);
dpi_din_args(din);
task dpi_din_args(input din);
/* verilator no_inline_task */
dpi_that_accesses_din();
// verilator no_inline_task
dpi_that_accesses_din();
endtask

10
docs/guide/extensions.rst
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@ -240,7 +240,7 @@ or "`ifdef`"'s may break other tools.
reg enable_r /*verilator clock_enable*/;
wire gated_clk = clk & enable_r;
always_ff @(posedge clk)
enable_r <= enable_early;
enable_r <= enable_early;
The clock_enable attribute will cause the clock gate to be ignored in
the scheduling algorithm, sometimes required for correct clock behavior,
@ -331,8 +331,8 @@ or "`ifdef`"'s may break other tools.
// Note the placement of the semicolon above
always_comb begin
if (....) begin
splitme = ....;
other assignments
splitme = ....;
other assignments
end
end
@ -346,13 +346,13 @@ or "`ifdef`"'s may break other tools.
// All assignments excluding those to splitme
always_comb begin
if (....) begin
other assignments
other assignments
end
end
// All assignments to splitme
always_comb begin
if (....) begin
splitme = ....;
splitme = ....;
end
end

42
docs/guide/install.rst
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@ -19,7 +19,7 @@ started. (Note distribution packages almost never have the most recent
Verilator version, so we recommend following :ref:`Git Install` below,
instead.) To install as a package:
.. code-block:: shell
.. code-block:: bash
apt-get install verilator # On Ubuntu
@ -56,7 +56,7 @@ options and details, see :ref:`Detailed Build Instructions` below.
In brief, to install from git:
.. code-block:: shell
.. code-block:: bash
# Prerequisites:
#sudo apt-get install git help2man perl python3 make autoconf g++ flex bison ccache
@ -109,7 +109,7 @@ Install Prerequisites
To build or run Verilator, you need these standard packages:
.. code-block:: shell
.. code-block:: bash
sudo apt-get install git help2man perl python3 make
sudo apt-get install g++ # Alternatively, clang
@ -120,27 +120,27 @@ To build or run Verilator, you need these standard packages:
For SystemC:
.. code-block:: shell
.. code-block:: bash
sudo apt-get install libsystemc libsystemc-dev
For constraints:
.. code-block:: shell
.. code-block:: bash
sudo apt-get install z3 # Optional solver
The following is optional but is recommended for nicely rendered command line
help when running Verilator:
.. code-block:: shell
.. code-block:: bash
sudo apt-get install perl-doc
To build or run Verilator, the following are optional but should be installed
for good performance:
.. code-block:: shell
.. code-block:: bash
sudo apt-get install ccache # If present at build, needed for run
sudo apt-get install mold # If present at build, needed for run
@ -149,13 +149,13 @@ for good performance:
To build Verilator you will need to install these packages; these do not
need to be present to run Verilator:
.. code-block:: shell
.. code-block:: bash
sudo apt-get install git autoconf flex bison
Those developing Verilator itself also need these (see internals.rst):
.. code-block:: shell
.. code-block:: bash
sudo apt-get install clang clang-format-18 cmake gdb gprof graphviz lcov
sudo apt-get install python3-clang python3-distro yapf3 bear jq
@ -185,7 +185,7 @@ To make use of Verilator FST tracing you will want `GTKwave
<https://gtkwave.sourceforge.net/>`__ installed, however this is not
required at Verilator build time.
.. code-block:: shell
.. code-block:: bash
sudo apt-get install gtkwave # Optional Waveform viewer
@ -209,14 +209,14 @@ Obtain Sources
Get the sources from the git repository: (You need to do this only once,
ever.)
.. code-block:: shell
.. code-block:: bash
git clone https://github.com/verilator/verilator # Only first time
## Note the URL above is not a page you can see with a browser; it's for git only
Enter the checkout and determine what version/branch to use:
.. code-block:: shell
.. code-block:: bash
cd verilator
git pull # Make sure we're up-to-date
@ -231,7 +231,7 @@ Auto Configure
Create the configuration script:
.. code-block:: shell
.. code-block:: bash
autoconf # Create ./configure script
@ -257,7 +257,7 @@ directory (don't run ``make install``). This allows the easiest
experimentation and upgrading, and allows many versions of Verilator to
co-exist on a system.
.. code-block:: shell
.. code-block:: bash
export VERILATOR_ROOT=`pwd` # if your shell is bash
setenv VERILATOR_ROOT `pwd` # if your shell is csh
@ -279,7 +279,7 @@ that may support multiple versions of every tool. Tell configure the
eventual destination directory name. We recommend that the destination
location include the Verilator version name:
.. code-block:: shell
.. code-block:: bash
unset VERILATOR_ROOT # if your shell is bash
unsetenv VERILATOR_ROOT # if your shell is csh
@ -291,7 +291,7 @@ the ``bin`` directory to your ``PATH``. Or, if you use `modulecmd
<https://modules.sourceforge.net/>`__, you'll want a module file like the
following:
.. code-block:: shell
.. code-block:: bash
set install_root /CAD_DISK/verilator/{version-number-used-above}
unsetenv VERILATOR_ROOT
@ -306,7 +306,7 @@ following:
The final option is to eventually install Verilator globally, using
configure's default system paths:
.. code-block:: shell
.. code-block:: bash
unset VERILATOR_ROOT # if your shell is bash
unsetenv VERILATOR_ROOT # if your shell is csh
@ -323,7 +323,7 @@ The command to configure the package was described in the previous step.
Developers should configure to have more complete developer tests.
Additional packages may be required for these tests.
.. code-block:: shell
.. code-block:: bash
export VERILATOR_AUTHOR_SITE=1 # Put in your .bashrc
./configure --enable-longtests ...above options...
@ -334,7 +334,7 @@ Compile
Compile Verilator:
.. code-block:: shell
.. code-block:: bash
make -j `nproc` # Or if error on `nproc`, the number of CPUs in system
@ -344,7 +344,7 @@ Test
Check the compilation by running self-tests:
.. code-block:: shell
.. code-block:: bash
make test
@ -356,7 +356,7 @@ If you used any install option other than the `1. Run-in-Place from
VERILATOR_ROOT <#_1_run_in_place_from_verilator_root>`__ scheme, install
the files:
.. code-block:: shell
.. code-block:: bash
make install

130
docs/guide/warnings.rst
View File

@ -103,8 +103,8 @@ List Of Warnings
.. code-block:: sv
always_comb begin
a = b;
b = 1;
a = b;
b = 1;
end
Ignoring this warning will only suppress the lint check; it will
@ -275,11 +275,11 @@ List Of Warnings
.. code-block:: sv
always @(posedge clk)
if (~reset_l)
for (i=0; i<`ARRAY_SIZE; i++)
array[i] <= 0; // Non-blocking assignment inside loop
else
array[address] <= data;
if (~reset_l)
for (i=0; i<`ARRAY_SIZE; i++)
array[i] <= 0; // Non-blocking assignment inside loop
else
array[address] <= data;
While this is supported in typical synthesizeable code (including the
example above), some complicated cases are not supported. Namely:
@ -577,7 +577,7 @@ List Of Warnings
:emphasize-lines: 5
module parameterized
#(parameter int MY_PARAM = 0);
#(parameter int MY_PARAM = 0);
endmodule
module upper;
defparam p0.MY_PARAM = 1; //<--- Warning
@ -598,12 +598,12 @@ List Of Warnings
:emphasize-lines: 6
module parameterized
#(parameter int MY_PARAM = 0);
#(parameter int MY_PARAM = 0);
endmodule
module upper
parameterized
#(.MY_PARAM(1)) //<--- Repaired
p0();
#(.MY_PARAM(1)) //<--- Repaired
p0();
endmodule
Other tools with similar warnings: Verible's forbid_defparam_rule.
@ -745,7 +745,7 @@ List Of Warnings
:emphasize-lines: 2
typedef enum [3:0] {
WRONG_WIDTH = 33'h3 //<--- Warning
WRONG_WIDTH = 33'h3 //<--- Warning
} enum_t;
To repair, correct the size of the item's value directly, or use a cast,
@ -831,8 +831,8 @@ List Of Warnings
:emphasize-lines: 2
generate
if (PARAM == 1) begin //<--- Warning
end
if (PARAM == 1) begin //<--- Warning
end
Results in:
@ -848,8 +848,8 @@ List Of Warnings
:emphasize-lines: 2
generate
if (PARAM == 1) begin : gen_param_1 //<--- Repaired
end
if (PARAM == 1) begin : gen_param_1 //<--- Repaired
end
Other tools with similar warnings: Verible's generate-label, "All
generate block statements must have a label."
@ -885,7 +885,7 @@ List Of Warnings
:emphasize-lines: 5
function int function_being_called_as_task;
return 1;
return 1;
endfunction
initial function_being_called_as_task(); //<--- Warning
@ -904,7 +904,7 @@ List Of Warnings
:emphasize-lines: 5
function int function_being_called_as_task;
return 1;
return 1;
endfunction
initial void'(function_being_called_as_task()); //<--- Repaired
@ -1074,10 +1074,10 @@ List Of Warnings
:emphasize-lines: 3
task foo(int local_var);
fork
#10 local_var++;
#20 $display("local_var = %d", local_var);
join_none
fork
#10 local_var++;
#20 $display("local_var = %d", local_var);
join_none
endtask
In the example above 'local_var' exists only within scope of 'foo', once foo
@ -1099,19 +1099,19 @@ List Of Warnings
:emphasize-lines: 4
task foo(int local_var);
fork
#10 begin
int forked_var = local_var;
forked_var++;
end
#20 begin
// Note that we are going to print the original value here,
// as `forked_var`is a local copy that was initialized while
// `foo` was still alive.
int forked_var = local_var;
$display("forked_var = %d", forked_var)
end
join_none
fork
#10 begin
int forked_var = local_var;
forked_var++;
end
#20 begin
// Note that we are going to print the original value here,
// as `forked_var`is a local copy that was initialized while
// `foo` was still alive.
int forked_var = local_var;
$display("forked_var = %d", forked_var)
end
join_none
endtask
If you need to share its state, another strategy is to ensure it's allocated
@ -1124,10 +1124,10 @@ List Of Warnings
int static_var;
task foo();
fork
#10 static_var++;
#20 $display("static_var = %d", static_var);
join_none
fork
#10 static_var++;
#20 $display("static_var = %d", static_var);
join_none
endtask
However, if you need to be able to instantiate at runtime, the solution would be to
@ -1139,23 +1139,23 @@ List Of Warnings
:emphasize-lines: 2
class Wrapper;
int m_var;
int m_var;
// Here we implicitly hold a reference to `this`
task foo();
fork
#10 m_var++;
#20 $display("this.m_var = %d", m_var);
join_none
endtask
// Here we implicitly hold a reference to `this`
task foo();
fork
#10 m_var++;
#20 $display("this.m_var = %d", m_var);
join_none
endtask
endclass
// Here we explicitly hold a handle to an object
task bar(Wrapper wrapper);
fork
#10 wrapper.m_var++;
#20 $display("wrapper.m_var = %d", wrapper.m_var);
join_none
fork
#10 wrapper.m_var++;
#20 $display("wrapper.m_var = %d", wrapper.m_var);
join_none
endtask
.. option:: LITENDIAN
@ -1197,8 +1197,8 @@ List Of Warnings
:emphasize-lines: 3
if (something)
statement_in_if;
statement_not_in_if; //<--- Warning
statement_in_if;
statement_not_in_if; //<--- Warning
Results in:
@ -1214,7 +1214,7 @@ List Of Warnings
:emphasize-lines: 3
if (something)
statement_in_if;
statement_in_if;
statement_not_in_if; //<--- Repaired
Other tools with similar warnings: GCC -Wmisleading-indentation,
@ -1489,11 +1489,11 @@ List Of Warnings
module a;
localparam A=1;
generate
if (A==0) begin
b b_inst1 (.x(1'b0)); //<--- error nonexistent port
b #(.PX(1'b0)) b_inst2 (); //<--- error nonexistent parameter
end
endgenerate
if (A==0) begin
b b_inst1 (.x(1'b0)); //<--- error nonexistent port
b #(.PX(1'b0)) b_inst2 (); //<--- error nonexistent parameter
end
endgenerate
endmodule
module b;
@ -1766,9 +1766,9 @@ List Of Warnings
wire vec[6:0];
initial begin
index = 7;
...
if (index < 7) out = vec[index]; // Never will use vec[7]
index = 7;
...
if (index < 7) out = vec[index]; // Never will use vec[7]
Other tools with similar warnings: Icarus Verilog's select-range,
"warning: ... [...] is selecting before vector" or "is selecting before
@ -1952,7 +1952,7 @@ List Of Warnings
task foo(inout sig); ... endtask
// ...
always @* begin
foo(bus_we_select_from[2]); // Will get TASKNSVAR error
foo(bus_we_select_from[2]); // Will get TASKNSVAR error
end
Change this to:
@ -1963,8 +1963,8 @@ List Of Warnings
// ...
reg foo_temp_out;
always @* begin
foo(foo_temp_out);
bus_we_select_from[2] = foo_temp_out;
foo(foo_temp_out);
bus_we_select_from[2] = foo_temp_out;
end
Verilator doesn't do this conversion for you, as some more complicated

60
test_regress/t/t_assert_comp_bad.out
View File

@ -1,47 +1,47 @@
-Info: t/t_assert_comp_bad.v:13:7: Elaboration system task message (IEEE 1800-2023 20.11)
-Info: t/t_assert_comp_bad.v:13:5: Elaboration system task message (IEEE 1800-2023 20.11)
: ... note: In instance 't'
13 | $info;
| ^~~~~
-Info: t/t_assert_comp_bad.v:14:7: User elaboration-time info
13 | $info;
| ^~~~~
-Info: t/t_assert_comp_bad.v:14:5: User elaboration-time info
: ... note: In instance 't'
14 | $info("User elaboration-time info");
| ^~~~~
-Info: t/t_assert_comp_bad.v:15:7: Percent=% PctPct=%% Ten=10
14 | $info("User elaboration-time info");
| ^~~~~
-Info: t/t_assert_comp_bad.v:15:5: Percent=% PctPct=%% Ten=10
: ... note: In instance 't'
15 | $info("Percent=%% PctPct=%s Ten=%0d", PCTPCT, TEN);
| ^~~~~
%Warning-USERWARN: t/t_assert_comp_bad.v:16:7: Elaboration system task message (IEEE 1800-2023 20.11)
15 | $info("Percent=%% PctPct=%s Ten=%0d", PCTPCT, TEN);
| ^~~~~
%Warning-USERWARN: t/t_assert_comp_bad.v:16:5: Elaboration system task message (IEEE 1800-2023 20.11)
: ... note: In instance 't'
16 | $warning;
| ^~~~~~~~
16 | $warning;
| ^~~~~~~~
... For warning description see https://verilator.org/warn/USERWARN?v=latest
... Use "/* verilator lint_off USERWARN */" and lint_on around source to disable this message.
%Warning-USERWARN: t/t_assert_comp_bad.v:17:7: User elaboration-time warning
%Warning-USERWARN: t/t_assert_comp_bad.v:17:5: User elaboration-time warning
: ... note: In instance 't'
17 | $warning("User elaboration-time warning");
| ^~~~~~~~
%Warning-USERWARN: t/t_assert_comp_bad.v:18:7: 1
17 | $warning("User elaboration-time warning");
| ^~~~~~~~
%Warning-USERWARN: t/t_assert_comp_bad.v:18:5: 1
: ... note: In instance 't'
18 | $warning(1);
| ^~~~~~~~
%Warning-USERERROR: t/t_assert_comp_bad.v:19:7: Elaboration system task message (IEEE 1800-2023 20.11)
18 | $warning(1);
| ^~~~~~~~
%Warning-USERERROR: t/t_assert_comp_bad.v:19:5: Elaboration system task message (IEEE 1800-2023 20.11)
: ... note: In instance 't'
19 | $error;
| ^~~~~~
19 | $error;
| ^~~~~~
... For warning description see https://verilator.org/warn/USERERROR?v=latest
... Use "/* verilator lint_off USERERROR */" and lint_on around source to disable this message.
%Warning-USERERROR: t/t_assert_comp_bad.v:20:7: User elaboration-time error
%Warning-USERERROR: t/t_assert_comp_bad.v:20:5: User elaboration-time error
: ... note: In instance 't'
20 | $error("User elaboration-time error");
| ^~~~~~
%Warning-USERFATAL: t/t_assert_comp_bad.v:21:7: User elaboration-time fatal
20 | $error("User elaboration-time error");
| ^~~~~~
%Warning-USERFATAL: t/t_assert_comp_bad.v:21:5: User elaboration-time fatal
: ... note: In instance 't'
21 | $fatal(0, "User elaboration-time fatal");
| ^~~~~~
21 | $fatal(0, "User elaboration-time fatal");
| ^~~~~~
... For warning description see https://verilator.org/warn/USERFATAL?v=latest
... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message.
%Warning-USERFATAL: t/t_assert_comp_bad.v:22:7: Elaboration system task message (IEEE 1800-2023 20.11)
%Warning-USERFATAL: t/t_assert_comp_bad.v:22:5: Elaboration system task message (IEEE 1800-2023 20.11)
: ... note: In instance 't'
22 | $fatal;
| ^~~~~~
22 | $fatal;
| ^~~~~~
%Error: Exiting due to

30
test_regress/t/t_assert_comp_bad.v
View File

@ -4,22 +4,22 @@
// any use, without warranty, 2007 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
module t;
localparam TEN = 10;
localparam string PCTPCT = "%%";
localparam TEN = 10;
localparam string PCTPCT = "%%";
if (1) begin
$info;
$info("User elaboration-time info");
$info("Percent=%% PctPct=%s Ten=%0d", PCTPCT, TEN);
$warning;
$warning("User elaboration-time warning");
$warning(1); // Check can convert arguments to format
$error;
$error("User elaboration-time error");
$fatal(0, "User elaboration-time fatal");
$fatal;
end
if (1) begin
$info;
$info("User elaboration-time info");
$info("Percent=%% PctPct=%s Ten=%0d", PCTPCT, TEN);
$warning;
$warning("User elaboration-time warning");
$warning(1); // Check can convert arguments to format
$error;
$error("User elaboration-time error");
$fatal(0, "User elaboration-time fatal");
$fatal;
end
endmodule

6
test_regress/t/t_lint_badvltpragma_bad.out
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@ -1,5 +1,5 @@
%Error-BADVLTPRAGMA: t/t_lint_badvltpragma_bad.v:7:4: Unknown verilator comment: '/*verilator lintt_off WIDTH <--- Warning (lint_off misspelled)*/'
7 | /*verilator lintt_off WIDTH <--- Warning (lint_off misspelled)*/
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
%Error-BADVLTPRAGMA: t/t_lint_badvltpragma_bad.v:7:3: Unknown verilator comment: '/*verilator lintt_off WIDTH <--- Warning (lint_off misspelled)*/'
7 | /*verilator lintt_off WIDTH <--- Warning (lint_off misspelled)*/
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
... For error description see https://verilator.org/warn/BADVLTPRAGMA?v=latest
%Error: Exiting due to

4
test_regress/t/t_lint_badvltpragma_bad.v
View File

@ -4,6 +4,6 @@
// SPDX-License-Identifier: CC0-1.0
module t;
// verilator lintt_off WIDTH //<--- Warning (lint_off misspelled)
bit one = 2;
// verilator lintt_off WIDTH //<--- Warning (lint_off misspelled)
bit one = 2;
endmodule

16
test_regress/t/t_lint_didnotconverge_bad.v
View File

@ -4,16 +4,16 @@
// any use, without warranty, 2012 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Outputs
a, b
);
module t ( /*AUTOARG*/
// Outputs
a, b
);
// verilator lint_off UNOPTFLAT
// verilator lint_off UNOPTFLAT
output logic a, b;
output logic a, b;
always_comb b = ~a;
always_comb a = b;
always_comb b = ~a;
always_comb a = b;
endmodule

28
test_regress/t/t_lint_multidriven_bad.out
View File

@ -1,17 +1,17 @@
%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:21:22: Signal has multiple driving blocks with different clocking: 't.mem'
t/t_lint_multidriven_bad.v:24:7: ... Location of first driving block
24 | mem[a0] <= d0;
| ^~~
t/t_lint_multidriven_bad.v:27:7: ... Location of other driving block
27 | mem[a0] <= d1;
| ^~~
%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:21:13: Signal has multiple driving blocks with different clocking: 't.mem'
t/t_lint_multidriven_bad.v:24:5: ... Location of first driving block
24 | mem[a0] <= d0;
| ^~~
t/t_lint_multidriven_bad.v:27:5: ... Location of other driving block
27 | mem[a0] <= d1;
| ^~~
... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest
... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message.
%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:19:22: Signal has multiple driving blocks with different clocking: 'out2'
t/t_lint_multidriven_bad.v:32:7: ... Location of first driving block
32 | out2[7:0] <= d0;
| ^~~~
t/t_lint_multidriven_bad.v:35:7: ... Location of other driving block
35 | out2[15:8] <= d0;
| ^~~~
%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:19:21: Signal has multiple driving blocks with different clocking: 'out2'
t/t_lint_multidriven_bad.v:32:5: ... Location of first driving block
32 | out2[7:0] <= d0;
| ^~~~
t/t_lint_multidriven_bad.v:35:5: ... Location of other driving block
35 | out2[15:8] <= d0;
| ^~~~
%Error: Exiting due to

52
test_regress/t/t_lint_multidriven_bad.v
View File

@ -4,35 +4,35 @@
// any use, without warranty, 2012 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Outputs
out, out2,
// Inputs
clk, a0, d0, d1
);
module t ( /*AUTOARG*/
// Outputs
out, out2,
// Inputs
clk, a0, d0, d1
);
input clk;
input [1:0] a0;
input [7:0] d0;
input [7:0] d1;
output reg [31:0] out;
output reg [15:0] out2;
input clk;
input [1:0] a0;
input [7:0] d0;
input [7:0] d1;
output reg [31:0] out;
output reg [15:0] out2;
reg [7:0] mem [4];
reg [7:0] mem[4];
always @(posedge clk) begin
mem[a0] <= d0; // <--- Warning
end
always @(negedge clk) begin
mem[a0] <= d1; // <--- Warning
end
assign out = {mem[3],mem[2],mem[1],mem[0]};
always @(posedge clk) begin
mem[a0] <= d0; // <--- Warning
end
always @(negedge clk) begin
mem[a0] <= d1; // <--- Warning
end
assign out = {mem[3], mem[2], mem[1], mem[0]};
always @(posedge clk) begin
out2[7:0] <= d0; // <--- Warning
end
always @(negedge clk) begin
out2[15:8] <= d0; // <--- Warning
end
always @(posedge clk) begin
out2[7:0] <= d0; // <--- Warning
end
always @(negedge clk) begin
out2[15:8] <= d0; // <--- Warning
end
endmodule

26
test_regress/t/t_lint_procassinit_bad.out
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@ -1,21 +1,21 @@
%Warning-PROCASSINIT: t/t_lint_procassinit_bad.v:26:21: Procedural assignment to declaration with initial value: 'flop_out'
%Warning-PROCASSINIT: t/t_lint_procassinit_bad.v:26:20: Procedural assignment to declaration with initial value: 'flop_out'
: ... note: In instance 't'
: ... Location of variable initialization
26 | logic flop_out = 1;
| ^
t/t_lint_procassinit_bad.v:30:10: ... Location of variable process write
: ... Perhaps should initialize instead using a reset in this process
30 | flop_out <= ~in;
| ^~~~~~~~
26 | logic flop_out = 1;
| ^
t/t_lint_procassinit_bad.v:30:7: ... Location of variable process write
: ... Perhaps should initialize instead using a reset in this process
30 | flop_out <= ~in;
| ^~~~~~~~
... For warning description see https://verilator.org/warn/PROCASSINIT?v=latest
... Use "/* verilator lint_off PROCASSINIT */" and lint_on around source to disable this message.
%Warning-PROCASSINIT: t/t_lint_procassinit_bad.v:48:21: Procedural assignment to declaration with initial value: 'bad_comb'
%Warning-PROCASSINIT: t/t_lint_procassinit_bad.v:48:20: Procedural assignment to declaration with initial value: 'bad_comb'
: ... note: In instance 't'
: ... Location of variable initialization
48 | logic bad_comb = 1;
| ^
t/t_lint_procassinit_bad.v:51:7: ... Location of variable process write
48 | logic bad_comb = 1;
| ^
t/t_lint_procassinit_bad.v:51:5: ... Location of variable process write
: ... Perhaps should initialize instead using a reset in this process
51 | bad_comb = ok2;
| ^~~~~~~~
51 | bad_comb = ok2;
| ^~~~~~~~
%Error: Exiting due to

74
test_regress/t/t_lint_procassinit_bad.v
View File

@ -4,53 +4,53 @@
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk, reset_l, in, enable
);
input clk;
input reset_l;
input in;
input enable;
module t ( /*AUTOARG*/
// Inputs
clk, reset_l, in, enable
);
input clk;
input reset_l;
input in;
input enable;
logic ok1 = 1;
logic ok2 = 1;
logic ok3 = ok2;
logic ok1 = 1;
logic ok2 = 1;
logic ok3 = ok2;
initial begin
ok1 = 1;
end
initial begin
ok1 = 1;
end
//== Faulty example
//== Faulty example
logic flop_out = 1; // <--- Warning
logic flop_out = 1; // <--- Warning
always @(posedge clk, negedge reset_l) begin
if (enable) begin
flop_out <= ~in; // <--- Use of initialized
end
end
always @(posedge clk, negedge reset_l) begin
if (enable) begin
flop_out <= ~in; // <--- Use of initialized
end
end
//== Fixed example
//== Fixed example
logic flop2_out;
logic flop2_out;
always @(posedge clk, negedge reset_l) begin
if (!reset_l) begin
flop2_out <= '1; // <--- Added reset init
end
else if (enable) begin
flop2_out <= ~in;
end
end
always @(posedge clk, negedge reset_l) begin
if (!reset_l) begin
flop2_out <= '1; // <--- Added reset init
end
else if (enable) begin
flop2_out <= ~in;
end
end
// Combo version
logic bad_comb = 1; // but this is not fine
// Combo version
logic bad_comb = 1; // but this is not fine
always @* begin
bad_comb = ok2;
end
always @* begin
bad_comb = ok2;
end
wire _unused_ok = &{1'b0, flop_out, flop2_out, bad_comb, ok1, ok2, ok3};
wire _unused_ok = &{1'b0, flop_out, flop2_out, bad_comb, ok1, ok2, ok3};
endmodule

6
test_regress/t/t_lint_stmtdly_bad.out
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@ -1,7 +1,7 @@
%Warning-STMTDLY: t/t_lint_stmtdly_bad.v:10:7: Ignoring delay on this statement due to --no-timing
%Warning-STMTDLY: t/t_lint_stmtdly_bad.v:10:5: Ignoring delay on this statement due to --no-timing
: ... note: In instance 't'
10 | #100 $finish;
| ^
10 | #100 $finish;
| ^
... For warning description see https://verilator.org/warn/STMTDLY?v=latest
... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.
%Error: Exiting due to

8
test_regress/t/t_lint_stmtdly_bad.v
View File

@ -4,10 +4,10 @@
// any use, without warranty, 2012 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
module t ( /*AUTOARG*/);
initial begin
#100 $finish; //<--- Warning
end
initial begin
#100 $finish; //<--- Warning
end
endmodule

6
test_regress/t/t_var_bad_hide_docs.out
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@ -1,6 +1,6 @@
%Warning-VARHIDDEN: t/t_var_bad_hide_docs.v:8:12: Declaration of signal hides declaration in upper scope: 't'
8 | integer t;
| ^
%Warning-VARHIDDEN: t/t_var_bad_hide_docs.v:8:11: Declaration of signal hides declaration in upper scope: 't'
8 | integer t;
| ^
t/t_var_bad_hide_docs.v:7:8: ... Location of original declaration
7 | module t;
| ^

2
test_regress/t/t_var_bad_hide_docs.v
View File

@ -5,5 +5,5 @@
// SPDX-License-Identifier: CC0-1.0
module t;
integer t; //<--- Warning ('t' hidden by module 't')
integer t; //<--- Warning ('t' hidden by module 't')
endmodule