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luke/verilator
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mirror of https://github.com/verilator/verilator.git synced 2026-10-06 01:54:01 +02:00
Code Issues Packages Projects Releases Wiki Activity
10,283 Commits 3 Branches 171 Tags
47ead4e89dd5b65bca812b23a544af9dfd40c016
Commit Graph
9 Commits
Author SHA1 Message Date
Wilson Snyder c8a75e9b4d Tests: Reformat some tests to mostly verilog-format standard. No test functional change. 2026-09-12 08:38:51 -04:00
Wilson Snyder 599f8b8e35 Tests: Reformat some tests to mostly verilog-format standard. No test functional change. 2026-09-08 21:26:11 -04:00
Veripool API Bot 07ed6aef53 Tests: Verilog format 2026-03-08 18:26:40 -04:00
Wilson Snyder 7c6c6a684b Add SPDX copyright identifiers, and get 'reuse' clean. No functional change. 2026-01-26 20:24:34 -05:00
Wilson Snyder 6e8bd3da19 Internals/Tests: Cleanup some missing dev coverage items 2025-10-11 12:54:55 -04:00
Wilson Snyder 915ceb2d04 Tests: Untabify tests. No functional change. 2022-05-01 10:10:00 -04:00
Wilson Snyder 3a5cbd5b67 Internals: Untabify some embedded tabs. 2021-11-13 10:46:25 -05:00
Wilson Snyder 1ce360ed5b Add SPDX license identifiers. No functional change. 2020-03-21 11:24:24 -04:00
Wilson Snyder 1f2abb9c0f Fix gate primitives with arrays and non-arrayed pins. 2014-05-15 20:57:09 -04:00
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