Internals/Tests: Cleanup some missing dev coverage items
This commit is contained in:
Wilson Snyder
parent
078275034d
commit
6e8bd3da19
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@ -655,6 +655,7 @@ GENHTML := genhtml
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GENHTML_OPT := -j $(shell nproc)
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GENHTML_OPT += --branch-coverage
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GENHTML_OPT += --demangle-cpp
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GENHTML_OPT += --missed
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GENHTML_OPT += --rc branch_coverage=1
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GENHTML_OPT += --rc genhtml_hi_limit=100
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GENHTML_OPT += --ignore-errors negative
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@ -111,7 +111,7 @@ public:
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return it->second->m_datap;
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} else {
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VL_FATAL_MT(__FILE__, __LINE__, "randomize", "indexed_name not found in m_arr_vars");
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return nullptr;
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return nullptr; // LCOV_EXCL_BR_LINE
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}
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}
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void emitHexs(std::ostream& s, const std::vector<IData>& indices, const size_t bit_width,
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@ -531,7 +531,7 @@ public:
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}
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VL_ATTR_ALWINLINE void chgEventTriggered(uint32_t* oldp) { fullEventTriggered(oldp); }
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VL_ATTR_ALWINLINE void chgDouble(uint32_t* oldp, double newval) {
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double old;
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double old; // LCOV_EXCL_LINE // lcov bug
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std::memcpy(&old, oldp, sizeof(old));
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if (VL_UNLIKELY(old != newval)) fullDouble(oldp, newval);
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}
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@ -2399,7 +2399,7 @@ bool vl_check_format(const VerilatedVar* varp, const p_vpi_value valuep, const c
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case VLVT_UINT32:
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case VLVT_UINT64:
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case VLVT_WDATA: return status;
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default: status = false;
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default: status = false; // LCOV_EXCL_LINE
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}
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} else if (valuep->format == vpiDecStrVal) {
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switch (varp->vltype()) {
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@ -2407,7 +2407,7 @@ bool vl_check_format(const VerilatedVar* varp, const p_vpi_value valuep, const c
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case VLVT_UINT16:
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case VLVT_UINT32:
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case VLVT_UINT64: return status;
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default: status = false;
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default: status = false; // LCOV_EXCL_LINE
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}
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} else if (valuep->format == vpiStringVal) {
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switch (varp->vltype()) {
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@ -2424,7 +2424,7 @@ bool vl_check_format(const VerilatedVar* varp, const p_vpi_value valuep, const c
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status = false;
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break;
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}
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default: status = false;
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default: status = false; // LCOV_EXCL_LINE
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}
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} else if (valuep->format == vpiIntVal) {
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switch (varp->vltype()) {
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@ -2433,12 +2433,12 @@ bool vl_check_format(const VerilatedVar* varp, const p_vpi_value valuep, const c
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case VLVT_UINT32:
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case VLVT_UINT64:
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case VLVT_WDATA: return status;
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default: status = false;
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default: status = false; // LCOV_EXCL_LINE
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}
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} else if (valuep->format == vpiRealVal) {
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switch (varp->vltype()) {
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case VLVT_REAL: return status;
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default: status = false;
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default: status = false; // LCOV_EXCL_LINE
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}
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} else if (valuep->format == vpiSuppressVal) {
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return status;
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@ -2919,14 +2919,14 @@ bool vl_check_array_format(const VerilatedVar* varp, const p_vpi_arrayvalue arra
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case VLVT_UINT32:
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case VLVT_UINT64:
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case VLVT_WDATA: return true;
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default:;
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default:; // LCOV_EXCL_LINE
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}
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} else if (arrayvalue_p->format == vpiIntVal) {
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switch (varp->vltype()) {
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case VLVT_UINT8:
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case VLVT_UINT16:
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case VLVT_UINT32: return true;
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default:;
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default:; // LCOV_EXCL_LINE
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}
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} else if ((arrayvalue_p->format == vpiRawTwoStateVal)
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|| (arrayvalue_p->format == vpiRawFourStateVal)) {
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@ -2936,13 +2936,13 @@ bool vl_check_array_format(const VerilatedVar* varp, const p_vpi_arrayvalue arra
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case VLVT_UINT32:
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case VLVT_UINT64:
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case VLVT_WDATA: return true;
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default:;
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default:; // LCOV_EXCL_LINE
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}
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} else if (arrayvalue_p->format == vpiShortIntVal) {
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switch (varp->vltype()) {
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case VLVT_UINT8:
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case VLVT_UINT16: return true;
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default:;
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default:; // LCOV_EXCL_LINE
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}
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} else if (arrayvalue_p->format == vpiLongIntVal) {
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switch (varp->vltype()) {
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@ -2950,7 +2950,7 @@ bool vl_check_array_format(const VerilatedVar* varp, const p_vpi_arrayvalue arra
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case VLVT_UINT16:
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case VLVT_UINT32:
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case VLVT_UINT64: return true;
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default:;
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default:; // LCOV_EXCL_LINE
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}
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}
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@ -1045,17 +1045,17 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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/************************************************************************/
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/* Tables */
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<TABLE>[rRfFpPnN\*] { FL; yylval.strp = PARSEP->newString(yytext, yyleng); return yaTABLE_FIELD; } /* edge_symbol */
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<TABLE>[01xX\?bB\-] { FL; yylval.strp = PARSEP->newString(yytext, yyleng); return yaTABLE_FIELD; } /* level_symbol, next_state */
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<TABLE>":" { FL; return yaTABLE_LRSEP; } /* LHS and RHS separator for table line. */
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<TABLE>";" { FL; return yaTABLE_LINEEND; }
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<TABLE>[\(\)] { FL; return yytext[0]; }
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<TABLE>{ws}|(\\){0,1}{crnl} { FL_FWD; FL_BRK; }
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<TABLE>"`line"{ws}+[^\n\r]*{crnl} { FL_FWD; PARSEP->lexPpline(yytext); FL_BRK; }
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<TABLE>"//"[^\n]* { FL_FWD; FL_BRK; } /* throw away single line comments */
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<TABLE>"endtable" { FL; yy_pop_state(); return yENDTABLE; }
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<TABLE><<EOF>> { FL; yylval.fl->v3error("EOF in 'table'");
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yyleng = 0; yy_pop_state(); FL_BRK; yyterminate(); }
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<TABLE>[rRfFpPnN\*] { FL; yylval.strp = PARSEP->newString(yytext, yyleng); return yaTABLE_FIELD; } /* edge_symbol */
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<TABLE>[01xX\?bB\-] { FL; yylval.strp = PARSEP->newString(yytext, yyleng); return yaTABLE_FIELD; } /* level_symbol, next_state */
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<TABLE>":" { FL; return yaTABLE_LRSEP; } /* LHS and RHS separator for table line. */
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<TABLE>";" { FL; return yaTABLE_LINEEND; }
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<TABLE>[\(\)] { FL; return yytext[0]; }
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<TABLE>{ws}|(\\){0,1}{crnl} { FL_FWD; FL_BRK; }
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<TABLE>"`line"{ws}+[^\n\r]*{crnl} { FL_FWD; PARSEP->lexPpline(yytext); FL_BRK; }
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<TABLE>"//"[^\n]* { FL_FWD; FL_BRK; } /* throw away single line comments */
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<TABLE>"endtable" { FL; yy_pop_state(); return yENDTABLE; }
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<TABLE><<EOF>> { FL; yylval.fl->v3error("EOF in 'table'");
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yyleng = 0; yy_pop_state(); FL_BRK; yyterminate(); }
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<EDGEDESC>{
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01|10|[01][zZxX]|[zZxX][01] { FL; return yaEDGEDESC; }
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@ -0,0 +1,16 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt')
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test.lint()
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test.passes()
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@ -0,0 +1,16 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2011 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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(* attr_name1 *)
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(* attr_name1 = val1 *)
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(* attr_name1 = val1, attr_name2 *)
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(* attr_name1 = val1, attr_name2=1 *)
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initial $finish;
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endmodule
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@ -7,7 +7,6 @@
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// SPDX-License-Identifier: CC0-1.0
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#include <verilated.h>
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#include VM_PREFIX_INCLUDE
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//======================================================================
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@ -21,25 +20,6 @@ extern void dpix_task();
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//======================================================================
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unsigned int main_time = 0;
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double sc_time_stamp() { return main_time; }
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VM_PREFIX* topp = nullptr;
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int main(int argc, char* argv[]) {
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Verilated::debug(0);
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Verilated::commandArgs(argc, argv);
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topp = new VM_PREFIX;
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topp->eval();
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topp->final();
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VL_DO_DANGLING(delete topp, topp);
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return 1;
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}
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void dpix_run_tests() {
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dpix_task(); // Wrong scope
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}
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@ -1,2 +1,2 @@
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%Error: unknown:0: Testbench C called 'dpix_task' but this DPI export function exists only in other scopes, not scope 'TOP.t'
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%Error: unknown:0: Testbench C called 'dpix_task' but this DPI export function exists only in other scopes, not scope 't'
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Aborting...
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@ -11,7 +11,7 @@ import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(v_flags2=["--exe", test.pli_filename], make_main=False)
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test.compile(v_flags2=["--binary", test.pli_filename])
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test.execute(fails=True, expect_filename=test.golden_filename)
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@ -4,86 +4,84 @@
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// any use, without warranty, 2014 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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module t (
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input clk
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);
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integer cyc = 0;
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reg [63:0] crc;
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reg [63:0] sum;
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integer cyc = 0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Take CRC data and apply to testblock inputs
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wire [7:0] a = crc[7:0];
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wire [7:0] b = crc[15:8];
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// Take CRC data and apply to testblock inputs
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wire [7:0] a = crc[7:0];
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wire [7:0] b = crc[15:8];
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [63:0] out; // From test of Test.v
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// End of automatics
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [63:0] out; // From test of Test.v
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wire [63:0] out2; // From test of Test.v
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// End of automatics
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Test test (/*AUTOINST*/
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// Outputs
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.out (out[63:0]),
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// Inputs
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.clk (clk),
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.a (a[7:0]),
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.b (b[7:0]));
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Test test ( /*AUTOINST*/
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// Outputs
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.out (out[63:0]),
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.out2 (out2[63:0]),
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// Inputs
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.clk (clk),
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.a (a[7:0]),
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.b (b[7:0]));
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// Aggregate outputs into a single result vector
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wire [63:0] result = {out};
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// Aggregate outputs into a single result vector
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wire [63:0] result = {out};
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// Test loop
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always @ (posedge clk) begin
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// Test loop
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
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$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= 64'h0;
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end
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else if (cyc<10) begin
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sum <= 64'h0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'h0908a1f2194d24ee
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
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if (cyc == 0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= 64'h0;
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end
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else if (cyc < 10) begin
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sum <= 64'h0;
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end
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else if (cyc < 90) begin
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if (out2 !== out) $stop;
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end
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else if (cyc == 99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'h0908a1f2194d24ee
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test (/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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clk, a, b
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);
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module Test (
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input clk,
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input [7:0] a,
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input [7:0] b,
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output reg [63:0] out,
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output reg [63:0] out2
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);
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input clk;
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input [7:0] a;
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input [7:0] b;
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output reg [63:0] out;
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and u0[7:0] (out[7:0], a[7:0], b[7:0]);
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and u1[7:0] (out[15:8], a[0], b[7:0]);
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and u2[7:0] (out[23:16], a[0], b[0]);
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nand u3[7:0] (out[31:24], a[0], b[7:0]);
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or u4[7:0] (out[39:32], a[0], b[7:0]);
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nor u5[7:0] (out[47:40], a[0], b[7:0]);
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xor u6[7:0] (out[55:48], a[0], b[7:0]);
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xnor u7[7:0] (out[63:56], a[0], b[7:0]);
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// Also cover comma syntax
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and u0a[7:0] (out[7:0], a[7:0], b[7:0]), u0b[7:0] (out2[7:0], a[7:0], b[7:0]);
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and u1a[7:0] (out[15:8], a[0], b[7:0]), u1b[7:0] (out2[15:8], a[0], b[7:0]);
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and u2a[7:0] (out[23:16], a[0], b[0]), u2b[7:0] (out2[23:16], a[0], b[0]);
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nand u3a[7:0] (out[31:24], a[0], b[7:0]), u3b[7:0] (out2[31:24], a[0], b[7:0]);
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or u4a[7:0] (out[39:32], a[0], b[7:0]), u4b[7:0] (out2[39:32], a[0], b[7:0]);
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nor u5a[7:0] (out[47:40], a[0], b[7:0]), u5b[7:0] (out2[47:40], a[0], b[7:0]);
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xor u6a[7:0] (out[55:48], a[0], b[7:0]), u6b[7:0] (out2[55:48], a[0], b[7:0]);
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xnor u7a[7:0] (out[63:56], a[0], b[7:0]), u7b[7:0] (out2[63:56], a[0], b[7:0]);
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endmodule
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@ -1,166 +1,214 @@
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%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:15:21: Signal definition not found, creating implicitly: 'i_and1'
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15 | and g_and(o_and, i_and1, i_and2, i_and3);
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| ^~~~~~
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%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:20: Signal definition not found, creating implicitly: 'i_and1'
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18 | and g_and(o_and, i_and1, i_and2, i_and3),
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| ^~~~~~
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... For warning description see https://verilator.org/warn/IMPLICIT?v=latest
|
||||
... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:15:29: Signal definition not found, creating implicitly: 'i_and2'
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:28: Signal definition not found, creating implicitly: 'i_and2'
|
||||
: ... Suggested alternative: 'i_and1'
|
||||
15 | and g_and(o_and, i_and1, i_and2, i_and3);
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:15:37: Signal definition not found, creating implicitly: 'i_and3'
|
||||
18 | and g_and(o_and, i_and1, i_and2, i_and3),
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:36: Signal definition not found, creating implicitly: 'i_and3'
|
||||
: ... Suggested alternative: 'i_and1'
|
||||
15 | and g_and(o_and, i_and1, i_and2, i_and3);
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:15:14: Signal definition not found, creating implicitly: 'o_and'
|
||||
18 | and g_and(o_and, i_and1, i_and2, i_and3),
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:13: Signal definition not found, creating implicitly: 'o_and'
|
||||
: ... Suggested alternative: 'i_and1'
|
||||
15 | and g_and(o_and, i_and1, i_and2, i_and3);
|
||||
| ^~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:16:30: Signal definition not found, creating implicitly: 'i_not1'
|
||||
16 | not g_not(o_not1, o_not2, i_not1);
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:16:14: Signal definition not found, creating implicitly: 'o_not1'
|
||||
: ... Suggested alternative: 'i_not1'
|
||||
16 | not g_not(o_not1, o_not2, i_not1);
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:16:22: Signal definition not found, creating implicitly: 'o_not2'
|
||||
: ... Suggested alternative: 'o_not1'
|
||||
16 | not g_not(o_not1, o_not2, i_not1);
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:17:21: Signal definition not found, creating implicitly: 'i_nor1'
|
||||
: ... Suggested alternative: 'i_not1'
|
||||
17 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3);
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:17:29: Signal definition not found, creating implicitly: 'i_nor2'
|
||||
: ... Suggested alternative: 'i_nor1'
|
||||
17 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3);
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:17:37: Signal definition not found, creating implicitly: 'i_nor3'
|
||||
: ... Suggested alternative: 'i_nor1'
|
||||
17 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3);
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:17:14: Signal definition not found, creating implicitly: 'o_nor'
|
||||
: ... Suggested alternative: 'i_nor1'
|
||||
17 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3);
|
||||
| ^~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:18: Signal definition not found, creating implicitly: 'i_or1'
|
||||
: ... Suggested alternative: 'i_nor1'
|
||||
18 | or g_or(o_or, i_or1, i_or2, i_or3);
|
||||
| ^~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:25: Signal definition not found, creating implicitly: 'i_or2'
|
||||
: ... Suggested alternative: 'i_nor2'
|
||||
18 | or g_or(o_or, i_or1, i_or2, i_or3);
|
||||
| ^~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:32: Signal definition not found, creating implicitly: 'i_or3'
|
||||
: ... Suggested alternative: 'i_nor3'
|
||||
18 | or g_or(o_or, i_or1, i_or2, i_or3);
|
||||
| ^~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:12: Signal definition not found, creating implicitly: 'o_or'
|
||||
: ... Suggested alternative: 'o_nor'
|
||||
18 | or g_or(o_or, i_or1, i_or2, i_or3);
|
||||
| ^~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:19:24: Signal definition not found, creating implicitly: 'i_nand1'
|
||||
: ... Suggested alternative: 'i_and1'
|
||||
19 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3);
|
||||
| ^~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:19:33: Signal definition not found, creating implicitly: 'i_nand2'
|
||||
: ... Suggested alternative: 'i_and2'
|
||||
19 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3);
|
||||
| ^~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:19:42: Signal definition not found, creating implicitly: 'i_nand3'
|
||||
: ... Suggested alternative: 'i_and3'
|
||||
19 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3);
|
||||
| ^~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:19:16: Signal definition not found, creating implicitly: 'o_nand'
|
||||
18 | and g_and(o_and, i_and1, i_and2, i_and3),
|
||||
| ^~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:19:11: Signal definition not found, creating implicitly: 'o2_and'
|
||||
: ... Suggested alternative: 'o_and'
|
||||
19 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3);
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:21: Signal definition not found, creating implicitly: 'i_xor1'
|
||||
: ... Suggested alternative: 'i_nor1'
|
||||
20 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3);
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:29: Signal definition not found, creating implicitly: 'i_xor2'
|
||||
: ... Suggested alternative: 'i_nor2'
|
||||
20 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3);
|
||||
19 | g2_and(o2_and, i_and1, i_and2, i_and3);
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:29: Signal definition not found, creating implicitly: 'i_not1'
|
||||
20 | not g_not(o_not1, o_not2, i_not1),
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:37: Signal definition not found, creating implicitly: 'i_xor3'
|
||||
: ... Suggested alternative: 'i_nor3'
|
||||
20 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3);
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:14: Signal definition not found, creating implicitly: 'o_xor'
|
||||
: ... Suggested alternative: 'o_nor'
|
||||
20 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3);
|
||||
| ^~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:21:23: Signal definition not found, creating implicitly: 'i_xnor1'
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:13: Signal definition not found, creating implicitly: 'o_not1'
|
||||
: ... Suggested alternative: 'i_not1'
|
||||
20 | not g_not(o_not1, o_not2, i_not1),
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:21: Signal definition not found, creating implicitly: 'o_not2'
|
||||
: ... Suggested alternative: 'o_not1'
|
||||
20 | not g_not(o_not1, o_not2, i_not1),
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:21:11: Signal definition not found, creating implicitly: 'o2_not1'
|
||||
: ... Suggested alternative: 'o_not1'
|
||||
21 | g2_not(o2_not1, o_not2, i_not1);
|
||||
| ^~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:20: Signal definition not found, creating implicitly: 'i_nor1'
|
||||
: ... Suggested alternative: 'i_not1'
|
||||
22 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3),
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:28: Signal definition not found, creating implicitly: 'i_nor2'
|
||||
: ... Suggested alternative: 'i_nor1'
|
||||
21 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3);
|
||||
| ^~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:21:32: Signal definition not found, creating implicitly: 'i_xnor2'
|
||||
: ... Suggested alternative: 'i_nor2'
|
||||
21 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3);
|
||||
| ^~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:21:41: Signal definition not found, creating implicitly: 'i_xnor3'
|
||||
: ... Suggested alternative: 'i_nor3'
|
||||
21 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3);
|
||||
| ^~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:21:15: Signal definition not found, creating implicitly: 'o_xnor'
|
||||
22 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3),
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:36: Signal definition not found, creating implicitly: 'i_nor3'
|
||||
: ... Suggested alternative: 'i_nor1'
|
||||
22 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3),
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:13: Signal definition not found, creating implicitly: 'o_nor'
|
||||
: ... Suggested alternative: 'i_nor1'
|
||||
22 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3),
|
||||
| ^~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:23:11: Signal definition not found, creating implicitly: 'o2_nor'
|
||||
: ... Suggested alternative: 'o_nor'
|
||||
21 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3);
|
||||
23 | g2_nor(o2_nor, i_nor1, i_nor2, i_nor3);
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:17: Signal definition not found, creating implicitly: 'i_or1'
|
||||
: ... Suggested alternative: 'i_nor1'
|
||||
24 | or g_or(o_or, i_or1, i_or2, i_or3),
|
||||
| ^~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:24: Signal definition not found, creating implicitly: 'i_or2'
|
||||
: ... Suggested alternative: 'i_nor2'
|
||||
24 | or g_or(o_or, i_or1, i_or2, i_or3),
|
||||
| ^~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:31: Signal definition not found, creating implicitly: 'i_or3'
|
||||
: ... Suggested alternative: 'i_nor3'
|
||||
24 | or g_or(o_or, i_or1, i_or2, i_or3),
|
||||
| ^~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:11: Signal definition not found, creating implicitly: 'o_or'
|
||||
: ... Suggested alternative: 'o_nor'
|
||||
24 | or g_or(o_or, i_or1, i_or2, i_or3),
|
||||
| ^~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:25:10: Signal definition not found, creating implicitly: 'o2_or'
|
||||
: ... Suggested alternative: 'o2_nor'
|
||||
25 | g2_or(o2_or, i_or1, i_or2, i_or3);
|
||||
| ^~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:23: Signal definition not found, creating implicitly: 'i_nand1'
|
||||
: ... Suggested alternative: 'i_and1'
|
||||
26 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3),
|
||||
| ^~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:32: Signal definition not found, creating implicitly: 'i_nand2'
|
||||
: ... Suggested alternative: 'i_and2'
|
||||
26 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3),
|
||||
| ^~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:41: Signal definition not found, creating implicitly: 'i_nand3'
|
||||
: ... Suggested alternative: 'i_and3'
|
||||
26 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3),
|
||||
| ^~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:15: Signal definition not found, creating implicitly: 'o_nand'
|
||||
: ... Suggested alternative: 'o_and'
|
||||
26 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3),
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:30: Signal definition not found, creating implicitly: 'i_buf1'
|
||||
22 | buf g_buf(o_buf1, o_buf2, i_buf1);
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:14: Signal definition not found, creating implicitly: 'o_buf1'
|
||||
: ... Suggested alternative: 'i_buf1'
|
||||
22 | buf g_buf(o_buf1, o_buf2, i_buf1);
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:27:12: Signal definition not found, creating implicitly: 'o2_nand'
|
||||
: ... Suggested alternative: 'o2_and'
|
||||
27 | g2_nand(o2_nand, i_nand1, i_nand2, i_nand3);
|
||||
| ^~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:28:20: Signal definition not found, creating implicitly: 'i_xor1'
|
||||
: ... Suggested alternative: 'i_nor1'
|
||||
28 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3),
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:28:28: Signal definition not found, creating implicitly: 'i_xor2'
|
||||
: ... Suggested alternative: 'i_nor2'
|
||||
28 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3),
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:28:36: Signal definition not found, creating implicitly: 'i_xor3'
|
||||
: ... Suggested alternative: 'i_nor3'
|
||||
28 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3),
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:28:13: Signal definition not found, creating implicitly: 'o_xor'
|
||||
: ... Suggested alternative: 'o_nor'
|
||||
28 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3),
|
||||
| ^~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:29:11: Signal definition not found, creating implicitly: 'o2_xor'
|
||||
: ... Suggested alternative: 'o2_nor'
|
||||
29 | g2_xor(o2_xor, i_xor1, i_xor2, i_xor3);
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:30:22: Signal definition not found, creating implicitly: 'i_xnor1'
|
||||
: ... Suggested alternative: 'i_nor1'
|
||||
30 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3),
|
||||
| ^~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:30:31: Signal definition not found, creating implicitly: 'i_xnor2'
|
||||
: ... Suggested alternative: 'i_nor2'
|
||||
30 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3),
|
||||
| ^~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:30:40: Signal definition not found, creating implicitly: 'i_xnor3'
|
||||
: ... Suggested alternative: 'i_nor3'
|
||||
30 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3),
|
||||
| ^~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:30:14: Signal definition not found, creating implicitly: 'o_xnor'
|
||||
: ... Suggested alternative: 'o_nor'
|
||||
30 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3),
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:22: Signal definition not found, creating implicitly: 'o_buf2'
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:31:11: Signal definition not found, creating implicitly: 'o2_xnor'
|
||||
: ... Suggested alternative: 'o2_nor'
|
||||
31 | g2_xor(o2_xnor, i_xnor1, i_xnor2, i_xnor3);
|
||||
| ^~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:32:29: Signal definition not found, creating implicitly: 'i_buf1'
|
||||
32 | buf g_buf(o_buf1, o_buf2, i_buf1),
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:32:13: Signal definition not found, creating implicitly: 'o_buf1'
|
||||
: ... Suggested alternative: 'i_buf1'
|
||||
32 | buf g_buf(o_buf1, o_buf2, i_buf1),
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:32:21: Signal definition not found, creating implicitly: 'o_buf2'
|
||||
: ... Suggested alternative: 'o_buf1'
|
||||
22 | buf g_buf(o_buf1, o_buf2, i_buf1);
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:23:41: Signal definition not found, creating implicitly: 'i_bufif02'
|
||||
23 | bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02);
|
||||
| ^~~~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:23:30: Signal definition not found, creating implicitly: 'i_bufif01'
|
||||
32 | buf g_buf(o_buf1, o_buf2, i_buf1),
|
||||
| ^~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:33:11: Signal definition not found, creating implicitly: 'o2_buf1'
|
||||
: ... Suggested alternative: 'o_buf1'
|
||||
33 | g2_buf(o2_buf1, o_buf2, i_buf1);
|
||||
| ^~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:34:40: Signal definition not found, creating implicitly: 'i_bufif02'
|
||||
34 | bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02),
|
||||
| ^~~~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:34:29: Signal definition not found, creating implicitly: 'i_bufif01'
|
||||
: ... Suggested alternative: 'i_bufif02'
|
||||
23 | bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02);
|
||||
| ^~~~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:23:20: Signal definition not found, creating implicitly: 'o_bufif0'
|
||||
34 | bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02),
|
||||
| ^~~~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:34:19: Signal definition not found, creating implicitly: 'o_bufif0'
|
||||
: ... Suggested alternative: 'i_bufif01'
|
||||
23 | bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02);
|
||||
| ^~~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:41: Signal definition not found, creating implicitly: 'i_bufif12'
|
||||
: ... Suggested alternative: 'i_bufif02'
|
||||
24 | bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12);
|
||||
| ^~~~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:30: Signal definition not found, creating implicitly: 'i_bufif11'
|
||||
: ... Suggested alternative: 'i_bufif01'
|
||||
24 | bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12);
|
||||
| ^~~~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:20: Signal definition not found, creating implicitly: 'o_bufif1'
|
||||
34 | bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02),
|
||||
| ^~~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:35:14: Signal definition not found, creating implicitly: 'o2_bufif0'
|
||||
: ... Suggested alternative: 'o_bufif0'
|
||||
24 | bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12);
|
||||
| ^~~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:25:41: Signal definition not found, creating implicitly: 'i_notif02'
|
||||
35 | g2_bufif0(o2_bufif0, i_bufif01, i_bufif02);
|
||||
| ^~~~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:36:40: Signal definition not found, creating implicitly: 'i_bufif12'
|
||||
: ... Suggested alternative: 'i_bufif02'
|
||||
25 | notif0 g_notif0(o_notif0, i_notif01, i_notif02);
|
||||
| ^~~~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:25:30: Signal definition not found, creating implicitly: 'i_notif01'
|
||||
36 | bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12),
|
||||
| ^~~~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:36:29: Signal definition not found, creating implicitly: 'i_bufif11'
|
||||
: ... Suggested alternative: 'i_bufif01'
|
||||
36 | bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12),
|
||||
| ^~~~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:36:19: Signal definition not found, creating implicitly: 'o_bufif1'
|
||||
: ... Suggested alternative: 'o_bufif0'
|
||||
36 | bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12),
|
||||
| ^~~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:37:14: Signal definition not found, creating implicitly: 'o2_bufif1'
|
||||
: ... Suggested alternative: 'o2_bufif0'
|
||||
37 | g2_bufif1(o2_bufif1, i_bufif11, i_bufif12);
|
||||
| ^~~~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:38:40: Signal definition not found, creating implicitly: 'i_notif02'
|
||||
: ... Suggested alternative: 'i_bufif02'
|
||||
38 | notif0 g_notif0(o_notif0, i_notif01, i_notif02),
|
||||
| ^~~~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:38:29: Signal definition not found, creating implicitly: 'i_notif01'
|
||||
: ... Suggested alternative: 'i_notif02'
|
||||
25 | notif0 g_notif0(o_notif0, i_notif01, i_notif02);
|
||||
| ^~~~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:25:20: Signal definition not found, creating implicitly: 'o_notif0'
|
||||
38 | notif0 g_notif0(o_notif0, i_notif01, i_notif02),
|
||||
| ^~~~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:38:19: Signal definition not found, creating implicitly: 'o_notif0'
|
||||
: ... Suggested alternative: 'i_notif01'
|
||||
25 | notif0 g_notif0(o_notif0, i_notif01, i_notif02);
|
||||
| ^~~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:41: Signal definition not found, creating implicitly: 'i_notif12'
|
||||
: ... Suggested alternative: 'i_notif02'
|
||||
26 | notif1 g_notif1(o_notif1, i_notif11, i_notif12);
|
||||
| ^~~~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:30: Signal definition not found, creating implicitly: 'i_notif11'
|
||||
: ... Suggested alternative: 'i_notif01'
|
||||
26 | notif1 g_notif1(o_notif1, i_notif11, i_notif12);
|
||||
| ^~~~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:20: Signal definition not found, creating implicitly: 'o_notif1'
|
||||
38 | notif0 g_notif0(o_notif0, i_notif01, i_notif02),
|
||||
| ^~~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:39:14: Signal definition not found, creating implicitly: 'o2_notif0'
|
||||
: ... Suggested alternative: 'o_notif0'
|
||||
26 | notif1 g_notif1(o_notif1, i_notif11, i_notif12);
|
||||
| ^~~~~~~~
|
||||
39 | g2_notif0(o2_notif0, i_notif01, i_notif02);
|
||||
| ^~~~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:40:40: Signal definition not found, creating implicitly: 'i_notif12'
|
||||
: ... Suggested alternative: 'i_notif02'
|
||||
40 | notif1 g_notif1(o_notif1, i_notif11, i_notif12),
|
||||
| ^~~~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:40:29: Signal definition not found, creating implicitly: 'i_notif11'
|
||||
: ... Suggested alternative: 'i_notif01'
|
||||
40 | notif1 g_notif1(o_notif1, i_notif11, i_notif12),
|
||||
| ^~~~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:40:19: Signal definition not found, creating implicitly: 'o_notif1'
|
||||
: ... Suggested alternative: 'o_notif0'
|
||||
40 | notif1 g_notif1(o_notif1, i_notif11, i_notif12),
|
||||
| ^~~~~~~~
|
||||
%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:41:14: Signal definition not found, creating implicitly: 'o2_notif1'
|
||||
: ... Suggested alternative: 'o2_notif0'
|
||||
41 | g2_notif1(o2_notif1, i_notif11, i_notif12);
|
||||
| ^~~~~~~~~
|
||||
|
|
|
|||
|
|
@ -4,98 +4,125 @@
|
|||
// any use, without warranty, 2023 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t(/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
int cyc=1;
|
||||
// verilog_format: off
|
||||
`define stop $stop
|
||||
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
|
||||
// verilog_format: on
|
||||
|
||||
// Instantiate the primitive gates to be tested.
|
||||
and g_and(o_and, i_and1, i_and2, i_and3);
|
||||
not g_not(o_not1, o_not2, i_not1);
|
||||
nor g_nor(o_nor, i_nor1, i_nor2, i_nor3);
|
||||
or g_or(o_or, i_or1, i_or2, i_or3);
|
||||
nand g_nand(o_nand, i_nand1, i_nand2, i_nand3);
|
||||
xor g_xor(o_xor, i_xor1, i_xor2, i_xor3);
|
||||
xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3);
|
||||
buf g_buf(o_buf1, o_buf2, i_buf1);
|
||||
bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02);
|
||||
bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12);
|
||||
notif0 g_notif0(o_notif0, i_notif01, i_notif02);
|
||||
notif1 g_notif1(o_notif1, i_notif11, i_notif12);
|
||||
module t(
|
||||
input clk
|
||||
);
|
||||
int cyc=1;
|
||||
|
||||
// Generate random data for inputs
|
||||
reg rd_data1, rd_data2, rd_data3;
|
||||
always @(posedge clk) begin
|
||||
rd_data1 = 1'($random);
|
||||
rd_data2 = 1'($random);
|
||||
rd_data3 = 1'($random);
|
||||
end
|
||||
// Instantiate the primitive gates to be tested.
|
||||
and g_and(o_and, i_and1, i_and2, i_and3),
|
||||
g2_and(o2_and, i_and1, i_and2, i_and3);
|
||||
not g_not(o_not1, o_not2, i_not1),
|
||||
g2_not(o2_not1, o_not2, i_not1);
|
||||
nor g_nor(o_nor, i_nor1, i_nor2, i_nor3),
|
||||
g2_nor(o2_nor, i_nor1, i_nor2, i_nor3);
|
||||
or g_or(o_or, i_or1, i_or2, i_or3),
|
||||
g2_or(o2_or, i_or1, i_or2, i_or3);
|
||||
nand g_nand(o_nand, i_nand1, i_nand2, i_nand3),
|
||||
g2_nand(o2_nand, i_nand1, i_nand2, i_nand3);
|
||||
xor g_xor(o_xor, i_xor1, i_xor2, i_xor3),
|
||||
g2_xor(o2_xor, i_xor1, i_xor2, i_xor3);
|
||||
xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3),
|
||||
g2_xor(o2_xnor, i_xnor1, i_xnor2, i_xnor3);
|
||||
buf g_buf(o_buf1, o_buf2, i_buf1),
|
||||
g2_buf(o2_buf1, o_buf2, i_buf1);
|
||||
bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02),
|
||||
g2_bufif0(o2_bufif0, i_bufif01, i_bufif02);
|
||||
bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12),
|
||||
g2_bufif1(o2_bufif1, i_bufif11, i_bufif12);
|
||||
notif0 g_notif0(o_notif0, i_notif01, i_notif02),
|
||||
g2_notif0(o2_notif0, i_notif01, i_notif02);
|
||||
notif1 g_notif1(o_notif1, i_notif11, i_notif12),
|
||||
g2_notif1(o2_notif1, i_notif11, i_notif12);
|
||||
|
||||
// Assign the input of primitive gates.
|
||||
// Generate random data for inputs
|
||||
reg rd_data1, rd_data2, rd_data3;
|
||||
always @(posedge clk) begin
|
||||
rd_data1 = 1'($random);
|
||||
rd_data2 = 1'($random);
|
||||
rd_data3 = 1'($random);
|
||||
end
|
||||
|
||||
// Assign the input of primitive gates.
|
||||
`default_nettype none
|
||||
assign i_and1 = rd_data1;
|
||||
assign i_and2 = rd_data2;
|
||||
assign i_and3 = rd_data3;
|
||||
assign i_and1 = rd_data1;
|
||||
assign i_and2 = rd_data2;
|
||||
assign i_and3 = rd_data3;
|
||||
|
||||
assign i_not1 = rd_data1;
|
||||
assign i_not1 = rd_data1;
|
||||
|
||||
assign i_nor1 = rd_data1;
|
||||
assign i_nor2 = rd_data2;
|
||||
assign i_nor3 = rd_data3;
|
||||
assign i_nor1 = rd_data1;
|
||||
assign i_nor2 = rd_data2;
|
||||
assign i_nor3 = rd_data3;
|
||||
|
||||
assign i_or1 = rd_data1;
|
||||
assign i_or2 = rd_data2;
|
||||
assign i_or3 = rd_data3;
|
||||
assign i_or1 = rd_data1;
|
||||
assign i_or2 = rd_data2;
|
||||
assign i_or3 = rd_data3;
|
||||
|
||||
assign i_nand1 = rd_data1;
|
||||
assign i_nand2 = rd_data2;
|
||||
assign i_nand3 = rd_data3;
|
||||
assign i_nand1 = rd_data1;
|
||||
assign i_nand2 = rd_data2;
|
||||
assign i_nand3 = rd_data3;
|
||||
|
||||
assign i_xor1 = rd_data1;
|
||||
assign i_xor2 = rd_data2;
|
||||
assign i_xor3 = rd_data3;
|
||||
assign i_xor1 = rd_data1;
|
||||
assign i_xor2 = rd_data2;
|
||||
assign i_xor3 = rd_data3;
|
||||
|
||||
assign i_xnor1 = rd_data1;
|
||||
assign i_xnor2 = rd_data2;
|
||||
assign i_xnor3 = rd_data3;
|
||||
assign i_xnor1 = rd_data1;
|
||||
assign i_xnor2 = rd_data2;
|
||||
assign i_xnor3 = rd_data3;
|
||||
|
||||
assign i_buf1 = rd_data1;
|
||||
assign i_buf1 = rd_data1;
|
||||
|
||||
assign i_bufif01 = rd_data1;
|
||||
assign i_bufif02 = rd_data2;
|
||||
assign i_bufif01 = rd_data1;
|
||||
assign i_bufif02 = rd_data2;
|
||||
|
||||
assign i_bufif11 = rd_data1;
|
||||
assign i_bufif12 = rd_data2;
|
||||
assign i_bufif11 = rd_data1;
|
||||
assign i_bufif12 = rd_data2;
|
||||
|
||||
assign i_notif01 = rd_data1;
|
||||
assign i_notif02 = rd_data2;
|
||||
assign i_notif01 = rd_data1;
|
||||
assign i_notif02 = rd_data2;
|
||||
|
||||
assign i_notif11 = rd_data1;
|
||||
assign i_notif12 = rd_data2;
|
||||
assign i_notif11 = rd_data1;
|
||||
assign i_notif12 = rd_data2;
|
||||
|
||||
// Check the outputs of the gate instances
|
||||
always @(negedge clk) begin
|
||||
if (o_and !== (i_and1 & i_and2 & i_and3)) $stop;
|
||||
if ((o_not1 !== ~i_not1) || (o_not2 != ~i_not1)) $stop;
|
||||
if (o_nor !== !(i_nor1 | i_nor2 | i_nor3)) $stop;
|
||||
if (o_or !== (i_or1 | i_or2 | i_or3)) $stop;
|
||||
if (o_nand !== !(i_nand1 & i_nand2 & i_nand3)) $stop;
|
||||
if (o_xor !== (i_xor1 ^ i_xor2 ^ i_xor3)) $stop;
|
||||
if (o_xnor !== !(i_xnor1 ^ i_xnor2 ^ i_xnor3)) $stop;
|
||||
if ((o_buf1 !== i_buf1) || (o_buf2 !== i_buf1)) $stop;
|
||||
if (!(o_bufif0 == (i_bufif01 & !i_bufif02))) $stop;
|
||||
if (!(o_bufif1 == (i_bufif11 & i_bufif12))) $stop;
|
||||
if (!(o_notif0 == (!i_notif01 & !i_notif02))) $stop;
|
||||
if (!(o_notif1 == (!i_notif11 & i_notif12))) $stop;
|
||||
end
|
||||
// Check the outputs of the gate instances
|
||||
always @(negedge clk) begin
|
||||
if (o_and !== (i_and1 & i_and2 & i_and3)) $stop;
|
||||
if ((o_not1 !== ~i_not1) || (o_not2 != ~i_not1)) $stop;
|
||||
if (o_nor !== !(i_nor1 | i_nor2 | i_nor3)) $stop;
|
||||
if (o_or !== (i_or1 | i_or2 | i_or3)) $stop;
|
||||
if (o_nand !== !(i_nand1 & i_nand2 & i_nand3)) $stop;
|
||||
if (o_xor !== (i_xor1 ^ i_xor2 ^ i_xor3)) $stop;
|
||||
if (o_xnor !== !(i_xnor1 ^ i_xnor2 ^ i_xnor3)) $stop;
|
||||
if ((o_buf1 !== i_buf1) || (o_buf2 !== i_buf1)) $stop;
|
||||
if (!(o_bufif0 == (i_bufif01 & !i_bufif02))) $stop;
|
||||
if (!(o_bufif1 == (i_bufif11 & i_bufif12))) $stop;
|
||||
if (!(o_notif0 == (!i_notif01 & !i_notif02))) $stop;
|
||||
if (!(o_notif1 == (!i_notif11 & i_notif12))) $stop;
|
||||
`checkh(o2_and, o2_and);
|
||||
`checkh(o2_not1, o2_not1);
|
||||
`checkh(o2_nor, o2_nor);
|
||||
`checkh(o2_or, o2_or);
|
||||
`checkh(o2_nand, o2_nand);
|
||||
`checkh(o2_xor, o2_xor);
|
||||
`checkh(o2_xnor, o2_xnor);
|
||||
`checkh(o2_buf1, o2_buf1);
|
||||
`checkh(o2_bufif0, o2_bufif0);
|
||||
`checkh(o2_bufif1, o2_bufif1);
|
||||
`checkh(o2_notif0, o2_notif0);
|
||||
`checkh(o2_notif1, o2_notif1);
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
cyc = cyc + 1;
|
||||
if (cyc == 100) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
always @(posedge clk) begin
|
||||
cyc = cyc + 1;
|
||||
if (cyc == 100) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -128,6 +128,11 @@ int main(int argc, char** argv) {
|
|||
int varLeft = varp->range(0)->left();
|
||||
int varBits = varLeft + 1;
|
||||
uint8_t* varData = reinterpret_cast<uint8_t*>(varp->datap());
|
||||
// Cover illegal access
|
||||
if (varp->range(1000) != nullptr) {
|
||||
VL_PRINTF("%%Error: Range null mismatch\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
// Check that all bits are high now
|
||||
for (int i = 0; i < varBits / 8; i++) {
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@ test.main_time_multiplier = 1e-6 / 1e-9
|
|||
|
||||
test.compile(
|
||||
v_flags2=['+define+time_scale_units=1us +define+time_scale_prec=1ns', test.pli_filename],
|
||||
verilator_flags2=['--vpi'])
|
||||
verilator_flags2=['--vpi --trace-vcd'])
|
||||
|
||||
test.execute(expect_filename=test.golden_filename)
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -5,11 +5,13 @@
|
|||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Outputs
|
||||
state,
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
// Outputs
|
||||
state,
|
||||
// Inouts
|
||||
fst_inout,
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
|
|
@ -27,6 +29,7 @@ module t (/*AUTOARG*/
|
|||
shortint fst_shortint;
|
||||
longint fst_longint;
|
||||
byte fst_byte;
|
||||
time fst_time;
|
||||
|
||||
parameter fst_parameter = 123;
|
||||
localparam fst_lparam = 456;
|
||||
|
|
@ -36,6 +39,7 @@ module t (/*AUTOARG*/
|
|||
tri1 fst_tri1;
|
||||
tri fst_tri;
|
||||
wire fst_wire;
|
||||
inout fst_inout;
|
||||
|
||||
Test test (/*AUTOINST*/
|
||||
// Outputs
|
||||
|
|
@ -47,6 +51,7 @@ module t (/*AUTOARG*/
|
|||
// Test loop
|
||||
always @ (posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
fst_time <= $time;
|
||||
if (cyc==0) begin
|
||||
// Setup
|
||||
rstn <= ~'1;
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
(state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
|
||||
(state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44))
|
||||
(state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
|
||||
(fst_inout (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
(INSTANCE t
|
||||
(NET
|
||||
|
|
@ -402,6 +403,70 @@
|
|||
(fst_byte\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_byte\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_byte\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[1\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 100))
|
||||
(fst_time\[2\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 50))
|
||||
(fst_time\[3\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 75))
|
||||
(fst_time\[4\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 62))
|
||||
(fst_time\[5\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 31))
|
||||
(fst_time\[6\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 15))
|
||||
(fst_time\[7\] (T0 510) (T1 490) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(fst_time\[8\] (T0 510) (T1 490) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(fst_time\[9\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_time\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[32\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[33\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[34\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[35\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[36\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[37\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[38\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[39\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[40\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[41\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[42\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[43\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[44\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[45\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[46\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[47\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[48\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[49\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[50\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[51\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[52\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[53\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[54\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[55\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[56\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_time\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[0\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_parameter\[1\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_parameter\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
|
|
@ -472,6 +537,7 @@
|
|||
(fst_tri1 (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_tri (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_wire (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_inout (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
(INSTANCE test
|
||||
(NET
|
||||
|
|
|
|||
|
|
@ -4,45 +4,48 @@
|
|||
// without warranty, 2008 by Lane Brooks.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (clk);
|
||||
input clk;
|
||||
module t (
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
reg [31:0] state; initial state=0;
|
||||
reg [31:0] state;
|
||||
initial state = 0;
|
||||
|
||||
wire A = state[0];
|
||||
wire OE = state[1];
|
||||
wire Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9;
|
||||
wire [3:0] Z10;
|
||||
wire Z11;
|
||||
wire A = state[0];
|
||||
wire OE = state[1];
|
||||
wire Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9;
|
||||
wire [3:0] Z10;
|
||||
wire Z11;
|
||||
|
||||
Test1 test1(/*AUTOINST*/
|
||||
Test1 test1 ( /*AUTOINST*/
|
||||
// Inouts
|
||||
.Z1 (Z1),
|
||||
// Inputs
|
||||
.OE (OE),
|
||||
.A (A));
|
||||
|
||||
Test2 test2(/*AUTOINST*/
|
||||
Test2 test2 ( /*AUTOINST*/
|
||||
// Inouts
|
||||
.Z2 (Z2),
|
||||
// Inputs
|
||||
.OE (OE),
|
||||
.A (A));
|
||||
|
||||
Test3 test3(/*AUTOINST*/
|
||||
Test3 test3 ( /*AUTOINST*/
|
||||
// Inouts
|
||||
.Z3 (Z3),
|
||||
// Inputs
|
||||
.OE (OE),
|
||||
.A (A));
|
||||
|
||||
Test4 test4(/*AUTOINST*/
|
||||
Test4 test4 ( /*AUTOINST*/
|
||||
// Outputs
|
||||
.Z4 (Z4),
|
||||
// Inouts
|
||||
.Z5 (Z5));
|
||||
|
||||
Test5 test5(/*AUTOINST*/
|
||||
Test5 test5 ( /*AUTOINST*/
|
||||
// Inouts
|
||||
.Z6 (Z6),
|
||||
.Z7 (Z7),
|
||||
|
|
@ -51,116 +54,126 @@ module t (clk);
|
|||
// Inputs
|
||||
.OE (OE));
|
||||
|
||||
Test6 test6(/*AUTOINST*/
|
||||
Test6 test6 ( /*AUTOINST*/
|
||||
// Inouts
|
||||
.Z10 (Z10[3:0]),
|
||||
// Inputs
|
||||
.OE (OE));
|
||||
|
||||
Test7 test7(/*AUTOINST*/
|
||||
Test7 test7 ( /*AUTOINST*/
|
||||
// Outputs
|
||||
.Z11 (Z11),
|
||||
// Inputs
|
||||
.state (state[2:0]));
|
||||
|
||||
always @(posedge clk) begin
|
||||
state <= state + 1;
|
||||
always @(posedge clk) begin
|
||||
state <= state + 1;
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("[%0t] state=%d Z1=%b 2=%b 3=%b 4=%b 5=%b 6=%b 7=%b 8=%b 9=%b 10=%b 11=%b\n",
|
||||
$time, state, Z1,Z2,Z3,Z4,Z5,Z6,Z7,Z8,Z9,Z10,Z11);
|
||||
$write("[%0t] state=%d Z1=%b 2=%b 3=%b 4=%b 5=%b 6=%b 7=%b 8=%b 9=%b 10=%b 11=%b\n", $time,
|
||||
state, Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11);
|
||||
`endif
|
||||
|
||||
if(state == 0) begin
|
||||
if(Z1 !== 1'b1) $stop; // tests pullups
|
||||
if(Z2 !== 1'b1) $stop;
|
||||
if(Z3 !== 1'b1) $stop;
|
||||
if (state == 0) begin
|
||||
if (Z1 !== 1'b1) $stop; // tests pullups
|
||||
if (Z2 !== 1'b1) $stop;
|
||||
if (Z3 !== 1'b1) $stop;
|
||||
`ifndef VERILATOR
|
||||
if(Z4 !== 1'b1) $stop;
|
||||
if (Z4 !== 1'b1) $stop;
|
||||
`endif
|
||||
if(Z5 !== 1'b1) $stop;
|
||||
if(Z6 !== 1'b1) $stop;
|
||||
if(Z7 !== 1'b0) $stop;
|
||||
if(Z8 !== 1'b0) $stop;
|
||||
if(Z9 !== 1'b1) $stop;
|
||||
if(Z10 !== 4'b0001) $stop;
|
||||
if(Z11 !== 1'b0) $stop;
|
||||
end
|
||||
else if(state == 1) begin
|
||||
if(Z1 !== 1'b1) $stop; // tests pullup
|
||||
if(Z2 !== 1'b1) $stop;
|
||||
if(Z3 !== 1'b1) $stop;
|
||||
if (Z5 !== 1'b1) $stop;
|
||||
if (Z6 !== 1'b1) $stop;
|
||||
if (Z7 !== 1'b0) $stop;
|
||||
if (Z8 !== 1'b0) $stop;
|
||||
if (Z9 !== 1'b1) $stop;
|
||||
if (Z10 !== 4'b0001) $stop;
|
||||
if (Z11 !== 1'b0) $stop;
|
||||
end
|
||||
else if (state == 1) begin
|
||||
if (Z1 !== 1'b1) $stop; // tests pullup
|
||||
if (Z2 !== 1'b1) $stop;
|
||||
if (Z3 !== 1'b1) $stop;
|
||||
`ifndef VERILATOR
|
||||
if(Z4 !== 1'b1) $stop;
|
||||
if (Z4 !== 1'b1) $stop;
|
||||
`endif
|
||||
if(Z5 !== 1'b1) $stop;
|
||||
if(Z6 !== 1'b1) $stop;
|
||||
if(Z7 !== 1'b0) $stop;
|
||||
if(Z8 !== 1'b0) $stop;
|
||||
if(Z9 !== 1'b1) $stop;
|
||||
if(Z10 !== 4'b0001) $stop;
|
||||
if(Z11 !== 1'b1) $stop;
|
||||
end
|
||||
else if(state == 2) begin
|
||||
if(Z1 !== 1'b0) $stop; // tests output driver low
|
||||
if(Z2 !== 1'b0) $stop;
|
||||
if(Z3 !== 1'b1 && Z3 !== 1'bx) $stop; // Conflicts
|
||||
if (Z5 !== 1'b1) $stop;
|
||||
if (Z6 !== 1'b1) $stop;
|
||||
if (Z7 !== 1'b0) $stop;
|
||||
if (Z8 !== 1'b0) $stop;
|
||||
if (Z9 !== 1'b1) $stop;
|
||||
if (Z10 !== 4'b0001) $stop;
|
||||
if (Z11 !== 1'b1) $stop;
|
||||
end
|
||||
else if (state == 2) begin
|
||||
if (Z1 !== 1'b0) $stop; // tests output driver low
|
||||
if (Z2 !== 1'b0) $stop;
|
||||
if (Z3 !== 1'b1 && Z3 !== 1'bx) $stop; // Conflicts
|
||||
`ifndef VERILATOR
|
||||
if(Z4 !== 1'b1) $stop;
|
||||
if (Z4 !== 1'b1) $stop;
|
||||
`endif
|
||||
if(Z5 !== 1'b1) $stop;
|
||||
if(Z6 !== 1'b0) $stop;
|
||||
if(Z7 !== 1'b1) $stop;
|
||||
if(Z8 !== 1'b1) $stop;
|
||||
if(Z9 !== 1'b0) $stop;
|
||||
if(Z10 !== 4'b0010) $stop;
|
||||
//if(Z11 !== 1'bx) $stop; // Doesn't matter
|
||||
end
|
||||
else if(state == 3) begin
|
||||
if(Z1 !== 1'b1) $stop; // tests output driver high
|
||||
if(Z2 !== 1'b1) $stop;
|
||||
if(Z3 !== 1'b1) $stop;
|
||||
if (Z5 !== 1'b1) $stop;
|
||||
if (Z6 !== 1'b0) $stop;
|
||||
if (Z7 !== 1'b1) $stop;
|
||||
if (Z8 !== 1'b1) $stop;
|
||||
if (Z9 !== 1'b0) $stop;
|
||||
if (Z10 !== 4'b0010) $stop;
|
||||
//if(Z11 !== 1'bx) $stop; // Doesn't matter
|
||||
end
|
||||
else if (state == 3) begin
|
||||
if (Z1 !== 1'b1) $stop; // tests output driver high
|
||||
if (Z2 !== 1'b1) $stop;
|
||||
if (Z3 !== 1'b1) $stop;
|
||||
`ifndef VERILATOR
|
||||
if(Z4 !== 1'b1) $stop;
|
||||
if (Z4 !== 1'b1) $stop;
|
||||
`endif
|
||||
if(Z5 !== 1'b1) $stop;
|
||||
if(Z6 !== 1'b0) $stop;
|
||||
if(Z7 !== 1'b1) $stop;
|
||||
if(Z8 !== 1'b1) $stop;
|
||||
if(Z9 !== 1'b0) $stop;
|
||||
if(Z10 !== 4'b0010) $stop;
|
||||
if(Z11 !== 1'b1) $stop;
|
||||
end
|
||||
else if(state == 4) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
pullup(Z1);
|
||||
pullup(Z2);
|
||||
pullup(Z3);
|
||||
pullup(Z4);
|
||||
pullup(Z5);
|
||||
pullup(Z6);
|
||||
pulldown(Z7);
|
||||
pullup(Z8);
|
||||
pulldown(Z9);
|
||||
pulldown pd10[3:0] (Z10);
|
||||
if (Z5 !== 1'b1) $stop;
|
||||
if (Z6 !== 1'b0) $stop;
|
||||
if (Z7 !== 1'b1) $stop;
|
||||
if (Z8 !== 1'b1) $stop;
|
||||
if (Z9 !== 1'b0) $stop;
|
||||
if (Z10 !== 4'b0010) $stop;
|
||||
if (Z11 !== 1'b1) $stop;
|
||||
end
|
||||
else if (state == 4) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
pullup (Z1), (Z2);
|
||||
pullup (Z3);
|
||||
pullup (Z4);
|
||||
pullup (Z5);
|
||||
pullup (Z6);
|
||||
pulldown (Z7), (Z9);
|
||||
pullup (Z8);
|
||||
pulldown pd10[3:0] (Z10);
|
||||
endmodule
|
||||
|
||||
|
||||
module Test1(input OE, input A, inout Z1);
|
||||
assign Z1 = (OE) ? A : 1'bz;
|
||||
module Test1 (
|
||||
input OE,
|
||||
input A,
|
||||
inout Z1
|
||||
);
|
||||
assign Z1 = (OE) ? A : 1'bz;
|
||||
endmodule
|
||||
|
||||
module Test2(input OE, input A, inout Z2);
|
||||
assign Z2 = (OE) ? A : 1'bz;
|
||||
module Test2 (
|
||||
input OE,
|
||||
input A,
|
||||
inout Z2
|
||||
);
|
||||
assign Z2 = (OE) ? A : 1'bz;
|
||||
endmodule
|
||||
|
||||
|
||||
// mixed low-Z and tristate
|
||||
module Test3(input OE, input A, inout Z3);
|
||||
assign Z3 = (OE) ? A : 1'bz;
|
||||
assign Z3 = 1'b1;
|
||||
module Test3 (
|
||||
input OE,
|
||||
input A,
|
||||
inout Z3
|
||||
);
|
||||
assign Z3 = (OE) ? A : 1'bz;
|
||||
assign Z3 = 1'b1;
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
@ -168,37 +181,61 @@ endmodule
|
|||
`ifndef VERILATOR
|
||||
// Note verilator doesn't know to make Z4 a tristate unless marked an inout
|
||||
`endif
|
||||
module Test4(output Z4, inout Z5);
|
||||
module Test4 (
|
||||
output Z4,
|
||||
inout Z5
|
||||
);
|
||||
endmodule
|
||||
|
||||
|
||||
// AND gate tristates
|
||||
module Test5(input OE, inout Z6, inout Z7, inout Z8, inout Z9);
|
||||
assign Z6 = (OE) ? 1'b0 : 1'bz;
|
||||
assign Z7 = (OE) ? 1'b1 : 1'bz;
|
||||
assign Z8 = (OE) ? 1'bz : 1'b0;
|
||||
assign Z9 = (OE) ? 1'bz : 1'b1;
|
||||
module Test5 (
|
||||
input OE,
|
||||
inout Z6,
|
||||
inout Z7,
|
||||
inout Z8,
|
||||
inout Z9
|
||||
);
|
||||
assign Z6 = (OE) ? 1'b0 : 1'bz;
|
||||
assign Z7 = (OE) ? 1'b1 : 1'bz;
|
||||
assign Z8 = (OE) ? 1'bz : 1'b0;
|
||||
assign Z9 = (OE) ? 1'bz : 1'b1;
|
||||
endmodule
|
||||
|
||||
// AND gate tristates
|
||||
module Test6(input OE, inout [3:0] Z10);
|
||||
wire [1:0] i;
|
||||
Test6a a (.OE(OE), .Z({Z10[0],Z10[1]}));
|
||||
Test6a b (.OE(~OE), .Z({Z10[2],Z10[0]}));
|
||||
module Test6 (
|
||||
input OE,
|
||||
inout [3:0] Z10
|
||||
);
|
||||
wire [1:0] i;
|
||||
Test6a a (
|
||||
.OE(OE),
|
||||
.Z({Z10[0], Z10[1]})
|
||||
);
|
||||
Test6a b (
|
||||
.OE(~OE),
|
||||
.Z({Z10[2], Z10[0]})
|
||||
);
|
||||
endmodule
|
||||
|
||||
module Test6a(input OE, inout [1:0] Z);
|
||||
assign Z = (OE) ? 2'b01 : 2'bzz;
|
||||
module Test6a (
|
||||
input OE,
|
||||
inout [1:0] Z
|
||||
);
|
||||
assign Z = (OE) ? 2'b01 : 2'bzz;
|
||||
endmodule
|
||||
|
||||
module Test7(input [2:0] state, output reg Z11);
|
||||
always @(*) begin
|
||||
casez (state)
|
||||
3'b000: Z11 = 1'b0;
|
||||
3'b0?1: Z11 = 1'b1;
|
||||
default: Z11 = 1'bx;
|
||||
endcase
|
||||
end
|
||||
module Test7 (
|
||||
input [2:0] state,
|
||||
output reg Z11
|
||||
);
|
||||
always @(*) begin
|
||||
casez (state)
|
||||
3'b000: Z11 = 1'b0;
|
||||
3'b0?1: Z11 = 1'b1;
|
||||
default: Z11 = 1'bx;
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
|
||||
// This is not implemented yet
|
||||
|
|
|
|||
|
|
@ -2,4 +2,23 @@
|
|||
11 | trireg unsup;
|
||||
| ^~~~~~
|
||||
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
|
||||
%Error-UNSUPPORTED: t/t_wire_trireg_unsup.v:12:4: Unsupported: trireg
|
||||
12 | trireg (small) unsup_s;
|
||||
| ^~~~~~
|
||||
%Error: t/t_wire_trireg_unsup.v:12:12: syntax error, unexpected STRENGTH keyword (strong1/etc)
|
||||
12 | trireg (small) unsup_s;
|
||||
| ^~~~~
|
||||
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
|
||||
%Error-UNSUPPORTED: t/t_wire_trireg_unsup.v:13:4: Unsupported: trireg
|
||||
13 | trireg (medium) unsup_m;
|
||||
| ^~~~~~
|
||||
%Error: t/t_wire_trireg_unsup.v:13:12: syntax error, unexpected STRENGTH keyword (strong1/etc)
|
||||
13 | trireg (medium) unsup_m;
|
||||
| ^~~~~~
|
||||
%Error-UNSUPPORTED: t/t_wire_trireg_unsup.v:14:4: Unsupported: trireg
|
||||
14 | trireg (large) unsup_l;
|
||||
| ^~~~~~
|
||||
%Error: t/t_wire_trireg_unsup.v:14:12: syntax error, unexpected STRENGTH keyword (strong1/etc)
|
||||
14 | trireg (large) unsup_l;
|
||||
| ^~~~~
|
||||
%Error: Exiting due to
|
||||
|
|
|
|||
|
|
@ -9,5 +9,8 @@
|
|||
module t;
|
||||
|
||||
trireg unsup;
|
||||
trireg (small) unsup_s;
|
||||
trireg (medium) unsup_m;
|
||||
trireg (large) unsup_l;
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
Loading…
Reference in New Issue