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Tests: Reformat some tests to mostly verilog-format standard. No test functional change.

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This commit is contained in:
Wilson Snyder
2026-09-12 08:38:51 -04:00
parent 012b647833
commit c8a75e9b4d
78 changed files with 630 additions and 694 deletions
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test_regress/t/t_assert_nonconsec_rep.v
+9 -10
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@@ -29,25 +29,24 @@ module t (
int count_fail4 = 0;
// Test 1: a[=2] |-> b (overlapping implication, 2 non-consecutive occurrences)
assert property (@(posedge clk) a[=2] |-> b)
else count_fail1 <= count_fail1 + 1;
assert property (@(posedge clk) a [= 2] |-> b)
else count_fail1 <= count_fail1 + 1;
// Test 2: a[=1] |-> c (single occurrence, overlapping)
assert property (@(posedge clk) a[=1] |-> c)
else count_fail2 <= count_fail2 + 1;
assert property (@(posedge clk) a [= 1] |-> c)
else count_fail2 <= count_fail2 + 1;
// Test 3: a[=3] |=> d (3 occurrences, non-overlapping implication)
assert property (@(posedge clk) a[=3] |=> d)
else count_fail3 <= count_fail3 + 1;
assert property (@(posedge clk) a [= 3] |=> d)
else count_fail3 <= count_fail3 + 1;
// Test 4: standalone nonconsec rep (no implication)
assert property (@(posedge clk) b[=2])
else count_fail4 <= count_fail4 + 1;
assert property (@(posedge clk) b [= 2])
else count_fail4 <= count_fail4 + 1;
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x a=%b b=%b c=%b d=%b\n",
$time, cyc, crc, a, b, c, d);
$write("[%0t] cyc==%0d crc=%x a=%b b=%b c=%b d=%b\n", $time, cyc, crc, a, b, c, d);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
test_regress/t/t_assign_expr.v
+4 -3
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@@ -22,7 +22,8 @@ module t;
function int foo();
x += 1;
return 1;
endfunction;
endfunction
;
// verilator lint_off ASSIGNEQEXPR
initial begin
@@ -109,9 +110,9 @@ module t;
`checkd(arr[1], 3);
`checkd(x, 2);
arr[foo() + 1] = 6;
arr[foo()+1] = 6;
`checkd(x, 3);
arr[foo() + 1] -= 5;
arr[foo()+1] -= 5;
`checkd(arr[2], 1);
`checkd(x, 4);
test_regress/t/t_bind.v
+4 -5
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@@ -7,11 +7,10 @@
bit a_finished;
bit b_finished;
module t ( /*AUTOARG*/
// Inputs
clk
);
input clk;
module t (
input clk
);
wire [31:0] o;
wire si = 1'b0;
test_regress/t/t_class_localparam_dotref.v
+1 -1
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@@ -37,7 +37,7 @@ typedef C#(1) inst1;
typedef C#(4) chain_a;
typedef chain_a chain_b;
module t ( /*AUTOARG*/);
module t;
// Wilson's exact case: typedef-aliased paramed class lparam.
localparam int LP_TYPEDEF_LPARAM = inst0::b;
test_regress/t/t_class_super_new.v
+1 -2
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@@ -106,8 +106,7 @@ class NewWithoutSuperParam #(
endfunction
endclass
module t ( /*AUTOARG*/
);
module t;
class FooInModule;
int x;
test_regress/t/t_cover_sequence.v
+1 -2
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@@ -79,8 +79,7 @@ module t (
hit_fixed_ring_multiplicity++;
// The same multiplicity occupies each endpoint of a consecutive-repetition range ring.
cover sequence (((cyc <= 1) [* 1: 2]) ##0 ((cyc >= 1) [* 1: 3]))
hit_range_ring_multiplicity++;
cover sequence (((cyc <= 1) [* 1: 2]) ##0 ((cyc >= 1) [* 1: 3])) hit_range_ring_multiplicity++;
// Multiplicity crosses a fixed-delay ring before entering a range ring.
cover sequence ((((cyc <= 1) [* 1: 2]) ##0 ((cyc >= 1) ##2 (cyc >= 3))) ##0
test_regress/t/t_coverage_prop_seq.v
+1 -1
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@@ -6,7 +6,7 @@
module t;
logic clk = 1'b0;
// verilog_format: off
property c_prop;
@(negedge clk)
1'b1;
test_regress/t/t_covergroup_clocked_sample.v
+2 -4
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@@ -4,11 +4,9 @@
// SPDX-FileCopyrightText: 2025 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t ( /*AUTOARG*/
// Inputs
clk
module t (
input clk
);
input clk;
logic [1:0] data;
test_regress/t/t_covergroup_empty.v
+2 -4
View File
@@ -6,11 +6,9 @@
// Test: Empty covergroup (no coverpoints)
// Expected: Should compile, coverage should be 100% (nothing to cover)
module t ( /*AUTOARG*/
// Inputs
clk
module t (
input clk
);
input clk;
logic [7:0] value;
test_regress/t/t_display_pattern_format.v
+6 -2
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@@ -64,8 +64,12 @@ module t;
`ifdef QUESTA
escaped_expected = {"\"", escaped, "\""};
`else
escaped_expected = {"\"quote=\\\" slash=\\\\ line=\\n cr=\\r tab=\\t bell=\\007 ",
"form=\\014 vert=\\013 ctrl=\\001 ", plain, "\""};
escaped_expected = {
"\"quote=\\\" slash=\\\\ line=\\n cr=\\r tab=\\t bell=\\007 ",
"form=\\014 vert=\\013 ctrl=\\001 ",
plain,
"\""
};
`endif
formatted = $sformatf("%p", plain);
`checks(formatted, {"\"", plain, "\""});
test_regress/t/t_exprstmt_on_lhs_of_nba.v
+8 -13
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@@ -4,24 +4,19 @@
// SPDX-FileCopyrightText: 2025 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t ( /*AUTOARG*/
// Outputs
data_o,
// Inputs
clk, rst_i, write_valid_i, write_front_i, read_valid_i, data_i
module t (
input clk,
input rst_i,
input write_valid_i,
input write_front_i,
input read_valid_i,
input [31:0] data_i,
output [31:0] data_o
);
localparam NR_ELEMENTS = 16;
localparam DATAW = 32;
input clk;
input rst_i;
input write_valid_i;
input write_front_i;
input read_valid_i;
input [31:0] data_i;
output [31:0] data_o;
reg [31:0] FIFOContent[NR_ELEMENTS-1:0];
typedef logic [$clog2(NR_ELEMENTS)-1:0] FIFOPointer_t;
test_regress/t/t_extend_c_class.v
+4 -9
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@@ -29,15 +29,10 @@ module t (
end
endmodule
module t_extend_c_class_v (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [31:0] in;
output logic [31:0] out;
module t_extend_c_class_v (
input [31:0] in,
output logic [31:0] out
);
always @* begin
// When "in" changes, call my method
test_regress/t/t_flag_csplit_eval.v
+11 -16
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@@ -4,34 +4,29 @@
// SPDX-FileCopyrightText: 2005 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Outputs
cnt0, cnt1,
// Inputs
clk, clk1
);
input clk;
input clk1;
module t (
input clk,
input clk1,
output int cnt0,
output int cnt1
);
output int cnt0;
output int cnt1;
always @ (posedge clk) cnt0 <= cnt0 + 1;
always @ (posedge clk1) cnt1 <= cnt1 + 1;
always @(posedge clk) cnt0 <= cnt0 + 1;
always @(posedge clk1) cnt1 <= cnt1 + 1;
final if (cnt0 == 0) $stop;
final if (cnt1 != 0) $stop;
// Some dummy statements to make the code larger
generate
genvar i;
for (i = 0 ; i < 100; i = i + 1) begin
genvar i;
for (i = 0; i < 100; i = i + 1) begin
always @(posedge clk) $c("/*", i, "*/");
end
endgenerate
always_comb begin
if (cnt0==99) begin
if (cnt0 == 99) begin
$write("*-* All Finished *-*\n");
$finish;
end
test_regress/t/t_foreach_nested.v
+3
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@@ -10,13 +10,16 @@ class Bar;
Foo foo;
function automatic void test();
// verilog_format: off
foreach(this.foo.x[i])
foreach(this.foo.x[i][j])
this.foo.x[i][j] = i * j;
for (int i = 0; i < 9; i++)
for (int j = 0; j < 9; j++)
if (this.foo.x[i][j] != i * j) $stop;
// verilog_format: on
endfunction
endclass
module t;
test_regress/t/t_gate_array.v
+39 -38
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@@ -18,18 +18,19 @@ module t (
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [63:0] out; // From test of Test.v
wire [63:0] out2; // From test of Test.v
wire [63:0] out; // From test of Test.v
wire [63:0] out2; // From test of Test.v
// End of automatics
Test test ( /*AUTOINST*/
// Outputs
.out (out[63:0]),
.out2 (out2[63:0]),
// Inputs
.clk (clk),
.a (a[7:0]),
.b (b[7:0]));
// Outputs
.out(out[63:0]),
.out2(out2[63:0]),
// Inputs
.clk(clk),
.a(a[7:0]),
.b(b[7:0])
);
// Aggregate outputs into a single result vector
wire [63:0] result = {out};
@@ -37,41 +38,41 @@ module t (
// Test loop
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc < 10) begin
sum <= 64'h0;
end
else if (cyc < 90) begin
if (out2 !== out) $stop;
end
else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h0908a1f2194d24ee
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc < 10) begin
sum <= 64'h0;
end
else if (cyc < 90) begin
if (out2 !== out) $stop;
end
else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h0908a1f2194d24ee
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (
input clk,
input [7:0] a,
input [7:0] b,
output reg [63:0] out,
output reg [63:0] out2
input clk,
input [7:0] a,
input [7:0] b,
output reg [63:0] out,
output reg [63:0] out2
);
// Also cover comma syntax
test_regress/t/t_interface_array_loop.v
+2 -5
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@@ -64,13 +64,10 @@ module l1_param_sub #(
end
endmodule
module t ( /*AUTOARG*/
// Inputs
clk
module t (
input clk
);
input clk;
localparam N = 4;
simple_if ifaces[N-1:0] ();
test_regress/t/t_interface_array_loop_bad.out
+4 -4
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@@ -1,10 +1,10 @@
%Error: t/t_interface_array_loop_bad.v:27:14: Expecting expression to be constant, but variable isn't const: 'i'
%Error: t/t_interface_array_loop_bad.v:24:14: Expecting expression to be constant, but variable isn't const: 'i'
: ... note: In instance 't'
27 | ifaces[i].value = 8'(i);
24 | ifaces[i].value = 8'(i);
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_interface_array_loop_bad.v:27:13: Could not expand constant selection inside dotted reference: 'i'
%Error: t/t_interface_array_loop_bad.v:24:13: Could not expand constant selection inside dotted reference: 'i'
: ... note: In instance 't'
27 | ifaces[i].value = 8'(i);
24 | ifaces[i].value = 8'(i);
| ^
%Error: Exiting due to
test_regress/t/t_interface_array_loop_bad.v
+2 -5
View File
@@ -8,13 +8,10 @@ interface simple_bad_if;
logic [7:0] value;
endinterface
module t ( /*AUTOARG*/
// Inputs
clk
module t (
input clk
);
input clk;
localparam N = 4;
simple_bad_if ifaces[N-1:0] ();
test_regress/t/t_interface_derived_type.v
+2 -5
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@@ -22,13 +22,10 @@ interface intf #(
`endif
endinterface
module t ( /*AUTOARG*/
// Inputs
clk
module t (
input clk
);
input clk;
// finish report
always @(posedge clk) begin
$write("*-* All Finished *-*\n");
test_regress/t/t_interface_modport.v
+3 -5
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@@ -42,12 +42,10 @@ module inout_mod_wrap(input we, inout d);
inout_mod prph (.*);
endmodule
module t (/*AUTOARG*/
// Inputs
clk
);
module t (
input clk
);
input clk;
integer cyc=1;
counter_if c1_data();
test_regress/t/t_interface_modport_dir_bad.v
+4 -9
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@@ -42,16 +42,11 @@ module parentSourceMod (
endmodule
module t ( /*AUTOARG*/
// Outputs
data,
// Inputs
clk,
rst
module t (
input clk,
input rst,
output logic data
);
input clk;
input rst;
output logic data;
validData ctrl (
.clk,
test_regress/t/t_interface_modport_import.v
+2 -4
View File
@@ -23,11 +23,9 @@ interface test_if;
endinterface // test_if
module t ( /*AUTOARG*/
// Inputs
clk
module t (
input clk
);
input clk;
test_if i ();
test_regress/t/t_interface_nest.v
+2 -4
View File
@@ -34,11 +34,9 @@ module mod1 (
endmodule
module t ( /*AUTOARG*/
// Inputs
clk
module t (
input clk
);
input clk;
if2 i2a ();
if2 i2b ();
test_regress/t/t_interface_param1.v
+2 -5
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@@ -6,12 +6,9 @@
//bug692
module t ( /*AUTOARG*/
// Inputs
clk
module t (
input wire clk
);
input wire clk;
wire [31:0] result;
test_if #(.ID(3)) s ();
sub_test U_SUB_TEST (
test_regress/t/t_interface_typedef.v
+2 -4
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@@ -17,11 +17,9 @@ interface ifc #(
typedef struct packed {logic [WIDTH-1:0] data;} struct_t;
endinterface
module t ( /*AUTOARG*/
// Inputs
clk
module t (
input clk
);
input clk;
ifc #(10) i_ifc10 ();
ifc #(20) i_ifc20 ();
test_regress/t/t_let.v
+1 -1
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@@ -15,7 +15,7 @@ module t;
let B() = 20;
let C(a) = 30 + a;
let D(a, b) = 30 + a + b;
let E(a=1, b=7) = 30 + a + b;
let E(a = 1, b = 7) = 30 + a + b;
let F(untyped a) = 30 + a;
initial begin
test_regress/t/t_lint_waitconst_bad.out
+9 -9
View File
@@ -1,12 +1,12 @@
%Warning-WAITCONST: t/t_timing_wait1.v:52:10: Wait statement condition is constant
52 | wait(1);
| ^
%Warning-WAITCONST: t/t_timing_wait1.v:62:11: Wait statement condition is constant
62 | wait (1);
| ^
... For warning description see https://verilator.org/warn/WAITCONST?v=latest
... Use "/* verilator lint_off WAITCONST */" and lint_on around source to disable this message.
%Warning-WAITCONST: t/t_timing_wait1.v:54:12: Wait statement condition is constant
54 | wait(0 < 1) $write("*-* All Finished *-*\n");
| ^
%Warning-WAITCONST: t/t_timing_wait1.v:59:18: Wait statement condition is constant
59 | initial wait(1 == 0) $stop;
| ^~
%Warning-WAITCONST: t/t_timing_wait1.v:64:13: Wait statement condition is constant
64 | wait (0 < 1) $write("*-* All Finished *-*\n");
| ^
%Warning-WAITCONST: t/t_timing_wait1.v:69:19: Wait statement condition is constant
69 | initial wait (1 == 0) $stop;
| ^~
%Error: Exiting due to
test_regress/t/t_lparam_assign_iface_array_typedef2.v
+14 -15
View File
@@ -10,21 +10,20 @@
// verilog_format: on
package a_pkg;
typedef struct packed {
int unsigned IdBits;
} cfg_t;
typedef struct packed {int unsigned IdBits;} cfg_t;
endpackage
interface bus_if #(
parameter a_pkg::cfg_t cfg = 0
)();
parameter a_pkg::cfg_t cfg = 0
) ();
typedef logic [cfg.IdBits-1:0] id_t;
id_t id;
endinterface
module a_mod #()(
bus_if bus_tgt_io_a [2]
,bus_if bus_mst_io_a [2]
module a_mod #(
) (
bus_if bus_tgt_io_a[2]
, bus_if bus_mst_io_a[2]
);
localparam type tgt_id_t = bus_tgt_io_a[0].id_t;
@@ -41,18 +40,18 @@ module a_mod #()(
endmodule
module t(
input logic clk
module t (
input logic clk
);
localparam a_pkg::cfg_t cfg0 = '{IdBits: 5};
localparam a_pkg::cfg_t cfg1 = '{IdBits: 10};
bus_if #(.cfg(cfg0)) bus_tgt_io_a [2] ();
bus_if #(.cfg(cfg1)) bus_mst_io_a [2] ();
bus_if #(.cfg(cfg0)) bus_tgt_io_a[2] ();
bus_if #(.cfg(cfg1)) bus_mst_io_a[2] ();
a_mod a_mod0(
.bus_tgt_io_a(bus_tgt_io_a),
.bus_mst_io_a(bus_mst_io_a)
a_mod a_mod0 (
.bus_tgt_io_a(bus_tgt_io_a),
.bus_mst_io_a(bus_mst_io_a)
);
initial begin
test_regress/t/t_lparam_assign_iface_typedef.v
+8 -10
View File
@@ -12,24 +12,22 @@
// verilog_format: on
interface x_if #(
parameter int p_awidth = 4,
parameter int p_dwidth = 7
)();
parameter int p_awidth = 4,
parameter int p_dwidth = 7
) ();
typedef struct packed {
logic [p_awidth-1:0] addr;
logic [p_dwidth-1:0] data;
} rq_t;
typedef struct packed {
logic [p_dwidth-1:0] data;
} rs_t;
typedef struct packed {logic [p_dwidth-1:0] data;} rs_t;
endinterface
module top();
module top ();
x_if #(
.p_awidth(16),
.p_dwidth(8)
) if0();
.p_awidth(16),
.p_dwidth(8)
) if0 ();
localparam type p0_rq_t = if0.rq_t;
localparam type p0_rs_t = if0.rs_t;
test_regress/t/t_lparam_assign_iface_typedef_nested.v
+12 -16
View File
@@ -8,34 +8,30 @@
//
interface y_if #(
parameter int p_awidth = 3
)();
typedef struct packed {
logic [p_awidth-1:0] addr;
} rq2_t;
parameter int p_awidth = 3
) ();
typedef struct packed {logic [p_awidth-1:0] addr;} rq2_t;
endinterface
interface x_if #(
parameter int p_awidth = 4,
parameter int p_dwidth = 7
)();
parameter int p_awidth = 4,
parameter int p_dwidth = 7
) ();
typedef struct packed {
logic [p_awidth-1:0] addr;
logic [p_dwidth-1:0] data;
} rq_t;
typedef struct packed {
logic [p_dwidth-1:0] data;
} rs_t;
typedef struct packed {logic [p_dwidth-1:0] data;} rs_t;
y_if#(.p_awidth(p_awidth)) y_if0();
y_if #(.p_awidth(p_awidth)) y_if0 ();
endinterface
module top();
module top ();
x_if #(
.p_awidth(16),
.p_dwidth(8)
) if0();
.p_awidth(16),
.p_dwidth(8)
) if0 ();
localparam type p0_rq2_t = if0.y_if0.rq2_t;
test_regress/t/t_lparam_assign_iface_typedef_nested6.v
+15 -16
View File
@@ -8,32 +8,31 @@
//
interface x_if #(
parameter int p_awidth = 4
)();
typedef struct packed {
logic [p_awidth-1:0] addr;
} rq_t;
parameter int p_awidth = 4
) ();
typedef struct packed {logic [p_awidth-1:0] addr;} rq_t;
endinterface
interface y_if #(
parameter int p_dwidth = 7
)();
typedef struct packed {
logic [p_dwidth-1:0] data;
} rs_t;
parameter int p_dwidth = 7
) ();
typedef struct packed {logic [p_dwidth-1:0] data;} rs_t;
endinterface
interface z_if #(
parameter int p_awidth = 3,
parameter int p_dwidth = 9
parameter int p_awidth = 3,
parameter int p_dwidth = 9
);
x_if #(p_awidth) x_if0();
y_if #(p_dwidth) y_if0();
x_if #(p_awidth) x_if0 ();
y_if #(p_dwidth) y_if0 ();
endinterface
module top();
module top ();
z_if #(.p_awidth(16) ,.p_dwidth(8)) if0();
z_if #(
.p_awidth(16),
.p_dwidth(8)
) if0 ();
localparam type rq_t = if0.x_if0.rq_t;
test_regress/t/t_lparam_assign_iface_typedef_nested_mod1.v
+11 -12
View File
@@ -9,26 +9,25 @@
//
interface bus_if #(
parameter int p_awidth = 4,
parameter int p_dwidth = 7
parameter int p_awidth = 4,
parameter int p_dwidth = 7
);
typedef struct packed {
logic [p_awidth-1:0] addr;
} rq_t;
typedef struct packed {logic [p_awidth-1:0] addr;} rq_t;
endinterface
module a_mod(
bus_if bus_io
module a_mod (
bus_if bus_io
);
localparam type bus_rq_t = bus_io.rq_t;
endmodule
module top();
bus_if #(.p_awidth(16), .p_dwidth(8)) bus_io();
module top ();
bus_if #(
.p_awidth(16),
.p_dwidth(8)
) bus_io ();
a_mod a_mod_inst(
.bus_io(bus_io)
);
a_mod a_mod_inst (.bus_io(bus_io));
initial begin
#1;
test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg2.v
+7 -10
View File
@@ -16,20 +16,17 @@ package a_pkg;
} cfg_t;
endpackage
module a_mod #(parameter a_pkg::cfg_t cfg=0)(
input logic a
module a_mod #(
parameter a_pkg::cfg_t cfg = 0
) (
input logic a
);
endmodule
module top();
localparam a_pkg::cfg_t cfg = '{
awidth : 16
,dwidth : 8
};
module top ();
localparam a_pkg::cfg_t cfg = '{awidth : 16, dwidth : 8};
a_mod #(cfg) a_mod_inst(
.a(1'b0)
);
a_mod #(cfg) a_mod_inst (.a(1'b0));
initial begin
#1;
test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg3.v
+7 -13
View File
@@ -14,28 +14,22 @@ endpackage
package cb;
typedef struct packed {
int unsigned XdatSize; // raw packet data size
int unsigned XdatSize; // raw packet data size
} cfg_t;
endpackage
module a_mod();
typedef struct packed {
logic hdr_vld;
} cmd_meta_t;
module a_mod ();
typedef struct packed {logic hdr_vld;} cmd_meta_t;
typedef struct packed {
cmd_meta_t meta;
} cmd_beat_t;
typedef struct packed {cmd_meta_t meta;} cmd_beat_t;
typedef logic [3:0] cc_index_t;
localparam cb::cfg_t cb_cfg = '{
XdatSize:$bits(cmd_beat_t)
};
localparam cb::cfg_t cb_cfg = '{XdatSize: $bits(cmd_beat_t)};
endmodule
module top();
a_mod a_mod_inst();
module top ();
a_mod a_mod_inst ();
initial begin
#1;
test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg4.v
+16 -24
View File
@@ -6,48 +6,40 @@
//
package aer;
typedef struct packed {
int unsigned NumCca;
} cfg_t;
typedef struct packed {int unsigned NumCca;} cfg_t;
endpackage
package cca;
typedef struct packed {
int unsigned NumCc;
} cfg_t;
typedef struct packed {int unsigned NumCc;} cfg_t;
endpackage
package amb;
typedef struct packed {
logic start;
} rule_t;
typedef struct packed {logic start;} rule_t;
endpackage
interface tb_if #(parameter cca::cfg_t cfg=0)();
interface tb_if #(
parameter cca::cfg_t cfg = 0
) ();
typedef logic [$clog2(cfg.NumCc)-1:0] cc_index_t;
endinterface
module modA#(
parameter aer::cfg_t cfg=0,
//
localparam type rule_t = amb::rule_t
)();
module modA #(
parameter aer::cfg_t cfg = 0,
//
localparam type rule_t = amb::rule_t
) ();
localparam cca::cfg_t cca_cfg = '{
NumCc : 4
};
localparam cca::cfg_t cca_cfg = '{NumCc : 4};
tb_if #(cca_cfg) tb_io();
tb_if #(cca_cfg) tb_io ();
localparam type cc_index_t = tb_io.cc_index_t;
endmodule
module tb();
module tb ();
localparam aer::cfg_t aer_cfg= '{
NumCca : 2
};
localparam aer::cfg_t aer_cfg = '{NumCca : 2};
modA #(aer_cfg) modA();
modA #(aer_cfg) modA ();
initial begin
#1;
test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg5.v
+14 -22
View File
@@ -6,46 +6,38 @@
//
package aer;
typedef struct packed {
int unsigned NumCca;
} cfg_t;
typedef struct packed {int unsigned NumCca;} cfg_t;
endpackage
package cca;
typedef struct packed {
int unsigned NumCc;
} cfg_t;
typedef struct packed {int unsigned NumCc;} cfg_t;
endpackage
package amb;
typedef struct packed {
logic start;
} rule_t;
typedef struct packed {logic start;} rule_t;
endpackage
interface tb_if #(parameter cca::cfg_t cfg=0)();
interface tb_if #(
parameter cca::cfg_t cfg = 0
) ();
typedef logic [$clog2(cfg.NumCc)-1:0] cc_index_t;
endinterface
module modA#(
localparam type rule_t = amb::rule_t
)();
module modA #(
localparam type rule_t = amb::rule_t
) ();
localparam cca::cfg_t cca_cfg = '{
NumCc : 4
};
localparam cca::cfg_t cca_cfg = '{NumCc : 4};
tb_if #(cca_cfg) tb_io();
tb_if #(cca_cfg) tb_io ();
localparam type cc_index_t = tb_io.cc_index_t;
endmodule
module tb();
module tb ();
localparam aer::cfg_t aer_cfg= '{
NumCca : 2
};
localparam aer::cfg_t aer_cfg = '{NumCca : 2};
modA #() modA();
modA #() modA ();
initial begin
#1;
test_regress/t/t_net_dtype_bad.out
+19 -19
View File
@@ -1,37 +1,37 @@
%Error: t/t_net_dtype_bad.v:25:15: Net 'bad_real' data type must be 4-state integral or array/union/struct of such (IEEE 1800-2023 6.7.1)
%Error: t/t_net_dtype_bad.v:19:15: Net 'bad_real' data type must be 4-state integral or array/union/struct of such (IEEE 1800-2023 6.7.1)
: ... note: In instance 't'
25 | wire real_t bad_real;
19 | wire real_t bad_real;
| ^~~~~~~~
t/t_net_dtype_bad.v:11:11: ... Location of failing data type 'real'
11 | typedef real real_t;
| ^~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_net_dtype_bad.v:27:12: Net 'bad_class' data type must be 4-state integral or array/union/struct of such (IEEE 1800-2023 6.7.1)
%Error: t/t_net_dtype_bad.v:21:12: Net 'bad_class' data type must be 4-state integral or array/union/struct of such (IEEE 1800-2023 6.7.1)
: ... note: In instance 't'
27 | wire Cls bad_class;
21 | wire Cls bad_class;
| ^~~~~~~~~
t/t_net_dtype_bad.v:27:8: ... Location of failing data type 'class{}Cls'
27 | wire Cls bad_class;
t/t_net_dtype_bad.v:21:8: ... Location of failing data type 'class{}Cls'
21 | wire Cls bad_class;
| ^~~
%Error: t/t_net_dtype_bad.v:29:15: Net 'bad_string' data type must be 4-state integral or array/union/struct of such (IEEE 1800-2023 6.7.1)
%Error: t/t_net_dtype_bad.v:23:15: Net 'bad_string' data type must be 4-state integral or array/union/struct of such (IEEE 1800-2023 6.7.1)
: ... note: In instance 't'
29 | wire string bad_string;
23 | wire string bad_string;
| ^~~~~~~~~~
t/t_net_dtype_bad.v:29:8: ... Location of failing data type 'string'
29 | wire string bad_string;
t/t_net_dtype_bad.v:23:8: ... Location of failing data type 'string'
23 | wire string bad_string;
| ^~~~~~
%Error: t/t_net_dtype_bad.v:31:12: Net 'bad_bit' data type must be 4-state integral or array/union/struct of such (IEEE 1800-2023 6.7.1)
%Error: t/t_net_dtype_bad.v:25:12: Net 'bad_bit' data type must be 4-state integral or array/union/struct of such (IEEE 1800-2023 6.7.1)
: ... note: In instance 't'
31 | wire bit bad_bit;
25 | wire bit bad_bit;
| ^~~~~~~
t/t_net_dtype_bad.v:31:8: ... Location of failing data type 'bit'
31 | wire bit bad_bit;
t/t_net_dtype_bad.v:25:8: ... Location of failing data type 'bit'
25 | wire bit bad_bit;
| ^~~
%Error: t/t_net_dtype_bad.v:33:14: Net 'bad_struct' data type must be 4-state integral or array/union/struct of such (IEEE 1800-2023 6.7.1)
%Error: t/t_net_dtype_bad.v:27:14: Net 'bad_struct' data type must be 4-state integral or array/union/struct of such (IEEE 1800-2023 6.7.1)
: ... note: In instance 't'
33 | wire bad_t bad_struct;
27 | wire bad_t bad_struct;
| ^~~~~~~~~~
t/t_net_dtype_bad.v:14:5: ... Location of failing data type 'bit'
14 | bit m_bit;
| ^~~
t/t_net_dtype_bad.v:13:26: ... Location of failing data type 'bit'
13 | typedef struct packed {bit m_bit;} bad_t;
| ^~~
%Error: Exiting due to
test_regress/t/t_net_dtype_bad.v
+3 -9
View File
@@ -10,17 +10,11 @@ endclass
module t;
typedef real real_t;
typedef struct packed {
bit m_bit;
} bad_t;
typedef struct packed {bit m_bit;} bad_t;
typedef struct {
logic m_bit;
} ok_unpk_t;
typedef struct {logic m_bit;} ok_unpk_t;
typedef struct packed {
logic m_bit;
} ok_t;
typedef struct packed {logic m_bit;} ok_t;
wire real_t bad_real; // <--- Error - bad net type
test_regress/t/t_process_copy_constr.v
+1 -2
View File
@@ -11,8 +11,7 @@ class Cls;
endfunction
endclass
module t ( /*AUTOARG*/
);
module t;
initial begin
Cls c, d;
c = new;
test_regress/t/t_property_disable_iff_unsup.out
+2 -2
View File
@@ -1,6 +1,6 @@
%Error-UNSUPPORTED: t/t_property_disable_iff_unsup.v:20:48: Unsupported: $sampled inside disabled condition of a sequence
%Error-UNSUPPORTED: t/t_property_disable_iff_unsup.v:18:48: Unsupported: $sampled inside disabled condition of a sequence
: ... note: In instance 't'
20 | assert property (@(posedge clk) disable iff ($sampled(val)) s_eventually 1);
18 | assert property (@(posedge clk) disable iff ($sampled(val)) s_eventually 1);
| ^~~~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to
test_regress/t/t_property_disable_iff_unsup.v
+2 -4
View File
@@ -4,12 +4,10 @@
// SPDX-FileCopyrightText: 2026 Antmicro
// SPDX-License-Identifier: CC0-1.0
module t ( /*AUTOARG*/
// Inputs
clk
module t (
input clk
);
input clk;
bit val;
always @(posedge clk) begin
test_regress/t/t_property_named.v
+3 -4
View File
@@ -4,11 +4,10 @@
// SPDX-FileCopyrightText: 2022 Antmicro Ltd
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
clk
);
module t (
input clk
);
input clk;
int cyc = 0;
logic val = 0;
test_regress/t/t_property_s_eventually_iface.v
+1 -1
View File
@@ -14,7 +14,7 @@ interface my_if (
assert property (@(posedge clk) s_eventually a);
endinterface
module t ( /*AUTOARG*/);
module t;
bit clk = 0;
initial forever #1 clk = ~clk;
test_regress/t/t_property_sexpr.out
+59 -59
View File
@@ -1,134 +1,134 @@
[2] triggered e1
[4] triggered e1
[4] single delay with const stmt, fileline:99
[4] single delay with const stmt, fileline:96
[6] triggered e1
[6] single delay with const stmt, fileline:99
[6] single delay with const stmt, fileline:96
[8] triggered e2
[10] triggered e2
[10] single delay with var stmt, fileline:102
[10] single delay with var stmt, fileline:99
[12] triggered e2
[12] single delay with var else, fileline:103
[12] single delay with var else, fileline:100
[14] triggered e2
[14] single delay with var stmt, fileline:102
[14] single delay with var stmt, fileline:99
[16] triggered e2
[16] single delay with var else, fileline:103
[16] single delay with var else, fileline:100
[18] triggered e2
[18] single delay with var stmt, fileline:102
[18] single delay with var stmt, fileline:99
[20] triggered e3
[22] triggered e3
[22] stmt1, fileline:106
[22] stmt2, fileline:107
[22] stmt1, fileline:103
[22] stmt2, fileline:104
[24] triggered e3
[24] else1, fileline:110
[24] else2, fileline:111
[24] else1, fileline:107
[24] else2, fileline:108
[26] triggered e3
[26] stmt1, fileline:106
[26] stmt2, fileline:107
[26] stmt1, fileline:103
[26] stmt2, fileline:104
[28] triggered e3
[28] else1, fileline:110
[28] else2, fileline:111
[28] else1, fileline:107
[28] else2, fileline:108
[30] triggered e4
[32] triggered e4
[34] triggered e4
[34] single multi-cycle delay with var stmt, fileline:115
[34] single multi-cycle delay with var stmt, fileline:112
[36] triggered e4
[36] single multi-cycle delay with var else, fileline:116
[36] single multi-cycle delay with var else, fileline:113
[38] triggered e4
[38] single multi-cycle delay with var stmt, fileline:115
[38] single multi-cycle delay with var stmt, fileline:112
[40] triggered e5
[42] triggered e5
[42] single delay with var brackets 1 stmt, fileline:119
[42] single delay with var brackets 1 stmt, fileline:116
[44] triggered e5
[44] single delay with var brackets 1 else, fileline:120
[44] single delay with var brackets 1 else, fileline:117
[46] triggered e5
[46] single delay with var brackets 1 stmt, fileline:119
[46] single delay with var brackets 1 stmt, fileline:116
[48] triggered e5
[48] single delay with var brackets 1 else, fileline:120
[48] single delay with var brackets 1 else, fileline:117
[50] triggered e6
[52] triggered e6
[52] single delay with var brackets 2 else, fileline:124
[52] single delay with var brackets 2 else, fileline:121
[54] triggered e6
[54] single delay with var brackets 2 stmt, fileline:123
[54] single delay with var brackets 2 stmt, fileline:120
[56] triggered e6
[56] single delay with var brackets 2 else, fileline:124
[56] single delay with var brackets 2 else, fileline:121
[58] triggered e6
[58] single delay with var brackets 2 stmt, fileline:123
[58] single delay with var brackets 2 stmt, fileline:120
[60] triggered e7
[62] triggered e7
[62] single delay with and var stmt, fileline:127
[62] single delay with and var stmt, fileline:124
[64] triggered e7
[64] single delay with and var else, fileline:128
[64] single delay with and var else, fileline:125
[66] triggered e7
[66] single delay with and var else, fileline:128
[66] single delay with and var else, fileline:125
[68] triggered e7
[68] single delay with and var else, fileline:128
[68] single delay with and var else, fileline:125
[70] triggered e8
[72] triggered e8
[72] single delay with negated var stmt, fileline:131
[72] single delay with negated var stmt, fileline:128
[74] triggered e8
[74] single delay with negated var else, fileline:132
[74] single delay with negated var else, fileline:129
[76] triggered e8
[76] single delay with negated var stmt, fileline:131
[76] single delay with negated var stmt, fileline:128
[78] triggered e8
[78] single delay with negated var else, fileline:132
[78] single delay with negated var else, fileline:129
[80] triggered e9
[82] triggered e9
[82] single delay with negated var brackets else, fileline:137
[82] single delay with negated var brackets else, fileline:134
[84] triggered e9
[84] single delay with negated var brackets stmt, fileline:135
[84] single delay with negated var brackets stmt, fileline:132
[86] triggered e9
[86] single delay with negated var brackets else, fileline:137
[86] single delay with negated var brackets else, fileline:134
[88] triggered e9
[88] single delay with negated var brackets stmt, fileline:135
[88] single delay with negated var brackets stmt, fileline:132
[90] triggered e10
[92] triggered e10
[94] triggered e10
[94] single delay with negated var brackets else, fileline:141
[94] single delay with negated var brackets else, fileline:138
[96] triggered e10
[98] triggered e10
[98] single delay with negated var brackets else, fileline:141
[98] single delay with negated var brackets else, fileline:138
[100] triggered e11
[102] triggered e11
[102] single delay with nested not stmt, fileline:144
[102] single delay with nested not stmt, fileline:141
[104] triggered e11
[104] single delay with nested not else, fileline:145
[104] single delay with nested not else, fileline:142
[106] triggered e11
[106] single delay with nested not stmt, fileline:144
[106] single delay with nested not stmt, fileline:141
[108] triggered e11
[108] single delay with nested not else, fileline:145
[108] single delay with nested not else, fileline:142
[110] triggered e12
[112] triggered e12
[114] triggered e12
[114] stmt, fileline: 148
[114] stmt, fileline: 145
[116] triggered e12
[116] else, fileline: 150
[116] else, fileline: 147
[118] triggered e12
[118] stmt, fileline: 148
[118] stmt, fileline: 145
[120] triggered e13
[122] triggered e13
[122] property, fileline:161
[122] property, fileline:158
[124] triggered e13
[124] property, fileline:160
[124] property, fileline:157
[126] triggered e13
[126] property, fileline:161
[126] property, fileline:158
[128] triggered e13
[128] property, fileline:160
[128] property, fileline:157
[130] triggered e14
[132] triggered e14
[132] else, fileline: 166
[132] else, fileline: 163
[134] triggered e14
[134] stmt, fileline: 164
[134] stmt, fileline: 161
[136] triggered e14
[136] else, fileline: 166
[136] else, fileline: 163
[138] triggered e14
[138] else, fileline: 166
[138] else, fileline: 163
[140] triggered e15
[140] else, fileline: 171
[140] else, fileline: 168
[142] triggered e15
[144] triggered e15
[144] else, fileline: 171
[144] else, fileline: 171
[144] else, fileline: 168
[144] else, fileline: 168
[146] triggered e15
[148] triggered e15
[148] else, fileline: 171
[148] else, fileline: 168
*-* All Finished *-*
test_regress/t/t_property_sexpr.v
+2 -5
View File
@@ -7,13 +7,10 @@
`define STRINGIFY(x) `"x`"
`define TRIGGER(e) ->e; $display("[%0t] triggered %s", $time, `STRINGIFY(e))
module t ( /*AUTOARG*/
// Inputs
clk
module t (
input clk
);
input clk;
bit [1:0] val = 0;
event e1;
event e2;
test_regress/t/t_property_sexpr2_bad.out
+6 -6
View File
@@ -1,15 +1,15 @@
%Error: t/t_property_sexpr2_bad.v:20:35: Delay value is not a non-negative elaboration-time constant (IEEE 1800-2023 16.7)
%Error: t/t_property_sexpr2_bad.v:18:35: Delay value is not a non-negative elaboration-time constant (IEEE 1800-2023 16.7)
: ... note: In instance 't'
20 | assert property (@(posedge clk) ##clk val);
18 | assert property (@(posedge clk) ##clk val);
| ^~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_property_sexpr2_bad.v:21:35: Delay value is not a non-negative elaboration-time constant (IEEE 1800-2023 16.7)
%Error: t/t_property_sexpr2_bad.v:19:35: Delay value is not a non-negative elaboration-time constant (IEEE 1800-2023 16.7)
: ... note: In instance 't'
21 | assert property (@(posedge clk) ##(1+clk) val);
19 | assert property (@(posedge clk) ##(1+clk) val);
| ^~
%Error-UNSUPPORTED: t/t_property_sexpr2_bad.v:23:35: Unsupported: SVA cycle delay exceeds implementation limit of 65536 (--max-num-width)
%Error-UNSUPPORTED: t/t_property_sexpr2_bad.v:21:35: Unsupported: SVA cycle delay exceeds implementation limit of 65536 (--max-num-width)
: ... note: In instance 't'
23 | assert property (@(posedge clk) ##32'h80000000 val);
21 | assert property (@(posedge clk) ##32'h80000000 val);
| ^~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to
test_regress/t/t_property_sexpr2_bad.v
+2 -4
View File
@@ -4,12 +4,10 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
module t ( /*AUTOARG*/
// Inputs
clk
module t (
input clk
);
input clk;
bit val;
always @(posedge clk) begin
test_regress/t/t_property_sexpr_bad.out
+2 -2
View File
@@ -1,6 +1,6 @@
%Error: t/t_property_sexpr_bad.v:20:39: Unexpected 'not' in sequence expression context
%Error: t/t_property_sexpr_bad.v:18:39: Unexpected 'not' in sequence expression context
: ... note: In instance 't'
20 | assert property (@(posedge clk) ##1 not val);
18 | assert property (@(posedge clk) ##1 not val);
| ^~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to
test_regress/t/t_property_sexpr_bad.v
+2 -4
View File
@@ -4,12 +4,10 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
module t ( /*AUTOARG*/
// Inputs
clk
module t (
input clk
);
input clk;
bit val;
always @(posedge clk) begin
test_regress/t/t_property_sexpr_cov.dat.out
+3 -3
View File
@@ -1,5 +1,5 @@
# SystemC::Coverage-3
C 'ft/t_property_sexpr_cov.vl41n3tuserpagev_user/tocoverhtop.t' 2
C 'ft/t_property_sexpr_cov.vl44n3tuserpagev_user/tocoverhtop.t' 2
C 'ft/t_property_sexpr_cov.vl47n3tuserpagev_user/tocoverhtop.t' 2
C 'ft/t_property_sexpr_cov.vl50n3tuserpagev_user/tocoverhtop.t' 3
C 'ft/t_property_sexpr_cov.vl53n3tuserpagev_user/tocoverhtop.t' 25
C 'ft/t_property_sexpr_cov.vl47n3tuserpagev_user/tocoverhtop.t' 3
C 'ft/t_property_sexpr_cov.vl50n3tuserpagev_user/tocoverhtop.t' 25
test_regress/t/t_property_sexpr_cov.out
+30 -30
View File
@@ -1,33 +1,33 @@
[4] cover property, fileline:42
[4] cover property, fileline:45
[4] cover property, fileline:48
[7] concurrent cover, fileline:54
[7] concurrent cover, fileline:51
[8] cover property, fileline:42
[8] cover property, fileline:45
[8] cover property, fileline:48
[12] not cover property, fileline:51
[15] concurrent cover, fileline:54
[18] not cover property, fileline:51
[20] not cover property, fileline:51
[23] concurrent cover, fileline:54
[31] concurrent cover, fileline:54
[39] concurrent cover, fileline:54
[47] concurrent cover, fileline:54
[55] concurrent cover, fileline:54
[63] concurrent cover, fileline:54
[71] concurrent cover, fileline:54
[79] concurrent cover, fileline:54
[87] concurrent cover, fileline:54
[95] concurrent cover, fileline:54
[103] concurrent cover, fileline:54
[111] concurrent cover, fileline:54
[119] concurrent cover, fileline:54
[127] concurrent cover, fileline:54
[135] concurrent cover, fileline:54
[143] concurrent cover, fileline:54
[151] concurrent cover, fileline:54
[159] concurrent cover, fileline:54
[167] concurrent cover, fileline:54
[175] concurrent cover, fileline:54
[183] concurrent cover, fileline:54
[191] concurrent cover, fileline:54
[199] concurrent cover, fileline:54
[12] not cover property, fileline:48
[15] concurrent cover, fileline:51
[18] not cover property, fileline:48
[20] not cover property, fileline:48
[23] concurrent cover, fileline:51
[31] concurrent cover, fileline:51
[39] concurrent cover, fileline:51
[47] concurrent cover, fileline:51
[55] concurrent cover, fileline:51
[63] concurrent cover, fileline:51
[71] concurrent cover, fileline:51
[79] concurrent cover, fileline:51
[87] concurrent cover, fileline:51
[95] concurrent cover, fileline:51
[103] concurrent cover, fileline:51
[111] concurrent cover, fileline:51
[119] concurrent cover, fileline:51
[127] concurrent cover, fileline:51
[135] concurrent cover, fileline:51
[143] concurrent cover, fileline:51
[151] concurrent cover, fileline:51
[159] concurrent cover, fileline:51
[167] concurrent cover, fileline:51
[175] concurrent cover, fileline:51
[183] concurrent cover, fileline:51
[191] concurrent cover, fileline:51
[199] concurrent cover, fileline:51
*-* All Finished *-*
test_regress/t/t_property_sexpr_cov.v
+2 -5
View File
@@ -4,13 +4,10 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
module t ( /*AUTOARG*/
// Inputs
clk
module t (
input clk
);
input clk;
bit [3:0] val = 0;
event e1;
event e2;
test_regress/t/t_property_sexpr_parse_unsup.out
+21 -21
View File
@@ -1,44 +1,44 @@
%Warning-WIDTHTRUNC: t/t_property_sexpr_unsup.v:76:14: Logical operator IMPLICATION expects 1 bit on the RHS, but RHS's CMETHODHARD 'at' generates 8 bits.
%Warning-WIDTHTRUNC: t/t_property_sexpr_unsup.v:74:14: Logical operator IMPLICATION expects 1 bit on the RHS, but RHS's CMETHODHARD 'at' generates 8 bits.
: ... note: In instance 't.ieee'
76 | $rose(a) |-> q[0];
74 | $rose(a) |-> q[0];
| ^~~
... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest
... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.
%Warning-WIDTHTRUNC: t/t_property_sexpr_unsup.v:81:29: Logical operator SEXPR expects 1 bit on the exprp, but exprp's CMETHODHARD 'at' generates 8 bits.
%Warning-WIDTHTRUNC: t/t_property_sexpr_unsup.v:79:29: Logical operator SEXPR expects 1 bit on the exprp, but exprp's CMETHODHARD 'at' generates 8 bits.
: ... note: In instance 't.ieee'
81 | ($rose(a), l_b = b) |-> ##[3:10] q[l_b];
79 | ($rose(a), l_b = b) |-> ##[3:10] q[l_b];
| ^~
%Warning-WIDTHTRUNC: t/t_property_sexpr_unsup.v:102:31: Logical operator SEXPR expects 1 bit on the exprp, but exprp's VARREF 'b' generates 32 bits.
%Warning-WIDTHTRUNC: t/t_property_sexpr_unsup.v:100:31: Logical operator SEXPR expects 1 bit on the exprp, but exprp's VARREF 'b' generates 32 bits.
: ... note: In instance 't.ieee'
102 | assert property (@clk not a ##1 b);
100 | assert property (@clk not a ##1 b);
| ^~
%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:47:39: Unsupported: 'until' in complex property expression
%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:45:39: Unsupported: 'until' in complex property expression
: ... note: In instance 't'
47 | assert property (@(posedge clk) val until val until val) $display("[%0t] nested until, fileline:%d", $time, 47);
45 | assert property (@(posedge clk) val until val until val) $display("[%0t] nested until, fileline:%d", $time, 45);
| ^~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:49:39: Unsupported: 'until' in complex property expression
%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:47:39: Unsupported: 'until' in complex property expression
: ... note: In instance 't'
49 | assert property (@(posedge clk) val until (val ##1 val)) $display("[%0t] sequence in until, fileline:%d", $time, 49);
47 | assert property (@(posedge clk) val until (val ##1 val)) $display("[%0t] sequence in until, fileline:%d", $time, 47);
| ^~~~~
%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:49:39: Unsupported: 's_until' in complex property expression
: ... note: In instance 't'
49 | assert property (@(posedge clk) val s_until val s_until val) $display("[%0t] nested s_until, fileline:%d", $time, 49);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:51:39: Unsupported: 's_until' in complex property expression
: ... note: In instance 't'
51 | assert property (@(posedge clk) val s_until val s_until val) $display("[%0t] nested s_until, fileline:%d", $time, 51);
51 | assert property (@(posedge clk) val s_until (val ##1 val)) $display("[%0t] sequence in until_with, fileline:%d", $time, 51);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:53:39: Unsupported: 's_until' in complex property expression
%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:53:39: Unsupported: 's_until_with' in complex property expression
: ... note: In instance 't'
53 | assert property (@(posedge clk) val s_until (val ##1 val)) $display("[%0t] sequence in until_with, fileline:%d", $time, 53);
| ^~~~~~~
53 | assert property (@(posedge clk) val s_until_with val s_until_with val) $display("[%0t] nested s_until_with, fileline:%d", $time, 53);
| ^~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:55:39: Unsupported: 's_until_with' in complex property expression
: ... note: In instance 't'
55 | assert property (@(posedge clk) val s_until_with val s_until_with val) $display("[%0t] nested s_until_with, fileline:%d", $time, 55);
55 | assert property (@(posedge clk) val s_until_with (val ##1 val)) $display("[%0t] sequence in until_with, fileline:%d", $time, 55);
| ^~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:57:39: Unsupported: 's_until_with' in complex property expression
%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:57:40: Unsupported: 'until' in complex property expression
: ... note: In instance 't'
57 | assert property (@(posedge clk) val s_until_with (val ##1 val)) $display("[%0t] sequence in until_with, fileline:%d", $time, 57);
| ^~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:59:40: Unsupported: 'until' in complex property expression
: ... note: In instance 't'
59 | assert property (@(posedge clk) (val until val) or val) $display("[%0t] until inside or, fileline:%d", $time, 59);
57 | assert property (@(posedge clk) (val until val) or val) $display("[%0t] until inside or, fileline:%d", $time, 57);
| ^~~~~
%Error: Exiting due to
test_regress/t/t_property_sexpr_unsup.out
+15 -15
View File
@@ -1,30 +1,30 @@
%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:47:39: Unsupported: 'until' in complex property expression
%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:45:39: Unsupported: 'until' in complex property expression
: ... note: In instance 't'
47 | assert property (@(posedge clk) val until val until val) $display("[%0t] nested until, fileline:%d", $time, 47);
45 | assert property (@(posedge clk) val until val until val) $display("[%0t] nested until, fileline:%d", $time, 45);
| ^~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:49:39: Unsupported: 'until' in complex property expression
%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:47:39: Unsupported: 'until' in complex property expression
: ... note: In instance 't'
49 | assert property (@(posedge clk) val until (val ##1 val)) $display("[%0t] sequence in until, fileline:%d", $time, 49);
47 | assert property (@(posedge clk) val until (val ##1 val)) $display("[%0t] sequence in until, fileline:%d", $time, 47);
| ^~~~~
%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:49:39: Unsupported: 's_until' in complex property expression
: ... note: In instance 't'
49 | assert property (@(posedge clk) val s_until val s_until val) $display("[%0t] nested s_until, fileline:%d", $time, 49);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:51:39: Unsupported: 's_until' in complex property expression
: ... note: In instance 't'
51 | assert property (@(posedge clk) val s_until val s_until val) $display("[%0t] nested s_until, fileline:%d", $time, 51);
51 | assert property (@(posedge clk) val s_until (val ##1 val)) $display("[%0t] sequence in until_with, fileline:%d", $time, 51);
| ^~~~~~~
%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:53:39: Unsupported: 's_until' in complex property expression
%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:53:39: Unsupported: 's_until_with' in complex property expression
: ... note: In instance 't'
53 | assert property (@(posedge clk) val s_until (val ##1 val)) $display("[%0t] sequence in until_with, fileline:%d", $time, 53);
| ^~~~~~~
53 | assert property (@(posedge clk) val s_until_with val s_until_with val) $display("[%0t] nested s_until_with, fileline:%d", $time, 53);
| ^~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:55:39: Unsupported: 's_until_with' in complex property expression
: ... note: In instance 't'
55 | assert property (@(posedge clk) val s_until_with val s_until_with val) $display("[%0t] nested s_until_with, fileline:%d", $time, 55);
55 | assert property (@(posedge clk) val s_until_with (val ##1 val)) $display("[%0t] sequence in until_with, fileline:%d", $time, 55);
| ^~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:57:39: Unsupported: 's_until_with' in complex property expression
%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:57:40: Unsupported: 'until' in complex property expression
: ... note: In instance 't'
57 | assert property (@(posedge clk) val s_until_with (val ##1 val)) $display("[%0t] sequence in until_with, fileline:%d", $time, 57);
| ^~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:59:40: Unsupported: 'until' in complex property expression
: ... note: In instance 't'
59 | assert property (@(posedge clk) (val until val) or val) $display("[%0t] until inside or, fileline:%d", $time, 59);
57 | assert property (@(posedge clk) (val until val) or val) $display("[%0t] until inside or, fileline:%d", $time, 57);
| ^~~~~
%Error: Exiting due to
test_regress/t/t_property_sexpr_unsup.v
+2 -4
View File
@@ -4,12 +4,10 @@
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
module t ( /*AUTOARG*/
// Inputs
clk
module t (
input clk
);
input clk;
integer cyc = 1;
bit val = 0;
test_regress/t/t_property_unsup.out
+12 -12
View File
@@ -1,20 +1,20 @@
%Error-UNSUPPORTED: t/t_property_unsup.v:65:41: Unsupported: eventually[] (in property expression)
65 | assert property (counter == 1 implies eventually[1: 2] counter == 3);
%Error-UNSUPPORTED: t/t_property_unsup.v:62:41: Unsupported: eventually[] (in property expression)
62 | assert property (counter == 1 implies eventually[1: 2] counter == 3);
| ^~~~~~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_property_unsup.v:80:20: Unsupported: eventually[] (in property expression)
80 | assert property (eventually[0: 2] counter == 3);
%Error-UNSUPPORTED: t/t_property_unsup.v:77:20: Unsupported: eventually[] (in property expression)
77 | assert property (eventually[0: 2] counter == 3);
| ^~~~~~~~~~
%Error-UNSUPPORTED: t/t_property_unsup.v:90:21: Unsupported: eventually[] (in property expression)
90 | assert property ((eventually[0: 1] a) implies (eventually[0: 1] a));
%Error-UNSUPPORTED: t/t_property_unsup.v:87:21: Unsupported: eventually[] (in property expression)
87 | assert property ((eventually[0: 1] a) implies (eventually[0: 1] a));
| ^~~~~~~~~~
%Error-UNSUPPORTED: t/t_property_unsup.v:90:50: Unsupported: eventually[] (in property expression)
90 | assert property ((eventually[0: 1] a) implies (eventually[0: 1] a));
%Error-UNSUPPORTED: t/t_property_unsup.v:87:50: Unsupported: eventually[] (in property expression)
87 | assert property ((eventually[0: 1] a) implies (eventually[0: 1] a));
| ^~~~~~~~~~
%Error-UNSUPPORTED: t/t_property_unsup.v:112:21: Unsupported: eventually[] (in property expression)
112 | assert property ((eventually[0: 1] a) iff (eventually[0: 1] a));
%Error-UNSUPPORTED: t/t_property_unsup.v:109:21: Unsupported: eventually[] (in property expression)
109 | assert property ((eventually[0: 1] a) iff (eventually[0: 1] a));
| ^~~~~~~~~~
%Error-UNSUPPORTED: t/t_property_unsup.v:112:46: Unsupported: eventually[] (in property expression)
112 | assert property ((eventually[0: 1] a) iff (eventually[0: 1] a));
%Error-UNSUPPORTED: t/t_property_unsup.v:109:46: Unsupported: eventually[] (in property expression)
109 | assert property ((eventually[0: 1] a) iff (eventually[0: 1] a));
| ^~~~~~~~~~
%Error: Exiting due to
test_regress/t/t_property_unsup.v
+3 -6
View File
@@ -36,13 +36,10 @@
// - homepage : https://www.cprover.org/ebmc/
// - source repository : https://github.com/diffblue/hw-cbmc
module t ( /*AUTOARG*/
// Inputs
clk,
reset
module t (
input clk,
input reset
);
input clk;
input reset;
eventually1 eventually1 (.*);
eventually2 eventually2 (.*);
sva_implies2 sva_implies2 (.*);
test_regress/t/t_property_until.v
+5 -7
View File
@@ -4,17 +4,15 @@
// SPDX-FileCopyrightText: 2026 Antmicro
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkh(gotv,
expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%p exp='h%p\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%p exp='h%p\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
// verilog_format: on
module t ( /*AUTOARG*/
// Inputs
clk
module t (
input clk
);
input clk;
typedef struct {
int fails;
int passs;
test_regress/t/t_randomize_solver_mt.v
+2 -4
View File
@@ -63,11 +63,9 @@ module sub_hi (
end
endmodule
module t ( /*AUTOARG*/
// Inputs
clk
module t (
input clk
);
input clk;
int nlo, nhi;
int cyc = 0;
sub_lo u_lo (
test_regress/t/t_randomize_with_dyn_arr.v
+8 -2
View File
@@ -31,7 +31,10 @@ class Cls;
arr[0] = 111112300;
arr[1] = 123000000;
repeat (40) begin
ok = a.randomize() with {x >= 0; x <= arr[1];};
ok = a.randomize() with {
x >= 0;
x <= arr[1];
};
`checkd(ok, 1);
`check_range(a.x, 0, 123000000);
`checkd_ne(a.x, prev);
@@ -39,7 +42,10 @@ class Cls;
end
prev = -1;
repeat (40) begin
ok = a.randomize() with {x >= 0; x <= foo();};
ok = a.randomize() with {
x >= 0;
x <= foo();
};
`checkd(ok, 1);
`check_range(a.x, 0, 111112300);
`checkd_ne(a.x, prev);
test_regress/t/t_randomize_with_dyn_arr_unsup.out
+3 -3
View File
@@ -1,5 +1,5 @@
%Error-UNSUPPORTED: t/t_randomize_with_dyn_arr_unsup.v:28:59: Unsupported: Randomization of an index to a non-random variable
28 | if (c.randomize() with {solve foo before x; x == arr[bit'(foo)]; foo <= 1;} != 1) $stop;
| ^
%Error-UNSUPPORTED: t/t_randomize_with_dyn_arr_unsup.v:30:21: Unsupported: Randomization of an index to a non-random variable
30 | x == arr[bit'(foo)];
| ^
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to
test_regress/t/t_randomize_with_dyn_arr_unsup.v
+6 -1
View File
@@ -25,7 +25,12 @@ class Cls4;
arr[0] = 123;
arr[1] = 124;
repeat (40) begin
if (c.randomize() with {solve foo before x; x == arr[bit'(foo)]; foo <= 1;} != 1) $stop;
if (c.randomize() with {
solve foo before x;
x == arr[bit'(foo)];
foo <= 1;
} != 1)
$stop;
`checkd(c.x, arr[bit'(c.foo)]);
end
endtask
test_regress/t/t_randomize_with_item_name.v
+1 -1
View File
@@ -109,7 +109,7 @@ class Seq;
endfunction
endclass
module t ( /*AUTOARG*/);
module t;
initial begin
automatic Seq s = new();
s.check_member_handle();
test_regress/t/t_randomize_with_item_name_types.v
+1 -1
View File
@@ -63,7 +63,7 @@ class Seq;
endfunction
endclass
module t ( /*AUTOARG*/);
module t;
// std::randomize() with reaches the 'with' clause through a different call
// site than a class randomize(), and must not shadow 'item' either.
function automatic void check_std_randomize();
test_regress/t/t_scheduling_0.v
+6 -10
View File
@@ -14,34 +14,30 @@
`define IMPURE_ONE |($random | $random);
`endif
module top(
clk
module top (
clk
);
input clk;
// Generate half speed 'clk_half', via non-blocking assignment
reg clk_half = 0;
always @(posedge clk)
clk_half <= ~clk_half;
always @(posedge clk) clk_half <= ~clk_half;
// 'clk_half_also' is the same as 'clk_half'.
wire clk_half_also = clk_half & `IMPURE_ONE;
// Random data updated by full speed clock
reg q = 0;
always @(posedge clk)
q <= ($random % 2 == 1) ? 1'b1 : 1'b0;
always @(posedge clk) q <= ($random % 2 == 1) ? 1'b1 : 1'b0;
// Flop `q` via `clk_half`
reg a = 0;
always @(posedge clk_half)
a <= q;
always @(posedge clk_half) a <= q;
// Flop `q` via `clk_half_also`
reg b = 0;
always @(posedge clk_half_also)
b <= q;
always @(posedge clk_half_also) b <= q;
// Cycle count
reg [31:0] cyc = 0;
test_regress/t/t_scope_cxx_equal_to.v
+31 -28
View File
@@ -16,9 +16,9 @@
module t;
wire [1:0] out;
reg in;
reg rst;
reg clk;
reg in;
reg rst;
reg clk;
initial begin
clk = 0;
@@ -37,38 +37,41 @@ module t;
#10 clk <= !clk;
end
Test test(.out(out), .in(in),
.clk(clk), .rst(rst));
Test test (
.out(out),
.in(in),
.clk(clk),
.rst(rst)
);
endmodule
module Test(/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in, rst
);
module Test ( /*AUTOARG*/
// Outputs
out,
// Inputs
clk,
in,
rst
);
input clk;
input in;
input rst;
output wire [1:0] out;
input clk;
input in;
input rst;
output wire [1:0] out;
reg [1:0] s;
reg sin;
reg [1:0] s;
reg sin;
assign out = s;
assign out = s;
always @(posedge clk)
begin
s[1] <= in;
s[0] <= sin;
end
always @(posedge clk) begin
s[1] <= in;
s[0] <= sin;
end
always @(negedge clk, posedge rst)
if (rst)
sin <= 1'b0;
else
sin <= in;
always @(negedge clk, posedge rst)
if (rst) sin <= 1'b0;
else sin <= in;
endmodule
test_regress/t/t_slice_struct_array_modport.v
+7 -5
View File
@@ -4,15 +4,17 @@
// SPDX-FileCopyrightText: 2015 Varun Koyyalagunta
// SPDX-License-Identifier: CC0-1.0
typedef struct packed {
logic p;
} s_data;
typedef struct packed {logic p;} s_data;
module m1 (output s_data data[1:0]);
module m1 (
output s_data data[1:0]
);
assign data[0].p = 0;
assign data[1].p = 0;
endmodule
module top (output s_data data[2:0]);
module top (
output s_data data[2:0]
);
m1 m1_inst (.data(data[1:0]));
endmodule
test_regress/t/t_split_var_auto.v
+48 -19
View File
@@ -21,13 +21,41 @@ module t (
logic [31:0] out3;
// Splittable
sub #(.ADDEND(1), .FORCEABLE(1'b0)) sub_0(clk, cnt, out0);
sub #(
.ADDEND(1),
.FORCEABLE(1'b0)
) sub_0 (
clk,
cnt,
out0
);
// Unsplittable due to hierarchical reference
sub #(.ADDEND(2), .FORCEABLE(1'b0)) sub_1(clk, cnt, out1);
sub #(
.ADDEND(2),
.FORCEABLE(1'b0)
) sub_1 (
clk,
cnt,
out1
);
// Unsplittable due to hiererchical reference
sub #(.ADDEND(3), .FORCEABLE(1'b0)) sub_2(clk, cnt, out2);
sub #(
.ADDEND(3),
.FORCEABLE(1'b0)
) sub_2 (
clk,
cnt,
out2
);
// Unsplittable due to forceable attribute
sub #(.ADDEND(4), .FORCEABLE(1'b1)) sub_3(clk, cnt, out3);
sub #(
.ADDEND(4),
.FORCEABLE(1'b1)
) sub_3 (
clk,
cnt,
out3
);
task print();
// This hierarchical reference should prevent automatic splitting
@@ -40,38 +68,39 @@ module t (
`checkh(out2, cnt + 32'd30);
`checkh(out3, cnt + 32'd40);
// This hierarchical reference should prevent automatic splitting
$display("sub_1.gen_else.tmp[9]: %02d", sub_1.gen_else.tmp[9]);
print();
// This hierarchical reference should prevent automatic splitting
$display("sub_1.gen_else.tmp[9]: %02d", sub_1.gen_else.tmp[9]);
print();
cnt <= cnt + 32'd1;
cnt <= cnt + 32'd1;
if (cnt == 20) begin
$write("*-* All Finished *-*\n");
$finish;
end
if (cnt == 20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub #(
parameter logic [31:0] ADDEND,
parameter logic FORCEABLE
parameter logic [31:0] ADDEND,
parameter logic FORCEABLE
) (
input wire clk,
input logic [31:0] i,
output logic [31:0] o
input wire clk,
input logic [31:0] i,
output logic [31:0] o
);
/* verilator lint_off UNOPTFLAT */
// Both branches do the same thing, difference is the 'forceable' attribute
if (FORCEABLE) begin : gen_then
wire logic [9:0][31:0] tmp /* verilator forceable */;
wire logic [9:0][31:0] tmp /* verilator forceable */;
assign tmp[0] = i;
for (genvar n = 1; n < 10; ++n) begin
assign tmp[n] = tmp[n-1] + ADDEND;
end
assign o = tmp[9] + ADDEND;
end else begin : gen_else
end
else begin : gen_else
wire logic [9:0][31:0] tmp;
assign tmp[0] = i;
for (genvar n = 1; n < 10; ++n) begin
test_regress/t/t_static_function_in_class.v
+14 -17
View File
@@ -8,39 +8,36 @@ class string_utils;
typedef string array_of_string[];
static function array_of_string split_by_dash(string s);
string parts[$];
int last_char_position = -1;
string parts[$];
int last_char_position = -1;
for (int i = 0; i < s.len(); i++) begin
if (i == s.len()-1) begin
parts.push_back(s.substr(last_char_position+1, i));
if (i == s.len() - 1) begin
parts.push_back(s.substr(last_char_position + 1, i));
end
// Can't remove this, because then the code will work
if (string'(s[i]) == "-") begin
parts.push_back(s.substr(last_char_position+1, i-1));
parts.push_back(s.substr(last_char_position + 1, i - 1));
last_char_position = i;
end
end // for (int i = 0; i < s.len(); i++)
end // for (int i = 0; i < s.len(); i++)
return parts;
endfunction // split_by_dash
endclass // string_utils
endfunction // split_by_dash
endclass // string_utils
class filter;
local static filter single_instance;
static function filter get();
if (single_instance == null)
single_instance = new();
if (single_instance == null) single_instance = new();
return single_instance;
endfunction // get
endfunction // get
local function new();
string parts[] = string_utils::split_by_dash("*");
if (parts.size() != 1)
$fatal(0, "Expected single element");
if (parts[0] != "*")
$fatal(0, "Expected element to be *");
endfunction // new
endclass // filter
if (parts.size() != 1) $fatal(0, "Expected single element");
if (parts[0] != "*") $fatal(0, "Expected element to be *");
endfunction // new
endclass // filter
module t;
const filter _filter = filter::get();
test_regress/t/t_stream_bitqueue.v
+2 -4
View File
@@ -10,9 +10,8 @@
`define checks(gotv, expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t ( /*AUTOARG*/
// Inputs
clk
module t (
input clk
);
typedef bit bit_q_t[$]; // CData (1-bit)
@@ -26,7 +25,6 @@ module t ( /*AUTOARG*/
typedef logic [63:0] qdata_logic_q_t[$]; // QData (64-bit)
typedef logic [127:0] wide_q_t[$]; // VlWide (128-bit)
input clk;
integer cyc = 0;
logic [7:0] d;
string s;
test_regress/t/t_stream_crc_example.v
+8 -9
View File
@@ -12,21 +12,20 @@
typedef bit bit_q_t[$];
module t ( /*AUTOARG*/
// Inputs
clk
module t (
input clk
);
input clk;
integer cyc = 0;
reg [63:0] crc = '0;
reg [63:0] sum = '0;
integer cyc = 0;
reg [63:0] crc = '0;
reg [63:0] sum = '0;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
wire [31:0] out; // From test of Test.v
// End of automatics
Test test (
test_regress/t/t_timing_suspendable_deep.v
+4 -3
View File
@@ -4,12 +4,13 @@
// SPDX-FileCopyrightText: 2023 Antmicro
// SPDX-License-Identifier: CC0-1.0
`timescale 1ns/1ns
`timescale 1ns / 1ns
event evt;
class Baz;
virtual task do_something(); endtask
virtual task do_something();
endtask
endclass
class Foo extends Baz;
@@ -21,7 +22,7 @@ class Bar extends Foo;
endtask
endclass
module top();
module top;
initial begin
Bar bar;
bar = new;
test_regress/t/t_timing_wait1.v
+35 -25
View File
@@ -5,9 +5,9 @@
// SPDX-License-Identifier: CC0-1.0
`ifdef TEST_VERBOSE
`define WRITE_VERBOSE(msg) $write(msg)
`define WRITE_VERBOSE(msg) $write(msg)
`else
`define WRITE_VERBOSE(msg)
`define WRITE_VERBOSE(msg)
`endif
module t;
@@ -18,45 +18,55 @@ module t;
initial begin
`WRITE_VERBOSE("start with a==0, b==0, c==0\n");
#2 a = 1; `WRITE_VERBOSE("assign 1 to a\n");
#1 a = 2; `WRITE_VERBOSE("assign 2 to a\n"); // a==2
#1 a = 0; `WRITE_VERBOSE("assign 0 to a\n");
#1 a = 2; `WRITE_VERBOSE("assign 2 to a\n"); // 1<a<3
#1 b = 2; `WRITE_VERBOSE("assign 2 to b\n");
#1 a = 1; `WRITE_VERBOSE("assign 1 to a\n"); // b>a
#1 c = 3; `WRITE_VERBOSE("assign 3 to c\n");
#1 c = 4; `WRITE_VERBOSE("assign 4 to c\n"); // a+b<c
#1 c = 4; `WRITE_VERBOSE("assign 5 to b\n"); // a<b && b>c
b = 5; `WRITE_VERBOSE("push_back b to q\n");
#2 a = 1;
`WRITE_VERBOSE("assign 1 to a\n");
#1 a = 2;
`WRITE_VERBOSE("assign 2 to a\n"); // a==2
#1 a = 0;
`WRITE_VERBOSE("assign 0 to a\n");
#1 a = 2;
`WRITE_VERBOSE("assign 2 to a\n"); // 1<a<3
#1 b = 2;
`WRITE_VERBOSE("assign 2 to b\n");
#1 a = 1;
`WRITE_VERBOSE("assign 1 to a\n"); // b>a
#1 c = 3;
`WRITE_VERBOSE("assign 3 to c\n");
#1 c = 4;
`WRITE_VERBOSE("assign 4 to c\n"); // a+b<c
#1 c = 4;
`WRITE_VERBOSE("assign 5 to b\n"); // a<b && b>c
b = 5;
`WRITE_VERBOSE("push_back b to q\n");
q.push_back(b);
end
initial begin
#1 `WRITE_VERBOSE("waiting for a==2\n");
wait(a == 2) if (a != 2) $stop;
wait (a == 2) if (a != 2) $stop;
`WRITE_VERBOSE("waiting for a<2\n");
wait(a < 2) if (a >= 2) $stop;
wait (a < 2) if (a >= 2) $stop;
`WRITE_VERBOSE("waiting for a==0\n");
wait(a == 0) if (a != 0) $stop;
wait (a == 0) if (a != 0) $stop;
`WRITE_VERBOSE("waiting for 1<a<3\n");
wait(a > 1 && a < 3) if (a <= 1 || a >= 3) $stop;
wait (a > 1 && a < 3) if (a <= 1 || a >= 3) $stop;
`WRITE_VERBOSE("waiting for b>a\n");
wait(b > a) if (b <= a) $stop;
wait (b > a) if (b <= a) $stop;
`WRITE_VERBOSE("waiting for a+b<c\n");
wait(a + b < c) if (a + b >= c) $stop;
wait (a + b < c) if (a + b >= c) $stop;
`WRITE_VERBOSE("waiting for a<b && b>c\n");
wait(a < b && b > c) if (a >= b || b <= c) $stop;
wait (a < b && b > c) if (a >= b || b <= c) $stop;
`WRITE_VERBOSE("waiting for q.size() > 0\n");
wait(q.size() > 0) if (q.size() <= 0) $stop;
wait (q.size() > 0) if (q.size() <= 0) $stop;
wait(1);
wait (1);
wait(0 < 1) $write("*-* All Finished *-*\n");
wait (0 < 1) $write("*-* All Finished *-*\n");
$finish;
end
initial wait(0) $stop; // Note this doesn't give WAITCONST
initial wait(1 == 0) $stop;
initial wait (0) $stop; // Note this doesn't give WAITCONST
initial wait (1 == 0) $stop;
initial #12 $stop; // timeout
initial #12 $stop; // timeout
endmodule
test_regress/t/t_to_string_emitted.v
+9 -17
View File
@@ -5,12 +5,8 @@
// SPDX-License-Identifier: CC0-1.0
typedef struct {
struct {
int a;
} s1;
struct {
int b;
} s2[2][3];
struct {int a;} s1;
struct {int b;} s2[2][3];
int x;
} struct_t;
@@ -26,17 +22,14 @@ class Class;
int z;
virtual iface i1;
virtual iface2 i2[1][1];
struct {
int a;
} s1;
struct {
int b;
} s2[2][3];
struct {int a;} s1;
struct {int b;} s2[2][3];
endclass
class Class2;
int x;
endclass;
endclass
;
class Base;
int base_a;
@@ -53,7 +46,8 @@ endclass
class Derived2 extends Base2;
int derived2_a;
Class2 c2;
endclass;
endclass
;
class Base3;
int base3_a;
@@ -79,9 +73,7 @@ class OuterClass;
endclass
endclass
typedef struct {
int x;
} struct2_t;
typedef struct {int x;} struct2_t;
interface iface3;
int i;
test_regress/t/t_typedef_package.v
+8 -8
View File
@@ -5,20 +5,20 @@
// SPDX-License-Identifier: CC0-1.0
package pkg1;
typedef logic [7:0] uint8_t;
typedef logic [7:0] uint8_t;
endpackage
package pkg2;
typedef enum pkg1::uint8_t {
a = 8'd1,
b = 8'd2
} opts;
typedef enum pkg1::uint8_t {
a = 8'd1,
b = 8'd2
} opts;
endpackage
module t;
initial begin
$display("%d", pkg2::a);
$write("*-* All Finished *-*\n");
$finish;
$display("%d", pkg2::a);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
test_regress/t/t_vpi_interface_ref.v
+3 -3
View File
@@ -48,7 +48,7 @@ module Bar (
);
Foo foo (
.intf_ref (intf_ref),
.intf_ref(intf_ref),
.plain_ref(plain_ref)
);
@@ -64,7 +64,7 @@ module t (
SomeIntf concrete_intf ();
Bar bar (
.intf_ref (concrete_intf),
.intf_ref(concrete_intf),
.plain_ref(concrete_intf)
);
@@ -74,7 +74,7 @@ module t (
logic run_mon_check = 1'b0;
initial begin
concrete_intf.some_intf_var = 32'h1111_2222;
concrete_intf.some_intf_var = 32'h1111_2222;
concrete_intf.other_intf_var = 32'h3333_4444;
run_mon_check = 1'b1;
test_regress/t/t_vpi_interface_ref_hier.v
+1 -1
View File
@@ -44,7 +44,7 @@ module t;
Sub sub ();
Foo foo (
.intf_ref (sub.concrete_intf),
.intf_ref(sub.concrete_intf),
.plain_ref(sub.concrete_intf)
);
test_regress/t/t_vpi_interface_ref_scopes.v
+1 -1
View File
@@ -44,7 +44,7 @@ module t;
SomeIntf concrete_intf ();
Foo foo (
.intf_ref (concrete_intf),
.intf_ref(concrete_intf),
.plain_ref(concrete_intf)
);