From 5faaa7ec58fd5ab25449f974482ffa38b9f7ebf9 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 31 Jul 2025 18:09:43 -0400
Subject: [PATCH] Commentary (#6246)

---
 docs/guide/verilating.rst | 2 --
 1 file changed, 2 deletions(-)

diff --git a/docs/guide/verilating.rst b/docs/guide/verilating.rst
index ab0d0b7d8..1126c275e 100644
--- a/docs/guide/verilating.rst
+++ b/docs/guide/verilating.rst
@@ -147,8 +147,6 @@ Hierarchy blocks have some limitations, including:
 * The hierarchy block cannot be accessed using dot (.) from the upper
   module(s) or other hierarchy blocks.
 
-* Signals in the block cannot be traced.
-
 * Modport cannot be used at the hierarchical block boundary.
 
 * The simulation speed is likely not as fast as flat Verilation, in which