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Merge branch 'verilator:master' into fix/broken-varscope-linkable

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9
CITATION.cff
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@ -1,3 +1,4 @@
---
# See https://citation-file-format.github.io/
cff-version: 1.2.0
title: Verilator
@ -14,14 +15,14 @@ authors:
family-names: Wasson
- given-names: Duane
family-names: Galbi
- given-names: Geza
family-names: Lore
- name: 'et al'
repository-code: 'https://github.com/verilator/verilator'
url: 'https://verilator.org'
abstract: >-
The Verilator package converts Verilog and SystemVerilog hardware
description language (HDL) designs into a fast C++ or SystemC model
that, after compiling, can be executed. Verilator is not a
that, after compiling, can be executed. Verilator is not only a
traditional simulator but a compiler.
license:
- LGPL-3.0-only
- Artistic-2.0
license: [LGPL-3.0-only, Artistic-2.0]

13
Changes
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@ -44,6 +44,7 @@ Verilator 5.043 devel
* Support general global constraints (#6709) (#6711). [Yilou Wang]
* Support complex std::randomize patterns (#6736) (#6737). [Yilou Wang]
* Support `rand_mode` in global constraint gathering (#6740) (#6752). [Yilou Wang]
* Support reduction or in constraints (#6840). [Pawel Kojma, Antmicro Ltd.]
* Optimize away calls to empty functions (#6626). [Geza Lore]
* Optimize redundant headers in Syms implementation files. [Geza Lore, Fractile Ltd.]
* Optimize constructor/destructor VerilatedModules (#6660). [Geza Lore, Fractile Ltd.]
@ -56,6 +57,7 @@ Verilator 5.043 devel
* Fix generate function(s) inside of generate blocks (#1011) (#6789). [em2machine]
* Fix typedef derived from type defined inside interface (#3441) (#6776). [em2machine]
* Fix extern function that returns parameterized class (#4924).
* Fix type deduction for variable parameterized classes (#6281) (#6813). [em2machine]
* Fix randomize called within func/task (#6144) (#6753). [Yilou Wang]
* Fix pre/post_randomize on extended classes (#6467). [Alex Solomatnikov]
* Fix expression short circuiting (#6483). [Todd Strader]
@ -92,7 +94,8 @@ Verilator 5.043 devel
* Fix fork scheduling semantics (#6730). [Artur Bieniek, Antmicro Ltd.]
* Fix internal fault when cross-class calling with DPI (#6735) (#6742). [Matthew Ballance]
* Fix write variable placement for global constraints (#6740) (#6750) (#6797). [Yilou Wang]
* Fix resolution of specialized typedefs (#6754) (#6808). [em2machine]
* Fix JSON dump missing output ports (#6751) (#6831). [Oleh Maksymenko]
* Fix resolution of specialized typedefs (#6754) (#6808) (#6834). [em2machine]
* Fix UNSUPPORTED on force / release with complex selects (#6755). [Ryszard Rozak, Antmicro Ltd.]
* Fix select assignment expansion (#6757). [Geza Lore]
* Fix `--lib-create` with multi-bit clocks (#6759). [Geza Lore]
@ -108,9 +111,14 @@ Verilator 5.043 devel
* Fix `disable iff` in simple properties (#6783). [Ryszard Rozak, Antmicro Ltd.]
* Fix input sampling of clocking block signals (#6788). [Pawel Kojma, Antmicro Ltd.]
* Fix O(n*2) analysis in const-bit-op-tree (#6791). [Geza Lore]
* Fix nested struct within parameter port list (#6818) (#6824). [Luca Colagrande]
* Fix member select of variable without randmode (#6800) (#6833). [Yilou Wang]
* Fix duplicate name error with interface initial blocks (#6804) (#6805). [Thomas Dybdahl Ahle]
* Fix nested struct within parameter port list (#6818) (#6824). [Luca Colagrande]
* Fix setting thread count in VerilatedContext (#6826 partial) (#6841). [Yangyu Chen]
* Fix firing array selects of events (#6829). [Amal Araweelo Almis]
* Fix false IMPLICITSTATIC on localparam (#6835). [Geza Lore]
* Fix randcase under fork (#6843). [Amal Araweelo Almis]
* Fix JSON missing `signed` indication (#6845).
Verilator 5.042 2025-11-02
@ -551,6 +559,7 @@ Verilator 5.034 2025-02-24
* Optimize labels as final `if` block statements (#5744).
* Optimize empty function definition bodies (#5750).
* Optimize splitting trigger computation and dump (#5798). [Geza Lore]
* Optimize some DFG multiplexers (#6822). [Yangyu Chen]
* Fix error message when call task as a function (#3089). [Matthew Ballance]
* Fix force VPI public signal visibility (#5225). [Frédéric Requin]
* Fix VPI iteration over hierarchy (#5314) (#5731). [Natan Kreimer]

1
Makefile.in
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@ -541,6 +541,7 @@ YAML_FILES = \
.*.yml \
.github/*.yml \
.github/*/*.yml \
CITATION.cff \
######################################################################
# Format

2
bin/verilator
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@ -408,6 +408,8 @@ detailed descriptions of these arguments.
-I<dir> Directory to search for includes
--if-depth <value> Tune IFDEPTH warning
+incdir+<dir> Directory to search for includes
--inline-cfuncs <value> Inline CFuncs with <=value nodes (0=off)
--inline-cfuncs-product <value> Inline CFuncs if size*calls <= value
--inline-mult <value> Tune module inlining
--instr-count-dpi <value> Assumed dynamic instruction count of DPI imports
-j <jobs> Parallelism for --build-jobs/--verilate-jobs

2
docs/CONTRIBUTORS
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@ -125,6 +125,7 @@ John Wehle
Jonathan Drolet
Jonathan Schröter
Jordan McConnon
Jose Drowne
Jose Loyola
Josep Sans
Joseph Nwabueze
@ -233,6 +234,7 @@ Steven Hugg
Szymon Gizler
Sören Tempel
Teng Huang
Thomas Aldrian
Thomas Dybdahl Ahle
Tim Hutt
Tim Snyder

9
docs/gen/ex_ASSIGNEQEXPR_faulty.rst
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@ -1,9 +1,8 @@
.. comment: generated by t_lint_assigneqexpr_bad
.. code-block:: sv
:linenos:
:emphasize-lines: 3
assign d_o = // Note = not == below
(
c_o = 1 // <--- Warning: ASSIGNEQEXPR
) ? 1 : (
output logic c_o,
output logic d_o
);
assign c_o = (a_i != 0) ? 1 : 0;

8
docs/guide/connecting.rst
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@ -502,16 +502,16 @@ described above is just a wrapper which calls these two functions.
3. If using delays and :vlopt:`--timing`, there are two additional methods
the user should call:
* ``designp->eventsPending()``, which returns ``true`` if there are
any delayed events pending,
* ``designp->eventsPending()``, which returns ``true`` if there are any
delayed events pending,
* ``designp->nextTimeSlot()``, which returns the simulation time of the
next delayed event. This method can only be called if
``designp->eventsPending()`` returned ``true``.
Call ``eventsPending()`` to check if you should continue with the
simulation, and then ``nextTimeSlot()`` to move simulation time forward.
:vlopt:`--main` can be used with :vlopt:`--timing` to generate a basic example
of a timing-enabled eval loop.
:vlopt:`--main` can be used with :vlopt:`--timing` to generate a basic
example of a timing-enabled eval loop.
When ``eval()`` (or ``eval_step()``) is called Verilator looks for changes
in clock signals and evaluates related sequential always blocks, such as

7
docs/guide/contributors.rst
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@ -29,9 +29,10 @@ Alliance <https://chipsalliance.org>`_, and `Antmicro Ltd
Previous major corporate sponsors of Verilator, by providing significant
contributions of time or funds include: Antmicro Ltd., Atmel Corporation,
Compaq Corporation, Digital Equipment Corporation, Embecosm Ltd., Fractile
Ltd., Hicamp Systems, Intel Corporation, Marvell Inc., Mindspeed Technologies
Inc., MicroTune Inc., picoChip Designs Ltd., Sun Microsystems Inc., Nauticus
Networks Inc., SiCortex Inc, Shunyao CAD, and Western Digital Inc.
Ltd., Hicamp Systems, Intel Corporation, Marvell Inc., Mindspeed
Technologies Inc., MicroTune Inc., picoChip Designs Ltd., Sun Microsystems
Inc., Nauticus Networks Inc., SiCortex Inc, Shunyao CAD, and Western
Digital Inc.
The contributors of major functionality are: Jeremy Bennett, Krzysztof
Bieganski, Byron Bradley, Lane Brooks, John Coiner, Duane Galbi, Arkadiusz

3
docs/guide/example_binary.rst
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@ -39,8 +39,7 @@ Breaking this command down:
#. :vlopt:`-j` `0` to Verilate using use as many CPU threads as the machine
has.
#. :vlopt:`-Wall` so Verilator has stronger lint warnings
enabled.
#. :vlopt:`-Wall` so Verilator has stronger lint warnings enabled.
#. An finally, :command:`our.v`, which is our SystemVerilog design file.

3
docs/guide/example_cc.rst
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@ -60,8 +60,7 @@ Breaking this command down:
#. :vlopt:`-j 0 <-j>` to Verilate using use as many CPU threads as the
machine has.
#. :vlopt:`-Wall` so Verilator has stronger lint warnings
enabled.
#. :vlopt:`-Wall` so Verilator has stronger lint warnings enabled.
#. And finally, :command:`our.v` which is our SystemVerilog design file.

27
docs/guide/exe_verilator.rst
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@ -867,6 +867,29 @@ Summary:
compatibility and is not recommended usage as this is not supported by
some third-party tools.
.. option:: --inline-cfuncs <value>
Inline small CFunc calls directly into their callers when the function
has at most <value> nodes. This reduces function call overhead when
:vlopt:`--output-split-cfuncs` places functions in separate compilation
units that the C++ compiler cannot inline.
Set to 0 to disable this optimization. The default is 20.
This optimization is automatically disabled when :vlopt:`--prof-cfuncs`
or :vlopt:`--trace` is used.
.. option:: --inline-cfuncs-product <value>
Tune the inlining of CFunc calls for larger functions. When a function
is too large to always inline (exceeds :vlopt:`--inline-cfuncs` threshold),
it may still be inlined if the function size multiplied by the number of
call sites is at most <value>.
This allows functions that are called only once or twice to be inlined
even if they exceed the small function threshold. Set to 0 to only inline
functions below the :vlopt:`--inline-cfuncs` threshold. The default is 200.
.. option:: --inline-mult <value>
Tune the inlining of modules. The default value of 2000 specifies that
@ -2495,8 +2518,8 @@ The grammar of control commands is as follows:
converted into ``begin``/``end`` blocks.
Similar to :option:`/*verilator&32;timing_on*/`,
:option:`/*verilator&32;timing_off*/` metacomments, but interpreted
independtly. If either a control file, or metacommets disable timing
:option:`/*verilator&32;timing_off*/` meta-comments, but interpreted
independently. If either a control file, or meta-comments disable timing
constructs, they will be disabled.
.. t_dist_docs_style ignore tracing_on

4
docs/guide/extensions.rst
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@ -1,9 +1,9 @@
.. Copyright 2003-2025 by Wilson Snyder.
.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
=====================
===================
Language Extensions
=====================
===================
The following additional constructs are the extensions Verilator supports
on top of standard Verilog code. Using these features outside of comments

4
docs/guide/faq.rst
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@ -403,8 +403,8 @@ How do I get faster build times?
environment variable to override this. Also see the
:vlopt:`--output-split` option and :ref: `Profiling ccache efficiency`.
* To reduce the compile time of classes that use a Verilated module (e.g., a
top CPP file) you may wish to add a
* To reduce the compile time of classes that use a Verilated module (e.g.,
a top CPP file) you may wish to add a
:option:`/*verilator&32;no_inline_module*/` metacomment to your top-level
module. This will decrease the amount of code in the model's Verilated
class, improving compile times of any instantiating top-level C++ code,

8
docs/guide/install.rst
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@ -163,10 +163,10 @@ packages (see internals.rst), and a Python virtual environment:
cpan install Pod::Perldoc
The Python virtual environment is only required for running the whole test
suite, and for additional development steps like linting and formatting. It is
not required for building Verilator itself. To install the python virtual
environment and all dependencies automatically, run the following once, after
``configure``:
suite, and for additional development steps like linting and formatting. It
is not required for building Verilator itself. To install the python
virtual environment and all dependencies automatically, run the following
once, after ``configure``:
.. code-block:: bash

4
docs/guide/languages.rst
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@ -143,8 +143,8 @@ error, except:
* delay statements - they are ignored (as they are in synthesis), though they
do issue a :option:`STMTDLY` warning,
* intra-assignment timing controls - they are ignored, though they do issue an
:option:`ASSIGNDLY` warning,
* intra-assignment timing controls - they are ignored, though they do issue
an :option:`ASSIGNDLY` warning,
* net delays - they are ignored,
* event controls at the top of the procedure,

9
docs/guide/verilating.rst
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@ -22,8 +22,8 @@ Verilator may be used in five major ways:
that may be used to feed into other user-designed tools.
* With the :vlopt:`-E` option, Verilator will preprocess the code according
to IEEE preprocessing rules and write the output to standard out. This
is useful to feed other tools and to debug how "\`define" statements are
to IEEE preprocessing rules and write the output to standard out. This is
useful to feed other tools and to debug how "\`define" statements are
expanded.
@ -80,8 +80,9 @@ Verilator first reads all files provided on the command line and
:vlopt:`-f` files, and parses all modules within. Each module is assigned
to the most recent library specified with :vlopt:`-work`, thus `-work liba
a.v -work libb b.v` will assign modules in `a.v` to `liba` and modules in
`b.v` to `libb`. In the absence of a `-work` mapping, each module is optionally
assigned to a library based on mappings provided by :vlopt:`-libmap`.
`b.v` to `libb`. In the absence of a `-work` mapping, each module is
optionally assigned to a library based on mappings provided by
:vlopt:`-libmap`.
If a module is not defined from a file on the command-line, Verilator
attempts to find a filename constructed from the module name using

8
docs/guide/warnings.rst
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@ -1,9 +1,9 @@
.. Copyright 2003-2025 by Wilson Snyder.
.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
=====================
===================
Errors and Warnings
=====================
===================
.. _disabling warnings:
@ -46,8 +46,8 @@ Warnings may be disabled in multiple ways:
lint_off -rule UNSIGNED -file "*/example.v" -lines 1
Metacomments and control file directives do not interact. If a warning is
disabled by either metacomments, or a directive in a control file, it will not
be emitted.
disabled by either metacomments, or a directive in a control file, it will
not be emitted.
Error And Warning Format
========================

25
docs/internals.rst
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@ -1,8 +1,8 @@
|Logo|
=====================
===================
Verilator Internals
=====================
===================
.. contents::
:depth: 3
@ -1771,8 +1771,8 @@ files that were read, filtered by preprocessing. This file can be fed back
into Verilator, replacing on the command line all of the previous input
files, to enable simplification of test cases. This file also contains most
command line arguments Verilator was invoked as `// verilator fargs``
metacomments, with and can be parsed by ``-f`. So to reproduce the run that
created the file, run:
metacomments, with and can be parsed by `\`-f`. So to reproduce the run
that created the file, run:
::
verilator -f <prefix>__inputs.vpp <prefix>__inputs.vpp
@ -2095,11 +2095,18 @@ To print a node:
``src/.gdbinit`` and ``src/.gdbinit.py`` define handy utilities for working
with JSON AST dumps. For example:
* ``jstash nodep`` - Perform a JSON AST dump and save it into GDB value history (e.g. ``$1``)
* ``jtree nodep`` - Perform a JSON AST dump and pretty print it using ``astsee_verilator``.
* ``jtree $1`` - Pretty print a dump that was previously saved by ``jstash``.
* ``jtree nodep -d '.file, .timeunit'`` - Perform a JSON AST dump, filter out some fields and pretty print it.
* ``jtree 0x55555613dca0`` - Pretty print using address literal (rather than actual pointer).
* ``jstash nodep`` - Perform a JSON AST dump and save it into GDB value
history (e.g. ``$1``)
* ``jtree nodep`` - Perform a JSON AST dump and pretty print it using
``astsee_verilator``.
* ``jtree $1`` - Pretty print a dump that was previously saved by
``jstash``.
* ``jtree nodep -d '.file, .timeunit'`` - Perform a JSON AST dump, filter
out some fields and pretty print it.
* ``jtree 0x55555613dca0`` - Pretty print using address literal (rather
than actual pointer).
* ``jtree $1 nodep`` - Diff ``nodep`` against an older dump.
A detailed description of ``jstash`` and ``jtree`` can be displayed using

4
docs/spelling.txt
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@ -4,6 +4,8 @@ Accellera
Affe
Aleksander
Alexandre
Almis
Amal
Ami
Amir
Anastasiadis
@ -13,6 +15,7 @@ Antmicro
Antonin
Antwerpen
Arasanipalai
Araweelo
Arjen
Arshid
Asciidoc
@ -986,6 +989,7 @@ qrqiuren
radix
randc
randcase
randmode
randsequence
randstate
raphmaster

6
examples/json_py/sub.v
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@ -5,9 +5,9 @@
// SPDX-License-Identifier: CC0-1.0
// ======================================================================
module sub
#(parameter type TYPE_t = logic)
(
module sub #(
parameter type TYPE_t = logic
) (
input TYPE_t in,
output TYPE_t out
);

30
examples/json_py/top.v
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@ -5,8 +5,7 @@
// SPDX-License-Identifier: CC0-1.0
// ======================================================================
module top
(
module top (
input clk,
input fastclk,
input reset_l,
@ -19,15 +18,24 @@ module top
input [69:0] in_wide
);
sub #(.TYPE_t(logic [1:0])) sub_small
(.in(in_small),
.out(out_small));
sub #(
.TYPE_t(logic [1:0])
) sub_small (
.in(in_small),
.out(out_small)
);
sub #(.TYPE_t(logic [39:0])) sub_quad
(.in(in_quad),
.out(out_quad));
sub #(
.TYPE_t(logic [39:0])
) sub_quad (
.in(in_quad),
.out(out_quad)
);
sub #(.TYPE_t(logic [69:0])) sub_wide
(.in(in_wide),
.out(out_wide));
sub #(
.TYPE_t(logic [69:0])
) sub_wide (
.in(in_wide),
.out(out_wide)
);
endmodule

12
examples/make_protect_lib/secret_impl.v
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@ -7,13 +7,13 @@
// This module will be used as libsecret.a or libsecret.so without
// exposing the source.
module secret_impl
(
module secret_impl (
input [31:0] a,
input [31:0] b,
output logic [31:0] x,
input clk,
input reset_l);
input reset_l
);
logic [31:0] accum_q;
logic [31:0] secret_value;
@ -27,10 +27,8 @@ module secret_impl
end
else begin
accum_q <= accum_q + a;
if (accum_q > 10)
x <= b;
else
x <= a + b + secret_value;
if (accum_q > 10) x <= b;
else x <= a + b + secret_value;
end
end

12
examples/make_protect_lib/top.v
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@ -6,7 +6,9 @@
// See also https://verilator.org/guide/latest/examples.html"
module top (input clk);
module top (
input clk
);
int cyc;
logic reset_l;
@ -14,7 +16,13 @@ module top (input clk);
logic [31:0] b;
logic [31:0] x;
verilated_secret secret (.a, .b, .x, .clk, .reset_l);
verilated_secret secret (
.a,
.b,
.x,
.clk,
.reset_l
);
always @(posedge clk) begin
$display("[%0t] cyc=%0d a=%0d b=%0d x=%0d", $time, cyc, a, b, x);

3
examples/make_tracing_c/sub.v
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@ -5,8 +5,7 @@
// SPDX-License-Identifier: CC0-1.0
// ======================================================================
module sub
(
module sub (
input clk,
input reset_l
);

3
examples/make_tracing_c/top.v
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@ -8,8 +8,7 @@
// This is intended to be a complex example of several features, please also
// see the simpler examples/make_hello_c.
module top
(
module top (
// Declare some signals so we can see how I/O works
input clk,
input reset_l,

3
examples/make_tracing_sc/sub.v
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@ -5,8 +5,7 @@
// SPDX-License-Identifier: CC0-1.0
// ======================================================================
module sub
(
module sub (
input clk,
input fastclk,
input reset_l

3
examples/make_tracing_sc/top.v
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@ -8,8 +8,7 @@
// This is intended to be a complex example of several features, please also
// see the simpler examples/make_hello_c.
module top
(
module top (
// Declare some signals so we can see how I/O works
input clk,
input fastclk,

2
src/CMakeLists.txt
View File

@ -114,6 +114,7 @@ set(HEADERS
V3Hasher.h
V3HierBlock.h
V3Inline.h
V3InlineCFuncs.h
V3Inst.h
V3InstrCount.h
V3Interface.h
@ -287,6 +288,7 @@ set(COMMON_SOURCES
V3Hasher.cpp
V3HierBlock.cpp
V3Inline.cpp
V3InlineCFuncs.cpp
V3Inst.cpp
V3InstrCount.cpp
V3Interface.cpp

1
src/Makefile_obj.in
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@ -284,6 +284,7 @@ RAW_OBJS_PCH_ASTNOMT = \
V3Gate.o \
V3HierBlock.o \
V3Inline.o \
V3InlineCFuncs.o \
V3Inst.o \
V3InstrCount.o \
V3Interface.o \

8
src/V3AstNodeOther.h
View File

@ -1203,6 +1203,7 @@ class AstModportVarRef final : public AstNode {
// A input/output/etc variable referenced under a modport
// The storage for the variable itself is inside the interface, thus this is a reference
// PARENT: AstModport
// @astgen op1 := exprp : Optional[AstNodeExpr]
//
// @astgen ptr := m_varp : Optional[AstVar] // Link to the actual Var
string m_name; // Name of the variable referenced
@ -1212,6 +1213,13 @@ public:
: ASTGEN_SUPER_ModportVarRef(fl)
, m_name{name}
, m_direction{direction} {}
AstModportVarRef(FileLine* fl, const string& name, AstNodeExpr* exprp,
VDirection::en direction)
: ASTGEN_SUPER_ModportVarRef(fl)
, m_name{name}
, m_direction{direction} {
this->exprp(exprp);
};
ASTGEN_MEMBERS_AstModportVarRef;
void dump(std::ostream& str) const override;
void dumpJson(std::ostream& str) const override;

1
src/V3AstNodes.cpp
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@ -2378,6 +2378,7 @@ void AstNodeDType::dump(std::ostream& str) const {
}
void AstNodeDType::dumpJson(std::ostream& str) const {
dumpJsonBoolFunc(str, generic);
if (isSigned() && !isDouble()) dumpJsonBool(str, "signed", 1);
dumpJsonGen(str);
}
void AstNodeDType::dumpSmall(std::ostream& str) const VL_MT_STABLE {

4
src/V3Fork.cpp
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@ -673,8 +673,8 @@ class ForkVisitor final : public VNVisitor {
if (nodep->access().isWriteOrRW() && (!nodep->isClassHandleValue() || nodep->user2())) {
nodep->v3warn(
E_LIFETIME,
"Invalid reference: Process might outlive variable `"
<< varp->name() << "`.\n"
"Invalid reference: Process might outlive variable "
<< varp->prettyNameQ() << ".\n"
<< varp->warnMore()
<< "... Suggest use it as read-only to initialize a local copy at the "
"beginning of the process, or declare it as static. It is also "

269
src/V3InlineCFuncs.cpp Normal file
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@ -0,0 +1,269 @@
// -*- mode: C++; c-file-style: "cc-mode" -*-
//*************************************************************************
// DESCRIPTION: Verilator: Inline small CFuncs into their callers
//
// Code available from: https://verilator.org
//
//*************************************************************************
//
// Copyright 2003-2025 by Wilson Snyder. This program is free software; you
// can redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
//
//*************************************************************************
// V3InlineCFuncs's Transformations:
//
// For each CCall to a small CFunc:
// - Check if function is eligible for inlining (small enough, same scope)
// - Clone local variables with unique names to avoid collisions
// - Replace CCall with cloned function body statements
//
// Two tunables control inlining:
// --inline-cfuncs <n> : Always inline if size <= n (default 20)
// --inline-cfuncs-product <n> : Also inline if size * call_count <= n (default 200)
//
//*************************************************************************
#include "V3PchAstNoMT.h" // VL_MT_DISABLED_CODE_UNIT
#include "V3InlineCFuncs.h"
#include "V3AstUserAllocator.h"
#include "V3Stats.h"
#include <map>
#include <vector>
VL_DEFINE_DEBUG_FUNCTIONS;
//######################################################################
// Helper visitor to check if a CFunc contains C statements
// Uses clearOptimizable pattern for debugging
class CFuncInlineCheckVisitor final : public VNVisitorConst {
// STATE
bool m_optimizable = true; // True if function can be inlined
string m_whyNot; // Reason why not optimizable
AstNode* m_whyNotNodep = nullptr; // Node that caused non-optimizable
// METHODS
void clearOptimizable(AstNode* nodep, const string& why) {
if (m_optimizable) {
m_optimizable = false;
m_whyNot = why;
m_whyNotNodep = nodep;
UINFO(9, "CFunc not inlineable: " << why);
if (nodep) UINFO(9, ": " << nodep);
UINFO(9, endl);
}
}
// VISITORS
void visit(AstCStmt* nodep) override { clearOptimizable(nodep, "contains AstCStmt"); }
void visit(AstCExpr* nodep) override { clearOptimizable(nodep, "contains AstCExpr"); }
void visit(AstCStmtUser* nodep) override { clearOptimizable(nodep, "contains AstCStmtUser"); }
void visit(AstCExprUser* nodep) override { clearOptimizable(nodep, "contains AstCExprUser"); }
void visit(AstNode* nodep) override { iterateChildrenConst(nodep); }
public:
// CONSTRUCTORS
explicit CFuncInlineCheckVisitor(AstCFunc* cfuncp) { iterateConst(cfuncp); }
// ACCESSORS
bool optimizable() const { return m_optimizable; }
string whyNot() const { return m_whyNot; }
AstNode* whyNotNodep() const { return m_whyNotNodep; }
};
//######################################################################
class InlineCFuncsVisitor final : public VNVisitor {
// NODE STATE
// AstCFunc::user1() -> vector of AstCCall* pointing to this function
// AstCFunc::user2() -> bool: true if checked for C statements
// AstCFunc::user3() -> bool: true if contains C statements (not inlineable)
const VNUser1InUse m_user1InUse;
const VNUser2InUse m_user2InUse;
const VNUser3InUse m_user3InUse;
AstUser1Allocator<AstCFunc, std::vector<AstCCall*>> m_callSites;
// STATE
VDouble0 m_statInlined; // Statistic tracking
const int m_threshold1; // Size threshold: always inline if size <= this
const int m_threshold2; // Product threshold: inline if size * calls <= this
AstCFunc* m_callerFuncp = nullptr; // Current caller function
// Tuples of (StmtExpr to replace, CFunc to inline from, caller func for vars)
std::vector<std::tuple<AstStmtExpr*, AstCFunc*, AstCFunc*>> m_toInline;
// METHODS
// Check if a function contains any $c() calls (user or internal)
// Results are cached in user2/user3 for efficiency
bool containsCStatements(AstCFunc* cfuncp) {
if (!cfuncp->user2()) {
// Not yet checked - run the check visitor
cfuncp->user2(true); // Mark as checked
const CFuncInlineCheckVisitor checker{cfuncp};
cfuncp->user3(!checker.optimizable()); // Store result (true = contains C stmts)
}
return cfuncp->user3();
}
// Check if a function is eligible for inlining into caller
bool isInlineable(AstCFunc* callerp, AstCFunc* cfuncp) {
// Must be in the same scope (same class) to access the same members
if (callerp->scopep() != cfuncp->scopep()) return false;
// Check for $c() calls that might use 'this'
if (containsCStatements(cfuncp)) return false;
// Check it's a void function (not a coroutine)
if (cfuncp->rtnTypeVoid() != "void") return false;
// Don't inline functions marked dontCombine (e.g. trace, entryPoint)
if (cfuncp->dontCombine()) return false;
// Don't inline entry point functions
if (cfuncp->entryPoint()) return false;
// Must have statements to inline
if (!cfuncp->stmtsp()) return false;
// Check size thresholds
const size_t funcSize = cfuncp->nodeCount();
// Always inline if small enough
if (funcSize <= static_cast<size_t>(m_threshold1)) return true;
// Also inline if size * call_count is reasonable
const size_t callCount = m_callSites(cfuncp).size();
if (callCount > 0 && funcSize * callCount <= static_cast<size_t>(m_threshold2)) {
return true;
}
return false;
}
// VISITORS
void visit(AstCCall* nodep) override {
iterateChildren(nodep);
AstCFunc* const cfuncp = nodep->funcp();
if (!cfuncp) return;
// Track call site for call counting
m_callSites(cfuncp).emplace_back(nodep);
}
void visit(AstCFunc* nodep) override {
VL_RESTORER(m_callerFuncp);
m_callerFuncp = nodep;
iterateChildren(nodep);
}
void visit(AstNodeModule* nodep) override {
// Process per module for better cache behavior
m_toInline.clear();
// Phase 1: Collect call sites within this module
iterateChildren(nodep);
// Phase 2: Determine which calls to inline
collectInlineCandidates(nodep);
// Phase 3: Perform inlining for this module
doInlining();
}
void visit(AstNode* nodep) override { iterateChildren(nodep); }
// Collect calls that should be inlined within this module
void collectInlineCandidates(AstNodeModule* modp) {
for (AstNode* stmtp = modp->stmtsp(); stmtp; stmtp = stmtp->nextp()) {
AstCFunc* const callerp = VN_CAST(stmtp, CFunc);
if (!callerp) continue;
callerp->foreach([&](AstCCall* callp) {
AstCFunc* const cfuncp = callp->funcp();
if (!cfuncp) return;
if (!isInlineable(callerp, cfuncp)) return;
// Walk up to find the containing StmtExpr
AstNode* stmtNodep = callp;
while (stmtNodep && !VN_IS(stmtNodep, StmtExpr) && !VN_IS(stmtNodep, CFunc)) {
stmtNodep = stmtNodep->backp();
}
AstStmtExpr* const stmtExprp = VN_CAST(stmtNodep, StmtExpr);
if (!stmtExprp) return;
m_toInline.emplace_back(stmtExprp, cfuncp, callerp);
});
}
}
// Perform the actual inlining after iteration is complete
void doInlining() {
for (const auto& tuple : m_toInline) {
AstStmtExpr* const stmtExprp = std::get<0>(tuple);
AstCFunc* const cfuncp = std::get<1>(tuple);
AstCFunc* const callerp = std::get<2>(tuple);
UINFO(6, "Inlining CFunc " << cfuncp->name() << " into " << callerp->name() << endl);
++m_statInlined;
// Clone local variables with unique names to avoid collisions
std::map<AstVar*, AstVar*> varMap;
for (AstVar* varp = cfuncp->varsp(); varp; varp = VN_AS(varp->nextp(), Var)) {
const string newName = "__Vinline_" + cfuncp->name() + "_" + varp->name();
AstVar* const newVarp = varp->cloneTree(false);
newVarp->name(newName);
callerp->addVarsp(newVarp);
varMap[varp] = newVarp;
}
// Clone the function body
AstNode* const bodyp = cfuncp->stmtsp()->cloneTree(true);
// Retarget variable references to the cloned variables
// Must iterate all sibling statements, not just the first
if (!varMap.empty()) {
for (AstNode* stmtp = bodyp; stmtp; stmtp = stmtp->nextp()) {
stmtp->foreach([&](AstVarRef* refp) {
auto it = varMap.find(refp->varp());
if (it != varMap.end()) refp->varp(it->second);
});
}
}
// Replace the statement with the inlined body
stmtExprp->addNextHere(bodyp);
VL_DO_DANGLING(stmtExprp->unlinkFrBack()->deleteTree(), stmtExprp);
}
}
public:
// CONSTRUCTORS
explicit InlineCFuncsVisitor(AstNetlist* nodep)
: m_threshold1{v3Global.opt.inlineCFuncs()}
, m_threshold2{v3Global.opt.inlineCFuncsProduct()} {
// Don't inline when profiling or tracing
if (v3Global.opt.profCFuncs() || v3Global.opt.trace()) return;
// Process modules one at a time for better cache behavior
iterateAndNextNull(nodep->modulesp());
}
~InlineCFuncsVisitor() override {
V3Stats::addStat("Optimizations, Inlined CFuncs", m_statInlined);
}
};
//######################################################################
// InlineCFuncs class functions
void V3InlineCFuncs::inlineAll(AstNetlist* nodep) {
UINFO(2, __FUNCTION__ << ":");
{ InlineCFuncsVisitor{nodep}; } // Destruct before checking
V3Global::dumpCheckGlobalTree("inlinecfuncs", 0, dumpTreeEitherLevel() >= 6);
}

30
src/V3InlineCFuncs.h Normal file
View File

@ -0,0 +1,30 @@
// -*- mode: C++; c-file-style: "cc-mode" -*-
//*************************************************************************
// DESCRIPTION: Verilator: Inline small CFuncs into their callers
//
// Code available from: https://verilator.org
//
//*************************************************************************
//
// Copyright 2003-2025 by Wilson Snyder. This program is free software; you
// can redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
//
//*************************************************************************
#ifndef VERILATOR_V3INLINECFUNCS_H_
#define VERILATOR_V3INLINECFUNCS_H_
#include "config_build.h"
#include "verilatedos.h"
class AstNetlist;
class V3InlineCFuncs final {
public:
static void inlineAll(AstNetlist* nodep) VL_MT_DISABLED;
};
#endif // Guard

8
src/V3LinkDot.cpp
View File

@ -2529,7 +2529,13 @@ class LinkDotIfaceVisitor final : public VNVisitor {
void visit(AstModportVarRef* nodep) override { // IfaceVisitor::
UINFO(5, " fiv: " << nodep);
iterateChildren(nodep);
VSymEnt* const symp = m_curSymp->findIdFallback(nodep->name());
VSymEnt* symp = nullptr;
if (nodep->exprp()) {
nodep->v3warn(E_UNSUPPORTED,
"Unsupported: Modport expressions (IEEE 1800-2023 25.5.4)");
} else {
symp = m_curSymp->findIdFallback(nodep->name());
}
if (!symp) {
nodep->v3error("Modport item not found: " << nodep->prettyNameQ());
} else if (AstVar* const varp = VN_CAST(symp->nodep(), Var)) {

2
src/V3Options.cpp
View File

@ -1528,6 +1528,8 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc,
}).notForRerun();
DECL_OPTION("-if-depth", Set, &m_ifDepth);
DECL_OPTION("-ignc", OnOff, &m_ignc).undocumented();
DECL_OPTION("-inline-cfuncs", Set, &m_inlineCFuncs);
DECL_OPTION("-inline-cfuncs-product", Set, &m_inlineCFuncsProduct);
DECL_OPTION("-inline-mult", Set, &m_inlineMult);
DECL_OPTION("-instr-count-dpi", CbVal, [this, fl](int val) {
m_instrCountDpi = val;

4
src/V3Options.h
View File

@ -319,6 +319,8 @@ private:
int m_hierChild = 0; // main switch: --hierarchical-child
int m_hierThreads = 0; // main switch: --hierarchical-threads
int m_ifDepth = 0; // main switch: --if-depth
int m_inlineCFuncs = 20; // main switch: --inline-cfuncs
int m_inlineCFuncsProduct = 200; // main switch: --inline-cfuncs-product
int m_inlineMult = 2000; // main switch: --inline-mult
int m_instrCountDpi = 200; // main switch: --instr-count-dpi
bool m_jsonEditNums = true; // main switch: --no-json-edit-nums
@ -595,6 +597,8 @@ public:
int expandLimit() const { return m_expandLimit; }
int gateStmts() const { return m_gateStmts; }
int ifDepth() const { return m_ifDepth; }
int inlineCFuncs() const { return m_inlineCFuncs; }
int inlineCFuncsProduct() const { return m_inlineCFuncsProduct; }
int inlineMult() const { return m_inlineMult; }
int instrCountDpi() const { return m_instrCountDpi; }
int localizeMaxSize() const { return m_localizeMaxSize; }

1
src/V3Randomize.cpp
View File

@ -2634,6 +2634,7 @@ class RandomizeVisitor final : public VNVisitor {
const std::string name = "__Vrandcase" + cvtToStr(m_randCaseNum++);
AstVar* const randVarp = new AstVar{fl, VVarType::BLOCKTEMP, name, sumDTypep};
randVarp->noSubst(true);
randVarp->lifetime(VLifetime::AUTOMATIC_EXPLICIT);
if (m_ftaskp) randVarp->funcLocal(true);
AstNodeExpr* sump = new AstConst{fl, AstConst::WidthedValue{}, 64, 0};
AstNodeIf* const firstIfsp

7
src/V3SenExprBuilder.h
View File

@ -126,9 +126,12 @@ private:
// Add post update if it does not exist yet
if (m_hasPostUpdate.emplace(*exprp).second) {
if (!isSupportedDType(exprp->dtypep())) {
exprp->v3warn(E_UNSUPPORTED,
exprp->v3warn(
E_UNSUPPORTED,
"Unsupported: Cannot detect changes on expression of complex type "
" (see combinational cycles reported by UNOPTFLAT)");
<< exprp->dtypep()->prettyDTypeNameQ() << "\n"
<< exprp->warnMore()
<< "... May be caused by combinational cycles reported with UNOPTFLAT");
return prevp;
}

6
src/Verilator.cpp
View File

@ -63,6 +63,7 @@
#include "V3Graph.h"
#include "V3HierBlock.h"
#include "V3Inline.h"
#include "V3InlineCFuncs.h"
#include "V3Inst.h"
#include "V3Interface.h"
#include "V3LibMap.h"
@ -565,6 +566,11 @@ static void process() {
V3Reloop::reloopAll(v3Global.rootp());
}
if (v3Global.opt.inlineCFuncs()) {
// Inline small CFuncs to reduce function call overhead
V3InlineCFuncs::inlineAll(v3Global.rootp());
}
// Fix very deep expressions
// Mark evaluation functions as member functions, if needed.
V3Depth::depthAll(v3Global.rootp());

18
src/verilog.y
View File

@ -1679,8 +1679,7 @@ modportPortsDeclList<nodep>:
// We track the type as with the V2k series of defines, then create as each ID is seen.
modportPortsDecl<nodep>:
// // IEEE: modport_simple_ports_declaration
port_direction modportSimplePortOrTFPort { $$ = new AstModportVarRef{$<fl>2, *$2, GRAMMARP->m_varIO};
GRAMMARP->m_modportImpExpActive = false;}
port_direction { GRAMMARP->m_modportImpExpActive = false; } modportSimplePortOrTFPort { $$ = $3; }
// // IEEE: modport_clocking_declaration
| yCLOCKING idAny/*clocking_identifier*/ { $$ = new AstModportClockingRef{$1, *$2}; }
// // IEEE: yIMPORT modport_tf_port
@ -1700,19 +1699,20 @@ modportPortsDecl<nodep>:
{ $$ = nullptr; BBUNSUP($<fl>1, "Unsupported: Modport export with prototype"); DEL($2); }
// Continuations of above after a comma.
// // IEEE: modport_simple_ports_declaration
| modportSimplePortOrTFPort { $$ = GRAMMARP->m_modportImpExpActive ?
| modportSimplePortOrTFPort { $$ = $1; }
;
modportSimplePortOrTFPort<nodep>:// IEEE: modport_simple_port or modport_tf_port, depending what keyword was earlier
idAny { $$ = GRAMMARP->m_modportImpExpActive ?
static_cast<AstNode*>(
new AstModportFTaskRef{
$<fl>1, *$1, GRAMMARP->m_modportImpExpLastIsExport} ) :
static_cast<AstNode*>(
new AstModportVarRef{
$<fl>1, *$1, GRAMMARP->m_varIO} ); }
;
modportSimplePortOrTFPort<strp>:// IEEE: modport_simple_port or modport_tf_port, depending what keyword was earlier
idAny { $$ = $1; }
| '.' idAny '(' ')' { $$ = $2; BBUNSUP($<fl>1, "Unsupported: Modport dotted port name"); }
| '.' idAny '(' expr ')' { $$ = $2; BBUNSUP($<fl>1, "Unsupported: Modport dotted port name"); }
| '.' idAny '(' ')' { $$ = new AstModportVarRef{$<fl>2, *$2, GRAMMARP->m_varIO};
BBUNSUP($<fl>4, "Unsupported: Modport empty expression"); }
| '.' idAny '(' expr ')' { $$ = new AstModportVarRef{$<fl>2, *$2, $4, GRAMMARP->m_varIO}; }
;
//************************************************

6
test_regress/t/t_alias_force.v
View File

@ -22,11 +22,13 @@ module t ( /*AUTOARG*/
force a = 16'h1234;
if (a != 16'h1234 || a != b) $stop;
release a;
end else if (cyc == 2) begin
end
else if (cyc == 2) begin
force b = 16'h5678;
if (a != 16'h5678 || a != b) $stop;
release b;
end else if (cyc == 3) begin
end
else if (cyc == 3) begin
$write("*-* All Finished *-*\n");
$finish;
end

5
test_regress/t/t_alw_reorder_inlined_func.v
View File

@ -4,8 +4,10 @@
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: $time=%0t got='h%x exp='h%x\n", `__FILE__,`__LINE__, $time, (got), (exp)); `stop; end while(0)
// verilog_format: on
module t;
@ -26,7 +28,8 @@ module t;
idx = ~idx;
tmp = array[~idx];
return tmp;
end else begin
end
else begin
return 0;
end
endfunction

5
test_regress/t/t_alw_sen_compare.v
View File

@ -11,7 +11,10 @@ module top;
);
endmodule
module sub(a, b);
module sub (
a,
b
);
input [127:0] a;
input [127:0] b;
always @(a or b) begin

2
test_regress/t/t_array_index_side.v
View File

@ -4,8 +4,10 @@
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
// verilog_format: on
class Cls;
int m_index;

8
test_regress/t/t_array_method_map.out
View File

@ -1,11 +1,11 @@
%Error-UNSUPPORTED: t/t_array_method_map.v:17:15: Unsupported: Array 'map' method (IEEE 1800-2023 7.12.5)
%Error-UNSUPPORTED: t/t_array_method_map.v:19:15: Unsupported: Array 'map' method (IEEE 1800-2023 7.12.5)
: ... note: In instance 't'
17 | res = a.map(el) with (el == 200);
19 | res = a.map(el) with (el == 200);
| ^~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: t/t_array_method_map.v:17:15: Unknown built-in array method 'map'
%Error: t/t_array_method_map.v:19:15: Unknown built-in array method 'map'
: ... note: In instance 't'
17 | res = a.map(el) with (el == 200);
19 | res = a.map(el) with (el == 200);
| ^~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to

4
test_regress/t/t_array_method_map.v
View File

@ -4,8 +4,10 @@
// any use, without warranty, 2024 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t;

3
test_regress/t/t_assert_elab_p.v
View File

@ -25,7 +25,8 @@ module t #(
.ID_T(ID_T),
.STAGE_IDS(STAGE_IDS)
) pipe (
.*);
.*
);
initial $finish;

5
test_regress/t/t_assert_future.v
View File

@ -10,11 +10,8 @@
// verilog_format: on
module t (
/*AUTOARG*/
// Inputs
clk
input clk
);
input clk;
global clocking @(posedge clk);
endclocking

20
test_regress/t/t_assert_future_bad.out
View File

@ -1,22 +1,22 @@
%Error: t/t_assert_future_bad.v:18:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
%Error: t/t_assert_future_bad.v:16:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
: ... note: In instance 't'
18 | else $display("Future=%0d", $future_gclk(a));
16 | else $display("Future=%0d", $future_gclk(a));
| ^~~~~~~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_assert_future_bad.v:21:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
%Error: t/t_assert_future_bad.v:19:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
: ... note: In instance 't'
21 | else $display("Future=%0d", $rising_gclk(a));
19 | else $display("Future=%0d", $rising_gclk(a));
| ^~~~~~~~~~~~
%Error: t/t_assert_future_bad.v:24:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
%Error: t/t_assert_future_bad.v:22:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
: ... note: In instance 't'
24 | else $display("Future=%0d", $falling_gclk(a));
22 | else $display("Future=%0d", $falling_gclk(a));
| ^~~~~~~~~~~~~
%Error: t/t_assert_future_bad.v:27:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
%Error: t/t_assert_future_bad.v:25:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
: ... note: In instance 't'
27 | else $display("Future=%0d", $steady_gclk(a));
25 | else $display("Future=%0d", $steady_gclk(a));
| ^~~~~~~~~~~~
%Error: t/t_assert_future_bad.v:30:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
%Error: t/t_assert_future_bad.v:28:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
: ... note: In instance 't'
30 | else $display("Future=%0d", $changing_gclk(a));
28 | else $display("Future=%0d", $changing_gclk(a));
| ^~~~~~~~~~~~~~
%Error: Exiting due to

8
test_regress/t/t_assert_future_bad.v
View File

@ -4,12 +4,10 @@
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t ( /*AUTOARG*/
// Inputs
a, clk
module t (
input a,
input clk
);
input a;
input clk;
global clocking @(posedge clk);
endclocking

4
test_regress/t/t_assert_future_unsup.out
View File

@ -1,6 +1,6 @@
%Error-UNSUPPORTED: t/t_assert_future_unsup.v:21:54: Unsupported/illegal: Future value function used with expression with operator FUNCREF 'func'
%Error-UNSUPPORTED: t/t_assert_future_unsup.v:19:54: Unsupported/illegal: Future value function used with expression with operator FUNCREF 'func'
: ... note: In instance 't'
21 | assert property (@(posedge clk) $future_gclk(a) == func(a));
19 | assert property (@(posedge clk) $future_gclk(a) == func(a));
| ^~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to

8
test_regress/t/t_assert_future_unsup.v
View File

@ -4,12 +4,10 @@
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t ( /*AUTOARG*/
// Inputs
a, clk
module t (
input a,
input clk
);
input a;
input clk;
function logic func(input logic i);
return i;

16
test_regress/t/t_assert_implication_coverage.v
View File

@ -4,13 +4,12 @@
// without warranty, 2025 by Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
module t (
input clk
);
input clk;
integer cyc; initial cyc=1;
integer cyc;
initial cyc = 1;
Test test (
/*AUTOINST*/
@ -35,7 +34,9 @@ module t (/*AUTOARG*/
endmodule
// Interface for data validation with coverage
interface data_valid_if (input logic clk);
interface data_valid_if (
input logic clk
);
logic enable_invalid_data_checks;
logic valid;
logic [7:0] data;
@ -49,8 +50,7 @@ interface data_valid_if (input logic clk);
endinterface
module Test
(
module Test (
input clk,
input integer cyc
);

14
test_regress/t/t_assert_pre.v
View File

@ -4,15 +4,14 @@
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkh(gotv,
expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
// verilog_format: on
module t ( /*AUTOARG*/
// Inputs
clk
module t (
input clk
);
input clk;
bit toggle = 0;
int inc = 0;
@ -49,7 +48,8 @@ module t ( /*AUTOARG*/
`endif
if (cyc % 3 == 0) begin
toggle <= 1;
end else begin
end
else begin
toggle <= 0;
end

32
test_regress/t/t_assign_automatic_bad.out
View File

@ -1,34 +1,34 @@
%Error: t/t_assign_automatic_bad.v:35:10: Dynamically-sized variable not allowed in continuous assignment (IEEE 1800-2023 6.21): 'bad_dyn5'
%Error: t/t_assign_automatic_bad.v:36:10: Dynamically-sized variable not allowed in continuous assignment (IEEE 1800-2023 6.21): 'bad_dyn5'
: ... note: In instance 't'
35 | assign bad_dyn5[0] = empty_dyn;
36 | assign bad_dyn5[0] = empty_dyn;
| ^~~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_assign_automatic_bad.v:37:12: Automatic lifetime variable not allowed in continuous assignment (IEEE 1800-2023 6.21): 'm_bad1'
%Error: t/t_assign_automatic_bad.v:38:12: Automatic lifetime variable not allowed in continuous assignment (IEEE 1800-2023 6.21): 'm_bad1'
: ... note: In instance 't'
37 | assign c.m_bad1 = 2;
38 | assign c.m_bad1 = 2;
| ^~~~~~
%Error: t/t_assign_automatic_bad.v:47:5: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'bad_dyn6'
%Error: t/t_assign_automatic_bad.v:48:5: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'bad_dyn6'
: ... note: In instance 't'
47 | bad_dyn6[0] <= 2;
48 | bad_dyn6[0] <= 2;
| ^~~~~~~~
%Error: t/t_assign_automatic_bad.v:49:5: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'bad_queue'
%Error: t/t_assign_automatic_bad.v:50:5: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'bad_queue'
: ... note: In instance 't'
49 | bad_queue[0] <= 2;
50 | bad_queue[0] <= 2;
| ^~~~~~~~~
%Error: t/t_assign_automatic_bad.v:51:5: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'bad_assoc'
%Error: t/t_assign_automatic_bad.v:52:5: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'bad_assoc'
: ... note: In instance 't'
51 | bad_assoc[0] <= 2;
52 | bad_assoc[0] <= 2;
| ^~~~~~~~~
%Error: t/t_assign_automatic_bad.v:54:7: Automatic lifetime variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'm_bad2'
%Error: t/t_assign_automatic_bad.v:55:7: Automatic lifetime variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'm_bad2'
: ... note: In instance 't'
54 | c.m_bad2 <= 2;
55 | c.m_bad2 <= 2;
| ^~~~~~
%Error: t/t_assign_automatic_bad.v:56:10: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 's_dyn'
%Error: t/t_assign_automatic_bad.v:57:10: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 's_dyn'
: ... note: In instance 't'
56 | Cls::s_dyn[0] <= 2;
57 | Cls::s_dyn[0] <= 2;
| ^~~~~
%Error: t/t_assign_automatic_bad.v:58:26: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 's_dyn'
%Error: t/t_assign_automatic_bad.v:63:7: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 's_dyn'
: ... note: In instance 't'
58 | clist[bad_dyn6[0]++].s_dyn[0] <= '1;
63 | ].s_dyn[0] <= '1;
| ^~~~~
%Error: Exiting due to

13
test_regress/t/t_assign_automatic_bad.v
View File

@ -18,8 +18,9 @@ class Cls;
int m_bad2;
endclass
module t(clk);
input clk;
module t (
input clk
);
Cls c;
@ -54,8 +55,12 @@ module t(clk);
c.m_bad2 <= 2; // <--- Error: nonblocking class automatic
Cls::s_dyn <= 2; // OK: nonblocking class static dynarray assignment, not to its element
Cls::s_dyn[0] <= 2; // Error: nonblocking class static dynarray element
clist[bad_dyn6[0]++].s_dyn <= '1; // OK: direct nonblocking assignment to dynamically-sized array
clist[bad_dyn6[0]++].s_dyn[0] <= '1; // Error: nonblocking assigment to dynamically-sized array element
clist[
bad_dyn6[0]++
].s_dyn <= '1; // OK: direct nonblocking assignment to dynamically-sized array
clist[
bad_dyn6[0]++
].s_dyn[0] <= '1; // Error: nonblocking assigment to dynamically-sized array element
mt(ok_7);
$stop;
end

7
test_regress/t/t_assoc_enum.v
View File

@ -4,9 +4,11 @@
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
class X;
typedef enum int {
@ -31,14 +33,11 @@ class X;
endclass
module t;/*AUTOARG*/
module t;
initial begin
X x = new;
$finish;
end
endmodule

2
test_regress/t/t_assoc_method_map.v
View File

@ -5,7 +5,7 @@
// SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
module t;

4
test_regress/t/t_assoc_wildcard_map.out
View File

@ -1,6 +1,6 @@
%Error-UNSUPPORTED: t/t_assoc_wildcard_map.v:17:15: Unsupported: Wildcard array 'map' method (IEEE 1800-2023 7.12.5)
%Error-UNSUPPORTED: t/t_assoc_wildcard_map.v:19:15: Unsupported: Wildcard array 'map' method (IEEE 1800-2023 7.12.5)
: ... note: In instance 't'
17 | res = a.map(el) with (el == 2);
19 | res = a.map(el) with (el == 2);
| ^~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to

4
test_regress/t/t_assoc_wildcard_map.v
View File

@ -4,8 +4,10 @@
// any use, without warranty, 2023 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t;

5
test_regress/t/t_bitsel_concat.v
View File

@ -9,7 +9,10 @@
// warranty, 2024 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
// verilog_format: off
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
// Test IEEE 1800-2023 concat bit selects, function bit selects, method bit selects

3
test_regress/t/t_bitsel_lvalue.v
View File

@ -4,8 +4,7 @@
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t
(
module t (
input wire [31:0] foo,
output reg [144:0] bar,
output reg [144:0] bar2,

2
test_regress/t/t_c_width_bad.out
View File

@ -1,4 +1,4 @@
%Error-UNSUPPORTED: t/t_c_width_bad.v:9:22: Unsupported: $c can't generate wider than 64 bits
%Error-UNSUPPORTED: t/t_c_width_bad.v:9:21: Unsupported: $c can't generate wider than 64 bits
: ... note: In instance 't'
9 | bit [99:0] wide = $c100("0");
| ^~~~~

2
test_regress/t/t_cast_stream.v
View File

@ -4,8 +4,10 @@
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
typedef enum {
UVM_TLM_READ_COMMAND,

7
test_regress/t/t_class_defaultparam_import.v
View File

@ -5,8 +5,11 @@
// SPDX-License-Identifier: CC0-1.0
package foo;
class bar#(type T=int);
class bar #(
type T = int
);
endclass
endpackage;
endpackage
;
import foo::bar;

4
test_regress/t/t_class_extern_typeref.v
View File

@ -4,7 +4,9 @@
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
class uvm_process_guard#(type T=int);
class uvm_process_guard #(
type T = int
);
T m_context;
extern function T get_context();
extern function new(T ctxt);

2
test_regress/t/t_class_hier_construction.v
View File

@ -4,9 +4,11 @@
// any use, without warranty, 2025 by Petr Nohavica
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
interface class IBottomMid;
pure virtual function void moo(int i);

2
test_regress/t/t_class_modscope.v
View File

@ -4,8 +4,10 @@
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module m ();
class c;

8
test_regress/t/t_class_param_extends_static_member_function_access.v
View File

@ -4,13 +4,17 @@
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
class Class1 #(type T);
class Class1 #(
type T
);
static function int get_p();
return 7;
endfunction
endclass
class Class2 #(type T) extends Class1 #(T);
class Class2 #(
type T
) extends Class1 #(T);
static function int get_p2;
return T::get_p();
endfunction

22
test_regress/t/t_class_param_typedef3.v
View File

@ -4,17 +4,19 @@
// without warranty.
// SPDX-License-Identifier: CC0-1.0
class func_c #(parameter p_width=4);
static function logic[p_width-1:0] func(
input logic[p_width-1:0] inb
class func_c #(
parameter p_width = 4
);
static function logic [p_width-1:0] func(input logic [p_width-1:0] inb);
func = inb;
endfunction
endclass
module modA #(parameter p_width = 7)(
input logic [p_width-1:0] sig_a
,output logic [p_width-1:0] sig_b
module modA #(
parameter p_width = 7
) (
input logic [p_width-1:0] sig_a,
output logic [p_width-1:0] sig_b
);
assign sig_b = func_c#(p_width)::func(sig_a);
endmodule
@ -25,9 +27,11 @@ module the_top();
logic [Size-1:0] sig_a;
logic [Size-1:0] sig_b;
modA #(.p_width(Size)) modA(
.sig_a(sig_a)
,.sig_b(sig_b)
modA #(
.p_width(Size)
) modA (
.sig_a(sig_a),
.sig_b(sig_b)
);
//assign sig_b = func_c#(p_width)::func(inb_i);

22
test_regress/t/t_class_param_typedef4.v
View File

@ -4,17 +4,19 @@
// without warranty.
// SPDX-License-Identifier: CC0-1.0
class func_c #(parameter p_width=4);
static function logic[p_width-1:0] func(
input logic[p_width-1:0] inb
class func_c #(
parameter p_width = 4
);
static function logic [p_width-1:0] func(input logic [p_width-1:0] inb);
func = inb;
endfunction
endclass
module modA #(parameter p_width = 7)(
input logic [p_width-1:0] sig_a
,output logic [p_width-1:0] sig_b
module modA #(
parameter p_width = 7
) (
input logic [p_width-1:0] sig_a,
output logic [p_width-1:0] sig_b
);
assign sig_b = func_c#(p_width)::func(sig_a);
endmodule
@ -26,9 +28,11 @@ module the_top();
logic [Size-1:0] sig_b;
logic [Size-1:0] sig_c;
modA #(.p_width(Size)) modA(
.sig_a(sig_a)
,.sig_b(sig_b)
modA #(
.p_width(Size)
) modA (
.sig_a(sig_a),
.sig_b(sig_b)
);
initial begin

18
test_regress/t/t_class_param_typedef5.v
View File

@ -4,18 +4,18 @@
// without warranty.
// SPDX-License-Identifier: CC0-1.0
class func_c #(parameter p_width=4);
typedef struct packed {
logic[p_width-1:0] data;
} my_type_t;
static function my_type_t func(
input logic[p_width-1:0] inb
class func_c #(
parameter p_width = 4
);
typedef struct packed {logic [p_width-1:0] data;} my_type_t;
static function my_type_t func(input logic [p_width-1:0] inb);
func.data = inb;
endfunction
endclass
module modA #(parameter p_width = 7)(
module modA #(
parameter p_width = 7
) (
input func_c#(p_width)::my_type_t sig_a,
output func_c#(p_width)::my_type_t sig_b
);
@ -27,7 +27,9 @@ module the_top();
func_c #(Size)::my_type_t sig_a, sig_b, sig_c;
modA #(.p_width(Size)) modA(
modA #(
.p_width(Size)
) modA (
.sig_a(sig_a),
.sig_b(sig_b)
);

14
test_regress/t/t_class_param_typedef6.v
View File

@ -4,22 +4,16 @@
// without warranty.
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkd(gotv,expv) \
do if ((gotv) !== (expv)) begin \
$write("%%Error: %s:%0d: got=%0d exp=%0d\n", \
`__FILE__,`__LINE__, (gotv), (expv)); \
`stop; \
end while(0);
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
class pipeline_class #(
parameter type XWORD = logic
);
typedef struct packed {
XWORD pc;
} if_id_t;
typedef struct packed {XWORD pc;} if_id_t;
endclass

13
test_regress/t/t_class_param_upcast.v
View File

@ -4,7 +4,9 @@
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
class factory #(type T);
class factory #(
type T
);
static function T create;
T obj = new;
return obj;
@ -24,10 +26,9 @@ endclass
module t;
initial begin
foo f;
if (bit'($random))
f = bar::create;
else
f = factory#(foo)::create();
if (bit'($random)) f = bar::create;
else f = factory#(foo)::create();
$finish;
end
endmodule;
endmodule
;

2
test_regress/t/t_class_scope_import_bad.out
View File

@ -1,4 +1,4 @@
%Error: t/t_class_scope_import_bad.v:11:11: Import statement directly within a class scope is illegal
%Error: t/t_class_scope_import_bad.v:11:10: Import statement directly within a class scope is illegal
11 | import pkg::*;
| ^~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.

2
test_regress/t/t_class_super_new_noextend_bad.out
View File

@ -1,4 +1,4 @@
%Error: t/t_class_super_new_noextend_bad.v:10:12: 'super' used on non-extended class (IEEE 1800-2023 8.15)
%Error: t/t_class_super_new_noextend_bad.v:10:10: 'super' used on non-extended class (IEEE 1800-2023 8.15)
10 | super.new();
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.

2
test_regress/t/t_class_to_basic_assignment_bad.out
View File

@ -1,4 +1,4 @@
%Error: t/t_class_to_basic_assignment_bad.v:26:29: Assign RHS 'class{}Foo' cannot be assigned to non-class 'int'
%Error: t/t_class_to_basic_assignment_bad.v:26:27: Assign RHS 'class{}Foo' cannot be assigned to non-class 'int'
26 | new_node.phase_done = get();
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.

3
test_regress/t/t_clocking_input_0_delay.v
View File

@ -21,8 +21,7 @@ module t;
end
initial begin
#4
if (data != 1) $stop;
#4 if (data != 1) $stop;
if (cb.data != 0) $stop;
#1;
#1step;

3
test_regress/t/t_clocking_input_default.v
View File

@ -21,8 +21,7 @@ module t;
end
initial begin
#4
if(data != 1 ) $stop;
#4 if (data != 1) $stop;
if (cb.data != 0) $stop;
#1;
#1step;

6
test_regress/t/t_constraint_global_arr_unsup.v
View File

@ -73,11 +73,13 @@ module t_constraint_global_arr_unsup;
o.m_mid_arr[1].m_arr[2].m_y == 400) begin
$display("*-* All Finished *-*");
$finish;
end else begin
end
else begin
$display("*-* FAILED *-*");
$stop;
end
end else begin
end
else begin
$display("*-* FAILED: randomize() returned 0 *-*");
$stop;
end

4
test_regress/t/t_constraint_global_randMode.v
View File

@ -6,9 +6,7 @@
class RandomValue;
rand int value;
constraint small_int_c {
value < 10;
}
constraint small_int_c {value < 10;}
task disable_val();
value.rand_mode(0);
endtask

4
test_regress/t/t_constraint_json_only.out
View File

@ -59,9 +59,9 @@
{"type":"BASICDTYPE","name":"logic","addr":"(GB)","loc":"d,22:14,22:15","dtypep":"(GB)","keyword":"logic","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(OB)","loc":"d,25:21,25:22","dtypep":"(OB)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"string","addr":"(M)","loc":"d,73:7,73:13","dtypep":"(M)","keyword":"string","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"int","addr":"(Q)","loc":"d,8:9,8:12","dtypep":"(Q)","keyword":"int","range":"31:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"int","addr":"(Q)","loc":"d,8:9,8:12","dtypep":"(Q)","keyword":"int","range":"31:0","generic":true,"signed":true,"rangep": []},
{"type":"BASICDTYPE","name":"bit","addr":"(U)","loc":"d,11:9,11:12","dtypep":"(U)","keyword":"bit","generic":true,"rangep": []},
{"type":"UNPACKARRAYDTYPE","name":"","addr":"(Y)","loc":"d,15:18,15:19","dtypep":"(Y)","isCompound":false,"declRange":"[0:1]","generic":false,"refDTypep":"(Q)","childDTypep": [],
{"type":"UNPACKARRAYDTYPE","name":"","addr":"(Y)","loc":"d,15:18,15:19","dtypep":"(Y)","isCompound":false,"declRange":"[0:1]","generic":false,"signed":true,"refDTypep":"(Q)","childDTypep": [],
"rangep": [
{"type":"RANGE","name":"","addr":"(PB)","loc":"d,15:18,15:19","ascending":true,"fromBracket":true,
"leftp": [

7
test_regress/t/t_cover_sys_line_expr.out
View File

@ -5,13 +5,10 @@
// any use, without warranty, 2024 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
module t (
input clk
);
input clk;
int cyc, bump, result;
logic foo;
%000001 initial begin

7
test_regress/t/t_cover_sys_line_expr.v
View File

@ -4,13 +4,10 @@
// any use, without warranty, 2024 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
module t (
input clk
);
input clk;
int cyc, bump, result;
logic foo;
initial begin

4
test_regress/t/t_covergroup_in_class_duplicate_bad.out
View File

@ -1,7 +1,7 @@
%Error: t/t_covergroup_in_class_duplicate_bad.v:13:16: Duplicate declaration of CLASS '__vlAnonCG_embeddedCg': '__vlAnonCG_embeddedCg'
%Error: t/t_covergroup_in_class_duplicate_bad.v:13:14: Duplicate declaration of CLASS '__vlAnonCG_embeddedCg': '__vlAnonCG_embeddedCg'
13 | covergroup embeddedCg;
| ^~~~~~~~~~
t/t_covergroup_in_class_duplicate_bad.v:9:16: ... Location of original declaration
t/t_covergroup_in_class_duplicate_bad.v:9:14: ... Location of original declaration
9 | covergroup embeddedCg;
| ^~~~~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.

3
test_regress/t/t_define_override.v
View File

@ -10,8 +10,7 @@
`define STRINGIFY(x) `"x`"
module test (
);
module test ();
initial begin
$display("TEST_MACRO %s", `STRINGIFY(`TEST_MACRO));
$finish;

3
test_regress/t/t_delay_1step.v
View File

@ -5,8 +5,7 @@
// SPDX-License-Identifier: CC0-1.0
module t;
timeunit 10s;
timeprecision 1s;
timeunit 10s; timeprecision 1s;
initial begin
#1;

10
test_regress/t/t_dfg_bin_to_one_hot.v
View File

@ -4,14 +4,14 @@
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: cyc=%0d got='h%x exp='h%x\n", `__FILE__,`__LINE__, cyc, (got), (exp)); `stop; end while(0)
`define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: cyc=%0d got='h%x exp='h%x\n", `__FILE__,`__LINE__, cyc, (gotv), (expv)); `stop; end while(0)
// verilog_format: on
module t (/*AUTOARG*/
// Inputs
clk
module t (
input clk
);
input clk;
reg [31:0] cyc = 0;
reg [6:0] cntA = 0;

6
test_regress/t/t_dfg_circular_merged_scc.v
View File

@ -4,7 +4,11 @@
// any use, without warranty, 2025 by Geza Lore.
// SPDX-License-Identifier: CC0-1.0
module mul (input [8:0] A, input [16:0] B, output [25:0] Y);
module mul (
input [8:0] A,
input [16:0] B,
output [25:0] Y
);
assign Y = $signed(A) * $signed(B);
endmodule

5
test_regress/t/t_dfg_regularize_clk.v
View File

@ -4,9 +4,10 @@
// without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkd(gotv,
expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module sub (
input clk,

4
test_regress/t/t_dfg_result_var_ext_write.v
View File

@ -4,8 +4,10 @@
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: $time=%0t got='h%x exp='h%x\n", `__FILE__,`__LINE__, $time, (got), (exp)); `stop; end while(0)
`define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: $time=%0t got='h%x exp='h%x\n", `__FILE__,`__LINE__, $time, (gotv), (expv)); `stop; end while(0)
// verilog_format: on
module top;

2
test_regress/t/t_dfg_true_cycle_bad.out
View File

@ -4,6 +4,6 @@
... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest
... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
t/t_dfg_true_cycle_bad.v:10:23: Example path: o
t/t_dfg_true_cycle_bad.v:12:22: Example path: ASSIGNW
t/t_dfg_true_cycle_bad.v:12:20: Example path: ASSIGNW
t/t_dfg_true_cycle_bad.v:10:23: Example path: o
%Error: Exiting due to

4
test_regress/t/t_disable_bad.out
View File

@ -1,8 +1,8 @@
%Error: t/t_disable_bad.v:9:15: Can't find definition of block/task: 'abcd'
%Error: t/t_disable_bad.v:9:13: Can't find definition of block/task: 'abcd'
9 | disable abcd;
| ^~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Internal Error: t/t_disable_bad.v:9:7: ../V3LinkJump.cpp:#: Unlinked disable statement
%Error: Internal Error: t/t_disable_bad.v:9:5: ../V3LinkJump.cpp:#: Unlinked disable statement
9 | disable abcd;
| ^~~~~~~
... This fatal error may be caused by the earlier error(s); resolve those first.

2
test_regress/t/t_display_merge.py
View File

@ -11,7 +11,7 @@ import vltest_bootstrap
test.scenarios('simulator_st')
test.compile(verilator_flags2=["--stats"])
test.compile(verilator_flags2=["--stats", "--inline-cfuncs", "0"])
test.execute(expect_filename=test.golden_filename)

88
test_regress/t/t_dist_warn_coverage.py
View File

@ -20,6 +20,8 @@ for s in [
# Instead of adding here, consider adding a LCOV_EXCL_LINE/START/STOP to the sources on the message
'exited with', # Is hit; driver.py filters out
'loading non-variable', # Instead 'storing to parameter' or syntax error
'does not allow '
' in the middle of literal', # Is covered, this parser misses it due to quote
'Assigned pin is neither input nor output', # Instead earlier error
'Define missing argument \'', # Instead get Define passed too many arguments
'Define or directive not defined: `', # Instead V3ParseImp will warn
@ -27,14 +29,19 @@ for s in [
'Syntax error: Range \':\', \'+:\' etc are not allowed in the instance', # Instead get syntax error
'dynamic new() not expected in this context (expected under an assign)', # Instead get syntax error
# Not yet analyzed
'$VERILATOR_ROOT needs to be in environment',
'--pipe-filter protocol error, unexpected:',
'--pipe-filter returned bad status',
'--pipe-filter: stdin/stdout closed before pipe opened',
'--pipe-filter: write to closed file',
'Array initialization has too few elements, need element',
'Assigning >32 bit to unranged parameter (defaults to 32 bits)',
'Assignment pattern with no members',
'Can\'t find varpin scope of',
'Can\'t read annotation file:',
'Can\'t resolve module reference: \'',
'Can\'t write file:',
'Circular logic when ordering code (non-cutable edge loop)',
'Expected data type, not a',
'Extern declaration\'s scope is not a defined class',
'File not found:',
@ -43,11 +50,14 @@ for s in [
'Illegal +: or -: select; type already selected, or bad dimension:',
'Illegal bit or array select; type already selected, or bad dimension:',
'Illegal range select; type already selected, or bad dimension:',
'Instance pin connected by name with empty reference:',
'Interface port declaration',
'Invalid reference: Process might outlive variable',
'Modport item is not a function/task:',
'Modport item is not a variable:',
'Modport not referenced as <interface>.',
'Modport not referenced from underneath an interface:',
'Need $SYSTEMC_INCLUDE in environment or when Verilator configured,',
'Non-interface used as an interface:',
'Parameter type pin value isn\'t a type: Param',
'Parameter type variable isn\'t a type: Param',
@ -59,25 +69,41 @@ for s in [
'Symbol matching',
'Unexpected connection to arrayed port',
'Unsized numbers/parameters not allowed in streams.',
'Unsupported (or syntax error): Foreach on this array\'s construct',
'Unsupported LHS node type in array assignment',
'Unsupported RHS tristate construct:',
'Unsupported or syntax error: Unsized range in instance or other declaration',
'Unsupported pullup/down (weak driver) construct.',
'Unsupported tristate construct (not in propagation graph):',
'Unsupported tristate port expression:',
'Unsupported/unknown built-in queue method',
'Unsupported: $bits for queue',
'Unsupported: &&& expression',
'Unsupported: 4-state numbers in this context',
'Unsupported: Assignments with signal strength with LHS of type:',
'Unsupported: Bind with instance list',
'Unsupported: Cannot detect changes on expression of complex type',
'Unsupported: Cast to',
'Unsupported: Concatenation to form',
'Unsupported: Modport dotted port name',
'Unsupported: Creating tristate signal not underneath a module:',
'Unsupported: Default value on module inout/ref/constref:',
'Unsupported: Modport empty expression',
'Unsupported: Modport export with prototype',
'Unsupported: Modport import with prototype',
'Unsupported: Non-constant default value in missing argument',
'Unsupported: Non-constant index when passing interface to module',
'Unsupported: Only one PSL clock allowed per assertion',
'Unsupported: Per-bit array instantiations',
'Unsupported: Public functions with >64 bit outputs;',
'Unsupported: Public functions with return > 64 bits wide.',
'Unsupported: Release statement argument is too complex array select',
'Unsupported: Replication to form',
'Unsupported: Shifting of by over 32-bit number isn\'t supported.',
'Unsupported: Size-changing cast on non-basic data type',
'Unsupported: Slice of non-constant bounds',
'Unsupported: Stream operation on a variable of a type',
'Unsupported: Unclocked assertion',
'Unsupported: Using --protect-ids with public function',
'Unsupported: Verilog 1995 deassign',
'Unsupported: Verilog 1995 gate primitive:',
'Unsupported: [] dimensions',
@ -85,15 +111,22 @@ for s in [
'Unsupported: \'{} .* patterns',
'Unsupported: assertion items in clocking blocks',
'Unsupported: don\'t know how to deal with',
'Unsupported: extern constraint definition with class-in-class',
'Unsupported: extern forkjoin',
'Unsupported: extern task',
'Unsupported: modport export',
'Unsupported: no_inline for tasks',
'Unsupported: non-const assert directive type expression',
'Unsupported: property port \'local\'',
'Unsupported: randsequence production function variable',
'Unsupported: repeat event control',
'Unsupported: static cast to',
'Unsupported: super',
'Unsupported: with[] stream expression',
'expected non-complex non-double',
'is not an unpacked array, but is in an unpacked array context',
'loading other than unpacked-array variable',
'loading other than unpacked/associative-array variable',
]:
Suppressed[s] = True
@ -106,7 +139,8 @@ def read_messages():
continue
with open(filename, 'r', encoding="utf8") as fh:
lineno = 0
read_next = None
statement = ""
statement_lineno = 0
excl = False
excl_next = False
@ -118,36 +152,52 @@ def read_messages():
if re.match(r'^\s*/\*', line):
continue
excl = excl_next
# print(('C ' if (statement != "") else 'L') + line)
if 'LCOV_EXCL_START' in line:
excl = True
excl_next = True
if 'LCOV_EXCL_STOP' in line:
excl_next = False # Reenables coverage on next line, not this one
if re.search(r'\b(v3error|v3warn|v3fatal|BBUNSUP)\b\($', line):
if 'LCOV_EXCL_LINE' not in line:
read_next = True
continue
m = re.search(r'.*\b(v3error|v3warn|v3fatal|BBUNSUP)\b(.*)', line)
if m:
line = m.group(2)
if 'LCOV_EXCL_LINE' not in line:
read_next = True
if read_next:
read_next = False
if 'LCOV_EXCL_LINE' in line:
continue
excl = True
if excl:
statement = ""
continue
if "\\" in line: # \" messes up next part
line = re.sub(r'\\n', '', line)
line = re.sub(r'\s+//.*', '', line)
line = line.rstrip()
m = re.search(r'\b((v3error|v3warn|v3fatal|BBUNSUP)\b.*)', line)
if m:
statement = m.group(1)
statement_lineno = lineno
if statement == "":
continue
m = re.search(r'"([^"]*)"', line)
statement += line
if ');' not in statement:
continue # Keep reading lines until get end of statement
if '\\"' in statement:
continue # Parser messes these up
# print("SSS " + statement)
m = re.search(r'"([^"]*)"', statement)
if m:
msg = m.group(1)
fileline = filename + ":" + str(lineno)
# print("FFFF " + fileline + ": " + msg + " LL " + line)
msg = re.sub(r'\s+$', '', msg)
msg = re.sub(r'^\s+', '', msg)
fileline = filename + ":" + str(statement_lineno)
# print("FFFF " + fileline + ": " + msg + " LL " + statement)
Messages[msg] = {}
Messages[msg]['fileline'] = fileline
Messages[msg]['line'] = origline
Messages[msg]['line'] = statement
statement = ""
print("Number of messages = " + str(len(Messages)))

12
test_regress/t/t_dpi_inline_new.v
View File

@ -9,8 +9,10 @@
package pyhdl_if;
typedef chandle PyObject;
import "DPI-C" context function PyObject _pyhdl_if_PyTuple_GetItem(input PyObject p0,
input longint unsigned p1);
import "DPI-C" context function PyObject _pyhdl_if_PyTuple_GetItem(
input PyObject p0,
input longint unsigned p1
);
function PyObject PyTuple_GetItem(input PyObject p0, input longint unsigned p1);
return _pyhdl_if_PyTuple_GetItem(p0, p1);
@ -32,11 +34,9 @@ package pyhdl_if;
endpackage
module t (/*AUTOARG*/
// Inputs
clk
module t (
input clk
);
input clk;
import pyhdl_if::*;

86
test_regress/t/t_dump_json.out
View File

@ -9,7 +9,7 @@
],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"cyc","addr":"(K)","loc":"e,13:12,13:15","dtypep":"UNLINKED","origName":"cyc","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED",
"childDTypep": [
{"type":"BASICDTYPE","name":"integer","addr":"(L)","loc":"e,13:4,13:11","dtypep":"(L)","keyword":"integer","range":"31:0","generic":false,"rangep": []}
{"type":"BASICDTYPE","name":"integer","addr":"(L)","loc":"e,13:4,13:11","dtypep":"(L)","keyword":"integer","range":"31:0","generic":false,"signed":true,"rangep": []}
],"delayp": [],
"valuep": [
{"type":"CONST","name":"?32?sh0","addr":"(M)","loc":"e,13:18,13:19","dtypep":"(N)"}
@ -1217,7 +1217,7 @@
{"type":"TYPEDEFFWD","name":"T","addr":"(GS)","loc":"d,34:12,34:13","fwdType":"none"},
{"type":"VAR","name":"m_bound","addr":"(HS)","loc":"d,36:19,36:26","dtypep":"UNLINKED","origName":"m_bound","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED",
"childDTypep": [
{"type":"BASICDTYPE","name":"int","addr":"(IS)","loc":"d,36:15,36:18","dtypep":"(IS)","keyword":"int","range":"31:0","generic":false,"rangep": []}
{"type":"BASICDTYPE","name":"int","addr":"(IS)","loc":"d,36:15,36:18","dtypep":"(IS)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"m_queue","addr":"(JS)","loc":"d,37:17,37:24","dtypep":"UNLINKED","origName":"m_queue","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED",
"childDTypep": [
@ -1233,7 +1233,7 @@
"stmtsp": [
{"type":"VAR","name":"bound","addr":"(PS)","loc":"d,39:22,39:27","dtypep":"UNLINKED","origName":"bound","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED",
"childDTypep": [
{"type":"BASICDTYPE","name":"int","addr":"(QS)","loc":"d,39:18,39:21","dtypep":"(QS)","keyword":"int","range":"31:0","generic":false,"rangep": []}
{"type":"BASICDTYPE","name":"int","addr":"(QS)","loc":"d,39:18,39:21","dtypep":"(QS)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
],"delayp": [],
"valuep": [
{"type":"CONST","name":"?32?sh0","addr":"(RS)","loc":"d,39:30,39:31","dtypep":"(N)"}
@ -1248,7 +1248,7 @@
],"scopeNamep": []},
{"type":"FUNC","name":"num","addr":"(VS)","loc":"d,43:18,43:21","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"num",
"fvarp": [
{"type":"BASICDTYPE","name":"int","addr":"(WS)","loc":"d,43:14,43:17","dtypep":"(WS)","keyword":"int","range":"31:0","generic":false,"rangep": []}
{"type":"BASICDTYPE","name":"int","addr":"(WS)","loc":"d,43:14,43:17","dtypep":"(WS)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
],"classOrPackagep": [],
"stmtsp": [
{"type":"RETURN","name":"","addr":"(XS)","loc":"d,44:7,44:13",
@ -1334,7 +1334,7 @@
],"scopeNamep": []},
{"type":"FUNC","name":"try_put","addr":"(CU)","loc":"d,55:18,55:25","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"try_put",
"fvarp": [
{"type":"BASICDTYPE","name":"int","addr":"(DU)","loc":"d,55:14,55:17","dtypep":"(DU)","keyword":"int","range":"31:0","generic":false,"rangep": []}
{"type":"BASICDTYPE","name":"int","addr":"(DU)","loc":"d,55:14,55:17","dtypep":"(DU)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
],"classOrPackagep": [],
"stmtsp": [
{"type":"VAR","name":"message","addr":"(EU)","loc":"d,55:28,55:35","dtypep":"UNLINKED","origName":"message","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED",
@ -1453,7 +1453,7 @@
],"scopeNamep": []},
{"type":"FUNC","name":"try_get","addr":"(VV)","loc":"d,72:18,72:25","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"try_get",
"fvarp": [
{"type":"BASICDTYPE","name":"int","addr":"(WV)","loc":"d,72:14,72:17","dtypep":"(WV)","keyword":"int","range":"31:0","generic":false,"rangep": []}
{"type":"BASICDTYPE","name":"int","addr":"(WV)","loc":"d,72:14,72:17","dtypep":"(WV)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
],"classOrPackagep": [],
"stmtsp": [
{"type":"VAR","name":"message","addr":"(XV)","loc":"d,72:32,72:39","dtypep":"UNLINKED","origName":"message","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED",
@ -1557,7 +1557,7 @@
],"scopeNamep": []},
{"type":"FUNC","name":"try_peek","addr":"(JX)","loc":"d,89:18,89:26","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"try_peek",
"fvarp": [
{"type":"BASICDTYPE","name":"int","addr":"(KX)","loc":"d,89:14,89:17","dtypep":"(KX)","keyword":"int","range":"31:0","generic":false,"rangep": []}
{"type":"BASICDTYPE","name":"int","addr":"(KX)","loc":"d,89:14,89:17","dtypep":"(KX)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
],"classOrPackagep": [],
"stmtsp": [
{"type":"VAR","name":"message","addr":"(LX)","loc":"d,89:33,89:40","dtypep":"UNLINKED","origName":"message","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED",
@ -1606,13 +1606,13 @@
"stmtsp": [
{"type":"VAR","name":"m_keyCount","addr":"(CY)","loc":"d,100:19,100:29","dtypep":"UNLINKED","origName":"m_keyCount","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED",
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{"type":"BASICDTYPE","name":"int","addr":"(DY)","loc":"d,100:15,100:18","dtypep":"(DY)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
],"delayp": [],"valuep": [],"attrsp": []},
{"type":"FUNC","name":"new","addr":"(EY)","loc":"d,102:14,102:17","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"new","fvarp": [],"classOrPackagep": [],
"stmtsp": [
{"type":"VAR","name":"keyCount","addr":"(FY)","loc":"d,102:22,102:30","dtypep":"UNLINKED","origName":"keyCount","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED",
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{"type":"BASICDTYPE","name":"int","addr":"(GY)","loc":"d,102:18,102:21","dtypep":"(GY)","keyword":"int","range":"31:0","generic":false,"rangep": []}
{"type":"BASICDTYPE","name":"int","addr":"(GY)","loc":"d,102:18,102:21","dtypep":"(GY)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
],"delayp": [],
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{"type":"CONST","name":"?32?sh0","addr":"(HY)","loc":"d,102:33,102:34","dtypep":"(N)"}
@ -1629,7 +1629,7 @@
"stmtsp": [
{"type":"VAR","name":"keyCount","addr":"(MY)","loc":"d,106:27,106:35","dtypep":"UNLINKED","origName":"keyCount","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED",
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{"type":"BASICDTYPE","name":"int","addr":"(NY)","loc":"d,106:23,106:26","dtypep":"(NY)","keyword":"int","range":"31:0","generic":false,"rangep": []}
{"type":"BASICDTYPE","name":"int","addr":"(NY)","loc":"d,106:23,106:26","dtypep":"(NY)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
],"delayp": [],
"valuep": [
{"type":"CONST","name":"?32?sh1","addr":"(OY)","loc":"d,106:38,106:39","dtypep":"(N)"}
@ -1652,7 +1652,7 @@
"stmtsp": [
{"type":"VAR","name":"keyCount","addr":"(VY)","loc":"d,110:18,110:26","dtypep":"UNLINKED","origName":"keyCount","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED",
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{"type":"BASICDTYPE","name":"int","addr":"(WY)","loc":"d,110:14,110:17","dtypep":"(WY)","keyword":"int","range":"31:0","generic":false,"rangep": []}
{"type":"BASICDTYPE","name":"int","addr":"(WY)","loc":"d,110:14,110:17","dtypep":"(WY)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
],"delayp": [],
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{"type":"CONST","name":"?32?sh1","addr":"(XY)","loc":"d,110:29,110:30","dtypep":"(N)"}
@ -1699,12 +1699,12 @@
],"scopeNamep": []},
{"type":"FUNC","name":"try_get","addr":"(NZ)","loc":"d,119:18,119:25","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"try_get",
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{"type":"BASICDTYPE","name":"int","addr":"(OZ)","loc":"d,119:14,119:17","dtypep":"(OZ)","keyword":"int","range":"31:0","generic":false,"rangep": []}
{"type":"BASICDTYPE","name":"int","addr":"(OZ)","loc":"d,119:14,119:17","dtypep":"(OZ)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
],"classOrPackagep": [],
"stmtsp": [
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{"type":"BASICDTYPE","name":"int","addr":"(QZ)","loc":"d,119:26,119:29","dtypep":"(QZ)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
],"delayp": [],
"valuep": [
{"type":"CONST","name":"?32?sh1","addr":"(RZ)","loc":"d,119:41,119:42","dtypep":"(N)"}
@ -1753,9 +1753,9 @@
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{"type":"DEFIMPLICITDTYPE","name":"__typeimpenum0","addr":"(IAB)","loc":"d,130:13,130:17","dtypep":"UNLINKED","generic":false,
"childDTypep": [
{"type":"ENUMDTYPE","name":"","addr":"(JAB)","loc":"d,130:13,130:17","dtypep":"UNLINKED","enum":true,"generic":false,"refDTypep":"UNLINKED",
{"type":"ENUMDTYPE","name":"","addr":"(JAB)","loc":"d,130:13,130:17","dtypep":"UNLINKED","enum":true,"generic":false,"signed":true,"refDTypep":"UNLINKED",
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{"type":"BASICDTYPE","name":"int","addr":"(KAB)","loc":"d,130:18,130:19","dtypep":"(KAB)","keyword":"int","range":"31:0","generic":false,"rangep": []}
{"type":"BASICDTYPE","name":"int","addr":"(KAB)","loc":"d,130:18,130:19","dtypep":"(KAB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
],
"itemsp": [
{"type":"ENUMITEM","name":"FINISHED","addr":"(LAB)","loc":"d,131:7,131:15","dtypep":"UNLINKED","rangep": [],
@ -2025,7 +2025,7 @@
],"extendsp": []},
{"type":"FUNC","name":"randomize","addr":"(GFB)","loc":"d,242:16,242:25","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"randomize",
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{"type":"BASICDTYPE","name":"int","addr":"(HFB)","loc":"d,242:12,242:15","dtypep":"(HFB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
],"classOrPackagep": [],
"stmtsp": [
{"type":"ASSIGN","name":"","addr":"(IFB)","loc":"d,243:15,243:16","dtypep":"UNLINKED",
@ -2048,11 +2048,11 @@
],"valuep": []},
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{"type":"BASICDTYPE","name":"int","addr":"(RFB)","loc":"d,251:5,251:8","dtypep":"(RFB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
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{"type":"MEMBERDTYPE","name":"goal","addr":"(SFB)","loc":"d,252:9,252:13","dtypep":"UNLINKED","isConstrainedRand":false,"name":"goal","tag":"","generic":false,"refDTypep":"UNLINKED",
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{"type":"BASICDTYPE","name":"int","addr":"(TFB)","loc":"d,252:5,252:8","dtypep":"(TFB)","keyword":"int","range":"31:0","generic":false,"rangep": []}
{"type":"BASICDTYPE","name":"int","addr":"(TFB)","loc":"d,252:5,252:8","dtypep":"(TFB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
],"valuep": []},
{"type":"MEMBERDTYPE","name":"comment","addr":"(UFB)","loc":"d,253:12,253:19","dtypep":"UNLINKED","isConstrainedRand":false,"name":"comment","tag":"","generic":false,"refDTypep":"UNLINKED",
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@ -2060,15 +2060,15 @@
],"valuep": []},
{"type":"MEMBERDTYPE","name":"at_least","addr":"(WFB)","loc":"d,254:9,254:17","dtypep":"UNLINKED","isConstrainedRand":false,"name":"at_least","tag":"","generic":false,"refDTypep":"UNLINKED",
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{"type":"BASICDTYPE","name":"int","addr":"(XFB)","loc":"d,254:5,254:8","dtypep":"(XFB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
],"valuep": []},
{"type":"MEMBERDTYPE","name":"auto_bin_max","addr":"(YFB)","loc":"d,255:9,255:21","dtypep":"UNLINKED","isConstrainedRand":false,"name":"auto_bin_max","tag":"","generic":false,"refDTypep":"UNLINKED",
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{"type":"BASICDTYPE","name":"int","addr":"(ZFB)","loc":"d,255:5,255:8","dtypep":"(ZFB)","keyword":"int","range":"31:0","generic":false,"rangep": []}
{"type":"BASICDTYPE","name":"int","addr":"(ZFB)","loc":"d,255:5,255:8","dtypep":"(ZFB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
],"valuep": []},
{"type":"MEMBERDTYPE","name":"cross_num_print_missing","addr":"(AGB)","loc":"d,256:9,256:32","dtypep":"UNLINKED","isConstrainedRand":false,"name":"cross_num_print_missing","tag":"","generic":false,"refDTypep":"UNLINKED",
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{"type":"BASICDTYPE","name":"int","addr":"(BGB)","loc":"d,256:5,256:8","dtypep":"(BGB)","keyword":"int","range":"31:0","generic":false,"rangep": []}
{"type":"BASICDTYPE","name":"int","addr":"(BGB)","loc":"d,256:5,256:8","dtypep":"(BGB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
],"valuep": []},
{"type":"MEMBERDTYPE","name":"cross_retain_auto_bins","addr":"(CGB)","loc":"d,257:9,257:31","dtypep":"UNLINKED","isConstrainedRand":false,"name":"cross_retain_auto_bins","tag":"","generic":false,"refDTypep":"UNLINKED",
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@ -2097,11 +2097,11 @@
"membersp": [
{"type":"MEMBERDTYPE","name":"weight","addr":"(NGB)","loc":"d,264:9,264:15","dtypep":"UNLINKED","isConstrainedRand":false,"name":"weight","tag":"","generic":false,"refDTypep":"UNLINKED",
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{"type":"BASICDTYPE","name":"int","addr":"(OGB)","loc":"d,264:5,264:8","dtypep":"(OGB)","keyword":"int","range":"31:0","generic":false,"rangep": []}
{"type":"BASICDTYPE","name":"int","addr":"(OGB)","loc":"d,264:5,264:8","dtypep":"(OGB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
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{"type":"MEMBERDTYPE","name":"goal","addr":"(PGB)","loc":"d,265:9,265:13","dtypep":"UNLINKED","isConstrainedRand":false,"name":"goal","tag":"","generic":false,"refDTypep":"UNLINKED",
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{"type":"BASICDTYPE","name":"int","addr":"(QGB)","loc":"d,265:5,265:8","dtypep":"(QGB)","keyword":"int","range":"31:0","generic":false,"rangep": []}
{"type":"BASICDTYPE","name":"int","addr":"(QGB)","loc":"d,265:5,265:8","dtypep":"(QGB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
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{"type":"MEMBERDTYPE","name":"comment","addr":"(RGB)","loc":"d,266:12,266:19","dtypep":"UNLINKED","isConstrainedRand":false,"name":"comment","tag":"","generic":false,"refDTypep":"UNLINKED",
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@ -2109,11 +2109,11 @@
],"valuep": []},
{"type":"MEMBERDTYPE","name":"at_least","addr":"(TGB)","loc":"d,267:9,267:17","dtypep":"UNLINKED","isConstrainedRand":false,"name":"at_least","tag":"","generic":false,"refDTypep":"UNLINKED",
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{"type":"BASICDTYPE","name":"int","addr":"(UGB)","loc":"d,267:5,267:8","dtypep":"(UGB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
],"valuep": []},
{"type":"MEMBERDTYPE","name":"auto_bin_max","addr":"(VGB)","loc":"d,268:9,268:21","dtypep":"UNLINKED","isConstrainedRand":false,"name":"auto_bin_max","tag":"","generic":false,"refDTypep":"UNLINKED",
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{"type":"BASICDTYPE","name":"int","addr":"(WGB)","loc":"d,268:5,268:8","dtypep":"(WGB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
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{"type":"MEMBERDTYPE","name":"detect_overlap","addr":"(XGB)","loc":"d,269:9,269:23","dtypep":"UNLINKED","isConstrainedRand":false,"name":"detect_overlap","tag":"","generic":false,"refDTypep":"UNLINKED",
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@ -2130,11 +2130,11 @@
"membersp": [
{"type":"MEMBERDTYPE","name":"weight","addr":"(CHB)","loc":"d,273:9,273:15","dtypep":"UNLINKED","isConstrainedRand":false,"name":"weight","tag":"","generic":false,"refDTypep":"UNLINKED",
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{"type":"BASICDTYPE","name":"int","addr":"(DHB)","loc":"d,273:5,273:8","dtypep":"(DHB)","keyword":"int","range":"31:0","generic":false,"rangep": []}
{"type":"BASICDTYPE","name":"int","addr":"(DHB)","loc":"d,273:5,273:8","dtypep":"(DHB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
],"valuep": []},
{"type":"MEMBERDTYPE","name":"goal","addr":"(EHB)","loc":"d,274:9,274:13","dtypep":"UNLINKED","isConstrainedRand":false,"name":"goal","tag":"","generic":false,"refDTypep":"UNLINKED",
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{"type":"BASICDTYPE","name":"int","addr":"(FHB)","loc":"d,274:5,274:8","dtypep":"(FHB)","keyword":"int","range":"31:0","generic":false,"rangep": []}
{"type":"BASICDTYPE","name":"int","addr":"(FHB)","loc":"d,274:5,274:8","dtypep":"(FHB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
],"valuep": []},
{"type":"MEMBERDTYPE","name":"comment","addr":"(GHB)","loc":"d,275:12,275:19","dtypep":"UNLINKED","isConstrainedRand":false,"name":"comment","tag":"","generic":false,"refDTypep":"UNLINKED",
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@ -2142,11 +2142,11 @@
],"valuep": []},
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{"type":"BASICDTYPE","name":"int","addr":"(JHB)","loc":"d,276:5,276:8","dtypep":"(JHB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
],"valuep": []},
{"type":"MEMBERDTYPE","name":"cross_num_print_missing","addr":"(KHB)","loc":"d,277:9,277:32","dtypep":"UNLINKED","isConstrainedRand":false,"name":"cross_num_print_missing","tag":"","generic":false,"refDTypep":"UNLINKED",
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{"type":"BASICDTYPE","name":"int","addr":"(LHB)","loc":"d,277:5,277:8","dtypep":"(LHB)","keyword":"int","range":"31:0","generic":false,"rangep": []}
{"type":"BASICDTYPE","name":"int","addr":"(LHB)","loc":"d,277:5,277:8","dtypep":"(LHB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
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{"type":"MEMBERDTYPE","name":"cross_retain_auto_bins","addr":"(MHB)","loc":"d,278:9,278:31","dtypep":"UNLINKED","isConstrainedRand":false,"name":"cross_retain_auto_bins","tag":"","generic":false,"refDTypep":"UNLINKED",
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@ -2163,11 +2163,11 @@
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{"type":"BASICDTYPE","name":"int","addr":"(SHB)","loc":"d,282:5,282:8","dtypep":"(SHB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
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{"type":"BASICDTYPE","name":"int","addr":"(UHB)","loc":"d,283:5,283:8","dtypep":"(UHB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
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@ -2200,11 +2200,11 @@
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{"type":"BASICDTYPE","name":"int","addr":"(JIB)","loc":"d,292:5,292:8","dtypep":"(JIB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
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{"type":"BASICDTYPE","name":"int","addr":"(LIB)","loc":"d,293:5,293:8","dtypep":"(LIB)","keyword":"int","range":"31:0","generic":false,"rangep": []}
{"type":"BASICDTYPE","name":"int","addr":"(LIB)","loc":"d,293:5,293:8","dtypep":"(LIB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []}
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@ -2225,11 +2225,11 @@
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@ -2243,21 +2243,21 @@
"miscsp": [
{"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(ZT)",
"typesp": [
{"type":"BASICDTYPE","name":"integer","addr":"(NS)","loc":"d,37:25,37:26","dtypep":"(NS)","keyword":"integer","range":"31:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(N)","loc":"d,39:30,39:31","dtypep":"(N)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"integer","addr":"(NS)","loc":"d,37:25,37:26","dtypep":"(NS)","keyword":"integer","range":"31:0","generic":true,"signed":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(N)","loc":"d,39:30,39:31","dtypep":"(N)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(YE)","loc":"d,49:22,49:24","dtypep":"(YE)","keyword":"logic","generic":true,"rangep": []},
{"type":"VOIDDTYPE","name":"","addr":"(ZT)","loc":"d,51:15,51:24","dtypep":"(ZT)","generic":false},
{"type":"BASICDTYPE","name":"logic","addr":"(UD)","loc":"d,133:17,133:18","dtypep":"(UD)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(VAB)","loc":"d,135:16,135:17","dtypep":"(VAB)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(UD)","loc":"d,133:17,133:18","dtypep":"(UD)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(VAB)","loc":"d,135:16,135:17","dtypep":"(VAB)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(JCB)","loc":"d,168:14,168:53","dtypep":"(JCB)","keyword":"logic","range":"295:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"string","addr":"(FG)","loc":"d,168:7,168:13","dtypep":"(FG)","keyword":"string","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(S)","loc":"e,14:9,14:11","dtypep":"(S)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(DB)","loc":"e,18:10,18:12","dtypep":"(DB)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(S)","loc":"e,14:9,14:11","dtypep":"(S)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(DB)","loc":"e,18:10,18:12","dtypep":"(DB)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(QC)","loc":"e,33:26,33:31","dtypep":"(QC)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(NC)","loc":"e,33:25,33:26","dtypep":"(NC)","keyword":"logic","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(EF)","loc":"e,45:17,45:38","dtypep":"(EF)","keyword":"logic","range":"63:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(NF)","loc":"e,48:22,48:24","dtypep":"(NF)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(WF)","loc":"e,51:22,51:24","dtypep":"(WF)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(NF)","loc":"e,48:22,48:24","dtypep":"(NF)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(WF)","loc":"e,51:22,51:24","dtypep":"(WF)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(HG)","loc":"e,54:17,54:49","dtypep":"(HG)","keyword":"logic","range":"231:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"QData","addr":"(JG)","loc":"e,54:51,54:56","dtypep":"(JG)","keyword":"QData","range":"63:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(AH)","loc":"e,59:17,59:41","dtypep":"(AH)","keyword":"logic","range":"167:0","generic":true,"rangep": []}

2
test_regress/t/t_event_control_expr_unsup.out
View File

@ -1,4 +1,4 @@
%Error-UNSUPPORTED: t/t_event_control_expr_unsup.v:15:21: Unsupported: Impure function calls in sensitivity lists
%Error-UNSUPPORTED: t/t_event_control_expr_unsup.v:15:20: Unsupported: Impure function calls in sensitivity lists
15 | always @(posedge foo());
| ^~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest

10
test_regress/t/t_expr_shortcircuit.v
View File

@ -4,13 +4,10 @@
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
module t (
input clk
);
input clk;
int cyc = 0;
function automatic logic is_odd(int value);
@ -20,8 +17,7 @@ module t (/*AUTOARG*/
endfunction
always_ff @(posedge clk) begin
if (cyc[0] == 1'b0 || is_odd(cyc))
cyc <= cyc + 1;
if (cyc[0] == 1'b0 || is_odd(cyc)) cyc <= cyc + 1;
if (cyc == 10) begin
$write("*-* All Finished *-*\n");
$finish;

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