24 lines
440 B
Systemverilog
24 lines
440 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module top;
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sub inst (
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.a({128{1'b1}}),
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.b({128{1'b1}})
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);
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endmodule
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module sub (
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a,
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b
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);
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input [127:0] a;
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input [127:0] b;
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always @(a or b) begin
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$display("doesn't matter");
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end
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endmodule
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