117 lines
2.2 KiB
Systemverilog
117 lines
2.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2025 by Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc;
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initial cyc = 1;
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Test test (
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/*AUTOINST*/
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// Inputs
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.clk(clk),
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.cyc(cyc)
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);
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always @(posedge clk) begin
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if (cyc != 0) begin
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cyc <= cyc + 1;
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`ifdef TEST_VERBOSE
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$display("cyc=%0d", cyc);
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`endif
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if (cyc == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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// Interface for data validation with coverage
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interface data_valid_if (
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input logic clk
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);
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logic enable_invalid_data_checks;
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logic valid;
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logic [7:0] data;
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property dataIsKnownWhenValid;
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@(posedge clk) enable_invalid_data_checks & valid |-> !$isunknown(data);
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endproperty
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assert_dataIsKnownWhenValid: assert property (dataIsKnownWhenValid)
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else $error("Data contains unknown values when valid is asserted");
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endinterface
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module Test (
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input clk,
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input integer cyc
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);
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logic rst_n;
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// Instantiate the interface
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data_valid_if dv_if (clk);
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// Reset logic
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initial begin
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rst_n = 0;
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dv_if.enable_invalid_data_checks = 0;
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end
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always @(posedge clk) begin
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if (cyc == 1) begin
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rst_n <= 1'b1;
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end
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end
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// Stimulus: Enable checks after reset
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always @(posedge clk) begin
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if (cyc == 2) begin
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dv_if.enable_invalid_data_checks <= 1'b1;
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end
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end
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// Simulate data transactions
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always @(posedge clk) begin
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case (cyc)
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3: begin
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dv_if.valid <= 1'b0;
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dv_if.data <= 8'h00;
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end
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4: begin
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dv_if.valid <= 1'b1;
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dv_if.data <= 8'hAA; // Valid data
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end
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5: begin
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dv_if.valid <= 1'b1;
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dv_if.data <= 8'h55; // Valid data
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end
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6: begin
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dv_if.valid <= 1'b0;
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dv_if.data <= 8'hxx; // Unknown OK when valid=0
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end
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7: begin
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dv_if.valid <= 1'b1;
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dv_if.data <= 8'hFF; // Valid data
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end
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8: begin
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dv_if.valid <= 1'b0;
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dv_if.data <= 8'h00;
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end
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default: begin
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dv_if.valid <= 1'b0;
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dv_if.data <= 8'h00;
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end
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endcase
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end
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endmodule
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