diff --git a/CITATION.cff b/CITATION.cff index 61136d929..a3e43ff86 100644 --- a/CITATION.cff +++ b/CITATION.cff @@ -1,3 +1,4 @@ +--- # See https://citation-file-format.github.io/ cff-version: 1.2.0 title: Verilator @@ -14,14 +15,14 @@ authors: family-names: Wasson - given-names: Duane family-names: Galbi + - given-names: Geza + family-names: Lore - name: 'et al' repository-code: 'https://github.com/verilator/verilator' url: 'https://verilator.org' abstract: >- The Verilator package converts Verilog and SystemVerilog hardware description language (HDL) designs into a fast C++ or SystemC model - that, after compiling, can be executed. Verilator is not a + that, after compiling, can be executed. Verilator is not only a traditional simulator but a compiler. -license: - - LGPL-3.0-only - - Artistic-2.0 +license: [LGPL-3.0-only, Artistic-2.0] diff --git a/Changes b/Changes index 4ae4b59fa..a02b5f99e 100644 --- a/Changes +++ b/Changes @@ -44,6 +44,7 @@ Verilator 5.043 devel * Support general global constraints (#6709) (#6711). [Yilou Wang] * Support complex std::randomize patterns (#6736) (#6737). [Yilou Wang] * Support `rand_mode` in global constraint gathering (#6740) (#6752). [Yilou Wang] +* Support reduction or in constraints (#6840). [Pawel Kojma, Antmicro Ltd.] * Optimize away calls to empty functions (#6626). [Geza Lore] * Optimize redundant headers in Syms implementation files. [Geza Lore, Fractile Ltd.] * Optimize constructor/destructor VerilatedModules (#6660). [Geza Lore, Fractile Ltd.] @@ -56,6 +57,7 @@ Verilator 5.043 devel * Fix generate function(s) inside of generate blocks (#1011) (#6789). [em2machine] * Fix typedef derived from type defined inside interface (#3441) (#6776). [em2machine] * Fix extern function that returns parameterized class (#4924). +* Fix type deduction for variable parameterized classes (#6281) (#6813). [em2machine] * Fix randomize called within func/task (#6144) (#6753). [Yilou Wang] * Fix pre/post_randomize on extended classes (#6467). [Alex Solomatnikov] * Fix expression short circuiting (#6483). [Todd Strader] @@ -92,7 +94,8 @@ Verilator 5.043 devel * Fix fork scheduling semantics (#6730). [Artur Bieniek, Antmicro Ltd.] * Fix internal fault when cross-class calling with DPI (#6735) (#6742). [Matthew Ballance] * Fix write variable placement for global constraints (#6740) (#6750) (#6797). [Yilou Wang] -* Fix resolution of specialized typedefs (#6754) (#6808). [em2machine] +* Fix JSON dump missing output ports (#6751) (#6831). [Oleh Maksymenko] +* Fix resolution of specialized typedefs (#6754) (#6808) (#6834). [em2machine] * Fix UNSUPPORTED on force / release with complex selects (#6755). [Ryszard Rozak, Antmicro Ltd.] * Fix select assignment expansion (#6757). [Geza Lore] * Fix `--lib-create` with multi-bit clocks (#6759). [Geza Lore] @@ -108,9 +111,14 @@ Verilator 5.043 devel * Fix `disable iff` in simple properties (#6783). [Ryszard Rozak, Antmicro Ltd.] * Fix input sampling of clocking block signals (#6788). [Pawel Kojma, Antmicro Ltd.] * Fix O(n*2) analysis in const-bit-op-tree (#6791). [Geza Lore] -* Fix nested struct within parameter port list (#6818) (#6824). [Luca Colagrande] +* Fix member select of variable without randmode (#6800) (#6833). [Yilou Wang] * Fix duplicate name error with interface initial blocks (#6804) (#6805). [Thomas Dybdahl Ahle] +* Fix nested struct within parameter port list (#6818) (#6824). [Luca Colagrande] +* Fix setting thread count in VerilatedContext (#6826 partial) (#6841). [Yangyu Chen] * Fix firing array selects of events (#6829). [Amal Araweelo Almis] +* Fix false IMPLICITSTATIC on localparam (#6835). [Geza Lore] +* Fix randcase under fork (#6843). [Amal Araweelo Almis] +* Fix JSON missing `signed` indication (#6845). Verilator 5.042 2025-11-02 @@ -551,6 +559,7 @@ Verilator 5.034 2025-02-24 * Optimize labels as final `if` block statements (#5744). * Optimize empty function definition bodies (#5750). * Optimize splitting trigger computation and dump (#5798). [Geza Lore] +* Optimize some DFG multiplexers (#6822). [Yangyu Chen] * Fix error message when call task as a function (#3089). [Matthew Ballance] * Fix force VPI public signal visibility (#5225). [Frédéric Requin] * Fix VPI iteration over hierarchy (#5314) (#5731). [Natan Kreimer] diff --git a/Makefile.in b/Makefile.in index 15134ab35..5e1b787e7 100644 --- a/Makefile.in +++ b/Makefile.in @@ -541,6 +541,7 @@ YAML_FILES = \ .*.yml \ .github/*.yml \ .github/*/*.yml \ + CITATION.cff \ ###################################################################### # Format diff --git a/bin/verilator b/bin/verilator index 62970eadd..730148ed8 100755 --- a/bin/verilator +++ b/bin/verilator @@ -408,6 +408,8 @@ detailed descriptions of these arguments. -I Directory to search for includes --if-depth Tune IFDEPTH warning +incdir+ Directory to search for includes + --inline-cfuncs Inline CFuncs with <=value nodes (0=off) + --inline-cfuncs-product Inline CFuncs if size*calls <= value --inline-mult Tune module inlining --instr-count-dpi Assumed dynamic instruction count of DPI imports -j Parallelism for --build-jobs/--verilate-jobs diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS index 0c8b1cc0b..2ca03eddd 100644 --- a/docs/CONTRIBUTORS +++ b/docs/CONTRIBUTORS @@ -125,6 +125,7 @@ John Wehle Jonathan Drolet Jonathan Schröter Jordan McConnon +Jose Drowne Jose Loyola Josep Sans Joseph Nwabueze @@ -233,6 +234,7 @@ Steven Hugg Szymon Gizler Sören Tempel Teng Huang +Thomas Aldrian Thomas Dybdahl Ahle Tim Hutt Tim Snyder diff --git a/docs/gen/ex_ASSIGNEQEXPR_faulty.rst b/docs/gen/ex_ASSIGNEQEXPR_faulty.rst index 7fd7546e0..af5f59067 100644 --- a/docs/gen/ex_ASSIGNEQEXPR_faulty.rst +++ b/docs/gen/ex_ASSIGNEQEXPR_faulty.rst @@ -1,9 +1,8 @@ .. comment: generated by t_lint_assigneqexpr_bad .. code-block:: sv :linenos: - :emphasize-lines: 3 - assign d_o = // Note = not == below - ( - c_o = 1 // <--- Warning: ASSIGNEQEXPR - ) ? 1 : ( + output logic c_o, + output logic d_o + ); + assign c_o = (a_i != 0) ? 1 : 0; diff --git a/docs/gen/ex_FUNCTIMECTL_faulty.rst b/docs/gen/ex_FUNCTIMECTL_faulty.rst index 5c2e70053..42e21e889 100644 --- a/docs/gen/ex_FUNCTIMECTL_faulty.rst +++ b/docs/gen/ex_FUNCTIMECTL_faulty.rst @@ -4,4 +4,4 @@ :emphasize-lines: 2 function void calls_timing_ctl; - @e; // <--- Bad IEEE 1800-2023 13.4 time-controlling + @e; // <--- Bad IEEE 1800-2023 13.4 time-controlling diff --git a/docs/guide/connecting.rst b/docs/guide/connecting.rst index dab359147..c9d7f7578 100644 --- a/docs/guide/connecting.rst +++ b/docs/guide/connecting.rst @@ -502,16 +502,16 @@ described above is just a wrapper which calls these two functions. 3. If using delays and :vlopt:`--timing`, there are two additional methods the user should call: - * ``designp->eventsPending()``, which returns ``true`` if there are - any delayed events pending, + * ``designp->eventsPending()``, which returns ``true`` if there are any + delayed events pending, * ``designp->nextTimeSlot()``, which returns the simulation time of the next delayed event. This method can only be called if ``designp->eventsPending()`` returned ``true``. Call ``eventsPending()`` to check if you should continue with the simulation, and then ``nextTimeSlot()`` to move simulation time forward. -:vlopt:`--main` can be used with :vlopt:`--timing` to generate a basic example -of a timing-enabled eval loop. +:vlopt:`--main` can be used with :vlopt:`--timing` to generate a basic +example of a timing-enabled eval loop. When ``eval()`` (or ``eval_step()``) is called Verilator looks for changes in clock signals and evaluates related sequential always blocks, such as diff --git a/docs/guide/contributors.rst b/docs/guide/contributors.rst index dd5676cce..a782eb120 100644 --- a/docs/guide/contributors.rst +++ b/docs/guide/contributors.rst @@ -29,9 +29,10 @@ Alliance `_, and `Antmicro Ltd Previous major corporate sponsors of Verilator, by providing significant contributions of time or funds include: Antmicro Ltd., Atmel Corporation, Compaq Corporation, Digital Equipment Corporation, Embecosm Ltd., Fractile -Ltd., Hicamp Systems, Intel Corporation, Marvell Inc., Mindspeed Technologies -Inc., MicroTune Inc., picoChip Designs Ltd., Sun Microsystems Inc., Nauticus -Networks Inc., SiCortex Inc, Shunyao CAD, and Western Digital Inc. +Ltd., Hicamp Systems, Intel Corporation, Marvell Inc., Mindspeed +Technologies Inc., MicroTune Inc., picoChip Designs Ltd., Sun Microsystems +Inc., Nauticus Networks Inc., SiCortex Inc, Shunyao CAD, and Western +Digital Inc. The contributors of major functionality are: Jeremy Bennett, Krzysztof Bieganski, Byron Bradley, Lane Brooks, John Coiner, Duane Galbi, Arkadiusz diff --git a/docs/guide/example_binary.rst b/docs/guide/example_binary.rst index c8d656b52..6633d46d1 100644 --- a/docs/guide/example_binary.rst +++ b/docs/guide/example_binary.rst @@ -39,8 +39,7 @@ Breaking this command down: #. :vlopt:`-j` `0` to Verilate using use as many CPU threads as the machine has. -#. :vlopt:`-Wall` so Verilator has stronger lint warnings - enabled. +#. :vlopt:`-Wall` so Verilator has stronger lint warnings enabled. #. An finally, :command:`our.v`, which is our SystemVerilog design file. diff --git a/docs/guide/example_cc.rst b/docs/guide/example_cc.rst index 7278d7270..c01f294d5 100644 --- a/docs/guide/example_cc.rst +++ b/docs/guide/example_cc.rst @@ -60,8 +60,7 @@ Breaking this command down: #. :vlopt:`-j 0 <-j>` to Verilate using use as many CPU threads as the machine has. -#. :vlopt:`-Wall` so Verilator has stronger lint warnings - enabled. +#. :vlopt:`-Wall` so Verilator has stronger lint warnings enabled. #. And finally, :command:`our.v` which is our SystemVerilog design file. diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst index f748f6ea1..11add271f 100644 --- a/docs/guide/exe_verilator.rst +++ b/docs/guide/exe_verilator.rst @@ -867,6 +867,29 @@ Summary: compatibility and is not recommended usage as this is not supported by some third-party tools. +.. option:: --inline-cfuncs + + Inline small CFunc calls directly into their callers when the function + has at most nodes. This reduces function call overhead when + :vlopt:`--output-split-cfuncs` places functions in separate compilation + units that the C++ compiler cannot inline. + + Set to 0 to disable this optimization. The default is 20. + + This optimization is automatically disabled when :vlopt:`--prof-cfuncs` + or :vlopt:`--trace` is used. + +.. option:: --inline-cfuncs-product + + Tune the inlining of CFunc calls for larger functions. When a function + is too large to always inline (exceeds :vlopt:`--inline-cfuncs` threshold), + it may still be inlined if the function size multiplied by the number of + call sites is at most . + + This allows functions that are called only once or twice to be inlined + even if they exceed the small function threshold. Set to 0 to only inline + functions below the :vlopt:`--inline-cfuncs` threshold. The default is 200. + .. option:: --inline-mult Tune the inlining of modules. The default value of 2000 specifies that @@ -2495,8 +2518,8 @@ The grammar of control commands is as follows: converted into ``begin``/``end`` blocks. Similar to :option:`/*verilator&32;timing_on*/`, - :option:`/*verilator&32;timing_off*/` metacomments, but interpreted - independtly. If either a control file, or metacommets disable timing + :option:`/*verilator&32;timing_off*/` meta-comments, but interpreted + independently. If either a control file, or meta-comments disable timing constructs, they will be disabled. .. t_dist_docs_style ignore tracing_on diff --git a/docs/guide/extensions.rst b/docs/guide/extensions.rst index 79d4d50fa..e4d003c2a 100644 --- a/docs/guide/extensions.rst +++ b/docs/guide/extensions.rst @@ -1,9 +1,9 @@ .. Copyright 2003-2025 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -===================== - Language Extensions -===================== +=================== +Language Extensions +=================== The following additional constructs are the extensions Verilator supports on top of standard Verilog code. Using these features outside of comments diff --git a/docs/guide/faq.rst b/docs/guide/faq.rst index dd56b20da..b806ca180 100644 --- a/docs/guide/faq.rst +++ b/docs/guide/faq.rst @@ -403,8 +403,8 @@ How do I get faster build times? environment variable to override this. Also see the :vlopt:`--output-split` option and :ref: `Profiling ccache efficiency`. -* To reduce the compile time of classes that use a Verilated module (e.g., a - top CPP file) you may wish to add a +* To reduce the compile time of classes that use a Verilated module (e.g., + a top CPP file) you may wish to add a :option:`/*verilator&32;no_inline_module*/` metacomment to your top-level module. This will decrease the amount of code in the model's Verilated class, improving compile times of any instantiating top-level C++ code, diff --git a/docs/guide/install.rst b/docs/guide/install.rst index b7a1c1297..b9ac0ad94 100644 --- a/docs/guide/install.rst +++ b/docs/guide/install.rst @@ -163,10 +163,10 @@ packages (see internals.rst), and a Python virtual environment: cpan install Pod::Perldoc The Python virtual environment is only required for running the whole test -suite, and for additional development steps like linting and formatting. It is -not required for building Verilator itself. To install the python virtual -environment and all dependencies automatically, run the following once, after -``configure``: +suite, and for additional development steps like linting and formatting. It +is not required for building Verilator itself. To install the python +virtual environment and all dependencies automatically, run the following +once, after ``configure``: .. code-block:: bash diff --git a/docs/guide/languages.rst b/docs/guide/languages.rst index a5da686f2..05dc1f8ed 100644 --- a/docs/guide/languages.rst +++ b/docs/guide/languages.rst @@ -143,8 +143,8 @@ error, except: * delay statements - they are ignored (as they are in synthesis), though they do issue a :option:`STMTDLY` warning, -* intra-assignment timing controls - they are ignored, though they do issue an - :option:`ASSIGNDLY` warning, +* intra-assignment timing controls - they are ignored, though they do issue + an :option:`ASSIGNDLY` warning, * net delays - they are ignored, * event controls at the top of the procedure, diff --git a/docs/guide/verilating.rst b/docs/guide/verilating.rst index 7e79d3641..25b5e966f 100644 --- a/docs/guide/verilating.rst +++ b/docs/guide/verilating.rst @@ -22,8 +22,8 @@ Verilator may be used in five major ways: that may be used to feed into other user-designed tools. * With the :vlopt:`-E` option, Verilator will preprocess the code according - to IEEE preprocessing rules and write the output to standard out. This - is useful to feed other tools and to debug how "\`define" statements are + to IEEE preprocessing rules and write the output to standard out. This is + useful to feed other tools and to debug how "\`define" statements are expanded. @@ -80,8 +80,9 @@ Verilator first reads all files provided on the command line and :vlopt:`-f` files, and parses all modules within. Each module is assigned to the most recent library specified with :vlopt:`-work`, thus `-work liba a.v -work libb b.v` will assign modules in `a.v` to `liba` and modules in -`b.v` to `libb`. In the absence of a `-work` mapping, each module is optionally -assigned to a library based on mappings provided by :vlopt:`-libmap`. +`b.v` to `libb`. In the absence of a `-work` mapping, each module is +optionally assigned to a library based on mappings provided by +:vlopt:`-libmap`. If a module is not defined from a file on the command-line, Verilator attempts to find a filename constructed from the module name using diff --git a/docs/guide/warnings.rst b/docs/guide/warnings.rst index f231e0894..eeec260b5 100644 --- a/docs/guide/warnings.rst +++ b/docs/guide/warnings.rst @@ -1,9 +1,9 @@ .. Copyright 2003-2025 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -===================== - Errors and Warnings -===================== +=================== +Errors and Warnings +=================== .. _disabling warnings: @@ -46,8 +46,8 @@ Warnings may be disabled in multiple ways: lint_off -rule UNSIGNED -file "*/example.v" -lines 1 Metacomments and control file directives do not interact. If a warning is -disabled by either metacomments, or a directive in a control file, it will not -be emitted. +disabled by either metacomments, or a directive in a control file, it will +not be emitted. Error And Warning Format ======================== diff --git a/docs/internals.rst b/docs/internals.rst index cf5325f4b..df592e8ac 100644 --- a/docs/internals.rst +++ b/docs/internals.rst @@ -1,8 +1,8 @@ |Logo| -===================== - Verilator Internals -===================== +=================== +Verilator Internals +=================== .. contents:: :depth: 3 @@ -1771,8 +1771,8 @@ files that were read, filtered by preprocessing. This file can be fed back into Verilator, replacing on the command line all of the previous input files, to enable simplification of test cases. This file also contains most command line arguments Verilator was invoked as `// verilator fargs`` -metacomments, with and can be parsed by ``-f`. So to reproduce the run that -created the file, run: +metacomments, with and can be parsed by `\`-f`. So to reproduce the run +that created the file, run: :: verilator -f __inputs.vpp __inputs.vpp @@ -2095,11 +2095,18 @@ To print a node: ``src/.gdbinit`` and ``src/.gdbinit.py`` define handy utilities for working with JSON AST dumps. For example: -* ``jstash nodep`` - Perform a JSON AST dump and save it into GDB value history (e.g. ``$1``) -* ``jtree nodep`` - Perform a JSON AST dump and pretty print it using ``astsee_verilator``. -* ``jtree $1`` - Pretty print a dump that was previously saved by ``jstash``. -* ``jtree nodep -d '.file, .timeunit'`` - Perform a JSON AST dump, filter out some fields and pretty print it. -* ``jtree 0x55555613dca0`` - Pretty print using address literal (rather than actual pointer). +* ``jstash nodep`` - Perform a JSON AST dump and save it into GDB value + history (e.g. ``$1``) + +* ``jtree nodep`` - Perform a JSON AST dump and pretty print it using + ``astsee_verilator``. +* ``jtree $1`` - Pretty print a dump that was previously saved by + ``jstash``. +* ``jtree nodep -d '.file, .timeunit'`` - Perform a JSON AST dump, filter + out some fields and pretty print it. + +* ``jtree 0x55555613dca0`` - Pretty print using address literal (rather + than actual pointer). * ``jtree $1 nodep`` - Diff ``nodep`` against an older dump. A detailed description of ``jstash`` and ``jtree`` can be displayed using diff --git a/docs/spelling.txt b/docs/spelling.txt index a2c00de64..7a68d978e 100644 --- a/docs/spelling.txt +++ b/docs/spelling.txt @@ -4,6 +4,8 @@ Accellera Affe Aleksander Alexandre +Almis +Amal Ami Amir Anastasiadis @@ -13,6 +15,7 @@ Antmicro Antonin Antwerpen Arasanipalai +Araweelo Arjen Arshid Asciidoc @@ -986,6 +989,7 @@ qrqiuren radix randc randcase +randmode randsequence randstate raphmaster diff --git a/examples/json_py/sub.v b/examples/json_py/sub.v index 94037d4c4..19a635b3e 100644 --- a/examples/json_py/sub.v +++ b/examples/json_py/sub.v @@ -5,12 +5,12 @@ // SPDX-License-Identifier: CC0-1.0 // ====================================================================== -module sub - #(parameter type TYPE_t = logic) - ( - input TYPE_t in, - output TYPE_t out - ); +module sub #( + parameter type TYPE_t = logic +) ( + input TYPE_t in, + output TYPE_t out +); // Some simple logic always_comb out = ~in; diff --git a/examples/json_py/top.v b/examples/json_py/top.v index 1106464f1..38a3be52b 100644 --- a/examples/json_py/top.v +++ b/examples/json_py/top.v @@ -5,29 +5,37 @@ // SPDX-License-Identifier: CC0-1.0 // ====================================================================== -module top - ( - input clk, - input fastclk, - input reset_l, +module top ( + input clk, + input fastclk, + input reset_l, - output wire [1:0] out_small, - output wire [39:0] out_quad, - output wire [69:0] out_wide, - input [1:0] in_small, - input [39:0] in_quad, - input [69:0] in_wide - ); + output wire [1:0] out_small, + output wire [39:0] out_quad, + output wire [69:0] out_wide, + input [1:0] in_small, + input [39:0] in_quad, + input [69:0] in_wide +); - sub #(.TYPE_t(logic [1:0])) sub_small - (.in(in_small), - .out(out_small)); + sub #( + .TYPE_t(logic [1:0]) + ) sub_small ( + .in(in_small), + .out(out_small) + ); - sub #(.TYPE_t(logic [39:0])) sub_quad - (.in(in_quad), - .out(out_quad)); + sub #( + .TYPE_t(logic [39:0]) + ) sub_quad ( + .in(in_quad), + .out(out_quad) + ); - sub #(.TYPE_t(logic [69:0])) sub_wide - (.in(in_wide), - .out(out_wide)); + sub #( + .TYPE_t(logic [69:0]) + ) sub_wide ( + .in(in_wide), + .out(out_wide) + ); endmodule diff --git a/examples/make_protect_lib/secret_impl.v b/examples/make_protect_lib/secret_impl.v index f2dc01b09..3f8fadf66 100644 --- a/examples/make_protect_lib/secret_impl.v +++ b/examples/make_protect_lib/secret_impl.v @@ -7,13 +7,13 @@ // This module will be used as libsecret.a or libsecret.so without // exposing the source. -module secret_impl - ( - input [31:0] a, - input [31:0] b, - output logic [31:0] x, - input clk, - input reset_l); +module secret_impl ( + input [31:0] a, + input [31:0] b, + output logic [31:0] x, + input clk, + input reset_l +); logic [31:0] accum_q; logic [31:0] secret_value; @@ -27,10 +27,8 @@ module secret_impl end else begin accum_q <= accum_q + a; - if (accum_q > 10) - x <= b; - else - x <= a + b + secret_value; + if (accum_q > 10) x <= b; + else x <= a + b + secret_value; end end diff --git a/examples/make_protect_lib/top.v b/examples/make_protect_lib/top.v index c80c1b2bb..c8989fe42 100644 --- a/examples/make_protect_lib/top.v +++ b/examples/make_protect_lib/top.v @@ -6,7 +6,9 @@ // See also https://verilator.org/guide/latest/examples.html" -module top (input clk); +module top ( + input clk +); int cyc; logic reset_l; @@ -14,7 +16,13 @@ module top (input clk); logic [31:0] b; logic [31:0] x; - verilated_secret secret (.a, .b, .x, .clk, .reset_l); + verilated_secret secret ( + .a, + .b, + .x, + .clk, + .reset_l + ); always @(posedge clk) begin $display("[%0t] cyc=%0d a=%0d b=%0d x=%0d", $time, cyc, a, b, x); diff --git a/examples/make_tracing_c/sub.v b/examples/make_tracing_c/sub.v index ad0ad3765..473139c07 100644 --- a/examples/make_tracing_c/sub.v +++ b/examples/make_tracing_c/sub.v @@ -5,11 +5,10 @@ // SPDX-License-Identifier: CC0-1.0 // ====================================================================== -module sub - ( - input clk, - input reset_l - ); +module sub ( + input clk, + input reset_l +); // Example counter/flop reg [31:0] count_c; diff --git a/examples/make_tracing_c/top.v b/examples/make_tracing_c/top.v index c3b140cb2..44393f9d2 100644 --- a/examples/make_tracing_c/top.v +++ b/examples/make_tracing_c/top.v @@ -8,24 +8,23 @@ // This is intended to be a complex example of several features, please also // see the simpler examples/make_hello_c. -module top - ( - // Declare some signals so we can see how I/O works - input clk, - input reset_l, +module top ( + // Declare some signals so we can see how I/O works + input clk, + input reset_l, - output wire [1:0] out_small, - output wire [39:0] out_quad, - output wire [69:0] out_wide, - input [1:0] in_small, - input [39:0] in_quad, - input [69:0] in_wide - ); + output wire [1:0] out_small, + output wire [39:0] out_quad, + output wire [69:0] out_wide, + input [1:0] in_small, + input [39:0] in_quad, + input [69:0] in_wide +); // Connect up the outputs, using some trivial logic assign out_small = ~reset_l ? '0 : (in_small + 2'b1); - assign out_quad = ~reset_l ? '0 : (in_quad + 40'b1); - assign out_wide = ~reset_l ? '0 : (in_wide + 70'b1); + assign out_quad = ~reset_l ? '0 : (in_quad + 40'b1); + assign out_wide = ~reset_l ? '0 : (in_wide + 70'b1); // And an example sub module. The submodule will print stuff. sub sub (/*AUTOINST*/ diff --git a/examples/make_tracing_sc/sub.v b/examples/make_tracing_sc/sub.v index fd84e6177..98328fbcc 100644 --- a/examples/make_tracing_sc/sub.v +++ b/examples/make_tracing_sc/sub.v @@ -5,12 +5,11 @@ // SPDX-License-Identifier: CC0-1.0 // ====================================================================== -module sub - ( - input clk, - input fastclk, - input reset_l - ); +module sub ( + input clk, + input fastclk, + input reset_l +); // Example counter/flop reg [31:0] count_f; diff --git a/examples/make_tracing_sc/top.v b/examples/make_tracing_sc/top.v index 8543934d2..8e5c42a40 100644 --- a/examples/make_tracing_sc/top.v +++ b/examples/make_tracing_sc/top.v @@ -8,25 +8,24 @@ // This is intended to be a complex example of several features, please also // see the simpler examples/make_hello_c. -module top - ( - // Declare some signals so we can see how I/O works - input clk, - input fastclk, - input reset_l, +module top ( + // Declare some signals so we can see how I/O works + input clk, + input fastclk, + input reset_l, - output wire [1:0] out_small, - output wire [39:0] out_quad, - output wire [69:0] out_wide, - input [1:0] in_small, - input [39:0] in_quad, - input [69:0] in_wide - ); + output wire [1:0] out_small, + output wire [39:0] out_quad, + output wire [69:0] out_wide, + input [1:0] in_small, + input [39:0] in_quad, + input [69:0] in_wide +); // Connect up the outputs, using some trivial logic assign out_small = ~reset_l ? '0 : (in_small + 2'b1); - assign out_quad = ~reset_l ? '0 : (in_quad + 40'b1); - assign out_wide = ~reset_l ? '0 : (in_wide + 70'b1); + assign out_quad = ~reset_l ? '0 : (in_quad + 40'b1); + assign out_wide = ~reset_l ? '0 : (in_wide + 70'b1); // And an example sub module. The submodule will print stuff. sub sub (/*AUTOINST*/ diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index a08cb45c2..487980e40 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -114,6 +114,7 @@ set(HEADERS V3Hasher.h V3HierBlock.h V3Inline.h + V3InlineCFuncs.h V3Inst.h V3InstrCount.h V3Interface.h @@ -287,6 +288,7 @@ set(COMMON_SOURCES V3Hasher.cpp V3HierBlock.cpp V3Inline.cpp + V3InlineCFuncs.cpp V3Inst.cpp V3InstrCount.cpp V3Interface.cpp diff --git a/src/Makefile_obj.in b/src/Makefile_obj.in index 74696c1b1..1bc6cc3af 100644 --- a/src/Makefile_obj.in +++ b/src/Makefile_obj.in @@ -284,6 +284,7 @@ RAW_OBJS_PCH_ASTNOMT = \ V3Gate.o \ V3HierBlock.o \ V3Inline.o \ + V3InlineCFuncs.o \ V3Inst.o \ V3InstrCount.o \ V3Interface.o \ diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h index 96ae9ee88..1009c3234 100644 --- a/src/V3AstNodeOther.h +++ b/src/V3AstNodeOther.h @@ -1203,6 +1203,7 @@ class AstModportVarRef final : public AstNode { // A input/output/etc variable referenced under a modport // The storage for the variable itself is inside the interface, thus this is a reference // PARENT: AstModport + // @astgen op1 := exprp : Optional[AstNodeExpr] // // @astgen ptr := m_varp : Optional[AstVar] // Link to the actual Var string m_name; // Name of the variable referenced @@ -1212,6 +1213,13 @@ public: : ASTGEN_SUPER_ModportVarRef(fl) , m_name{name} , m_direction{direction} {} + AstModportVarRef(FileLine* fl, const string& name, AstNodeExpr* exprp, + VDirection::en direction) + : ASTGEN_SUPER_ModportVarRef(fl) + , m_name{name} + , m_direction{direction} { + this->exprp(exprp); + }; ASTGEN_MEMBERS_AstModportVarRef; void dump(std::ostream& str) const override; void dumpJson(std::ostream& str) const override; diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp index 6492fed29..6396a6f8a 100644 --- a/src/V3AstNodes.cpp +++ b/src/V3AstNodes.cpp @@ -2378,6 +2378,7 @@ void AstNodeDType::dump(std::ostream& str) const { } void AstNodeDType::dumpJson(std::ostream& str) const { dumpJsonBoolFunc(str, generic); + if (isSigned() && !isDouble()) dumpJsonBool(str, "signed", 1); dumpJsonGen(str); } void AstNodeDType::dumpSmall(std::ostream& str) const VL_MT_STABLE { diff --git a/src/V3Fork.cpp b/src/V3Fork.cpp index 53e8cac0c..3c494b963 100644 --- a/src/V3Fork.cpp +++ b/src/V3Fork.cpp @@ -673,8 +673,8 @@ class ForkVisitor final : public VNVisitor { if (nodep->access().isWriteOrRW() && (!nodep->isClassHandleValue() || nodep->user2())) { nodep->v3warn( E_LIFETIME, - "Invalid reference: Process might outlive variable `" - << varp->name() << "`.\n" + "Invalid reference: Process might outlive variable " + << varp->prettyNameQ() << ".\n" << varp->warnMore() << "... Suggest use it as read-only to initialize a local copy at the " "beginning of the process, or declare it as static. It is also " diff --git a/src/V3InlineCFuncs.cpp b/src/V3InlineCFuncs.cpp new file mode 100644 index 000000000..95927d19e --- /dev/null +++ b/src/V3InlineCFuncs.cpp @@ -0,0 +1,269 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// DESCRIPTION: Verilator: Inline small CFuncs into their callers +// +// Code available from: https://verilator.org +// +//************************************************************************* +// +// Copyright 2003-2025 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//************************************************************************* +// V3InlineCFuncs's Transformations: +// +// For each CCall to a small CFunc: +// - Check if function is eligible for inlining (small enough, same scope) +// - Clone local variables with unique names to avoid collisions +// - Replace CCall with cloned function body statements +// +// Two tunables control inlining: +// --inline-cfuncs : Always inline if size <= n (default 20) +// --inline-cfuncs-product : Also inline if size * call_count <= n (default 200) +// +//************************************************************************* + +#include "V3PchAstNoMT.h" // VL_MT_DISABLED_CODE_UNIT + +#include "V3InlineCFuncs.h" + +#include "V3AstUserAllocator.h" +#include "V3Stats.h" + +#include +#include + +VL_DEFINE_DEBUG_FUNCTIONS; + +//###################################################################### +// Helper visitor to check if a CFunc contains C statements +// Uses clearOptimizable pattern for debugging + +class CFuncInlineCheckVisitor final : public VNVisitorConst { + // STATE + bool m_optimizable = true; // True if function can be inlined + string m_whyNot; // Reason why not optimizable + AstNode* m_whyNotNodep = nullptr; // Node that caused non-optimizable + + // METHODS + void clearOptimizable(AstNode* nodep, const string& why) { + if (m_optimizable) { + m_optimizable = false; + m_whyNot = why; + m_whyNotNodep = nodep; + UINFO(9, "CFunc not inlineable: " << why); + if (nodep) UINFO(9, ": " << nodep); + UINFO(9, endl); + } + } + + // VISITORS + void visit(AstCStmt* nodep) override { clearOptimizable(nodep, "contains AstCStmt"); } + void visit(AstCExpr* nodep) override { clearOptimizable(nodep, "contains AstCExpr"); } + void visit(AstCStmtUser* nodep) override { clearOptimizable(nodep, "contains AstCStmtUser"); } + void visit(AstCExprUser* nodep) override { clearOptimizable(nodep, "contains AstCExprUser"); } + void visit(AstNode* nodep) override { iterateChildrenConst(nodep); } + +public: + // CONSTRUCTORS + explicit CFuncInlineCheckVisitor(AstCFunc* cfuncp) { iterateConst(cfuncp); } + + // ACCESSORS + bool optimizable() const { return m_optimizable; } + string whyNot() const { return m_whyNot; } + AstNode* whyNotNodep() const { return m_whyNotNodep; } +}; + +//###################################################################### + +class InlineCFuncsVisitor final : public VNVisitor { + // NODE STATE + // AstCFunc::user1() -> vector of AstCCall* pointing to this function + // AstCFunc::user2() -> bool: true if checked for C statements + // AstCFunc::user3() -> bool: true if contains C statements (not inlineable) + const VNUser1InUse m_user1InUse; + const VNUser2InUse m_user2InUse; + const VNUser3InUse m_user3InUse; + AstUser1Allocator> m_callSites; + + // STATE + VDouble0 m_statInlined; // Statistic tracking + const int m_threshold1; // Size threshold: always inline if size <= this + const int m_threshold2; // Product threshold: inline if size * calls <= this + AstCFunc* m_callerFuncp = nullptr; // Current caller function + // Tuples of (StmtExpr to replace, CFunc to inline from, caller func for vars) + std::vector> m_toInline; + + // METHODS + + // Check if a function contains any $c() calls (user or internal) + // Results are cached in user2/user3 for efficiency + bool containsCStatements(AstCFunc* cfuncp) { + if (!cfuncp->user2()) { + // Not yet checked - run the check visitor + cfuncp->user2(true); // Mark as checked + const CFuncInlineCheckVisitor checker{cfuncp}; + cfuncp->user3(!checker.optimizable()); // Store result (true = contains C stmts) + } + return cfuncp->user3(); + } + + // Check if a function is eligible for inlining into caller + bool isInlineable(AstCFunc* callerp, AstCFunc* cfuncp) { + // Must be in the same scope (same class) to access the same members + if (callerp->scopep() != cfuncp->scopep()) return false; + + // Check for $c() calls that might use 'this' + if (containsCStatements(cfuncp)) return false; + + // Check it's a void function (not a coroutine) + if (cfuncp->rtnTypeVoid() != "void") return false; + + // Don't inline functions marked dontCombine (e.g. trace, entryPoint) + if (cfuncp->dontCombine()) return false; + + // Don't inline entry point functions + if (cfuncp->entryPoint()) return false; + + // Must have statements to inline + if (!cfuncp->stmtsp()) return false; + + // Check size thresholds + const size_t funcSize = cfuncp->nodeCount(); + + // Always inline if small enough + if (funcSize <= static_cast(m_threshold1)) return true; + + // Also inline if size * call_count is reasonable + const size_t callCount = m_callSites(cfuncp).size(); + if (callCount > 0 && funcSize * callCount <= static_cast(m_threshold2)) { + return true; + } + + return false; + } + + // VISITORS + void visit(AstCCall* nodep) override { + iterateChildren(nodep); + + AstCFunc* const cfuncp = nodep->funcp(); + if (!cfuncp) return; + + // Track call site for call counting + m_callSites(cfuncp).emplace_back(nodep); + } + + void visit(AstCFunc* nodep) override { + VL_RESTORER(m_callerFuncp); + m_callerFuncp = nodep; + iterateChildren(nodep); + } + + void visit(AstNodeModule* nodep) override { + // Process per module for better cache behavior + m_toInline.clear(); + + // Phase 1: Collect call sites within this module + iterateChildren(nodep); + + // Phase 2: Determine which calls to inline + collectInlineCandidates(nodep); + + // Phase 3: Perform inlining for this module + doInlining(); + } + + void visit(AstNode* nodep) override { iterateChildren(nodep); } + + // Collect calls that should be inlined within this module + void collectInlineCandidates(AstNodeModule* modp) { + for (AstNode* stmtp = modp->stmtsp(); stmtp; stmtp = stmtp->nextp()) { + AstCFunc* const callerp = VN_CAST(stmtp, CFunc); + if (!callerp) continue; + + callerp->foreach([&](AstCCall* callp) { + AstCFunc* const cfuncp = callp->funcp(); + if (!cfuncp) return; + if (!isInlineable(callerp, cfuncp)) return; + + // Walk up to find the containing StmtExpr + AstNode* stmtNodep = callp; + while (stmtNodep && !VN_IS(stmtNodep, StmtExpr) && !VN_IS(stmtNodep, CFunc)) { + stmtNodep = stmtNodep->backp(); + } + + AstStmtExpr* const stmtExprp = VN_CAST(stmtNodep, StmtExpr); + if (!stmtExprp) return; + + m_toInline.emplace_back(stmtExprp, cfuncp, callerp); + }); + } + } + + // Perform the actual inlining after iteration is complete + void doInlining() { + for (const auto& tuple : m_toInline) { + AstStmtExpr* const stmtExprp = std::get<0>(tuple); + AstCFunc* const cfuncp = std::get<1>(tuple); + AstCFunc* const callerp = std::get<2>(tuple); + + UINFO(6, "Inlining CFunc " << cfuncp->name() << " into " << callerp->name() << endl); + ++m_statInlined; + + // Clone local variables with unique names to avoid collisions + std::map varMap; + for (AstVar* varp = cfuncp->varsp(); varp; varp = VN_AS(varp->nextp(), Var)) { + const string newName = "__Vinline_" + cfuncp->name() + "_" + varp->name(); + AstVar* const newVarp = varp->cloneTree(false); + newVarp->name(newName); + callerp->addVarsp(newVarp); + varMap[varp] = newVarp; + } + + // Clone the function body + AstNode* const bodyp = cfuncp->stmtsp()->cloneTree(true); + + // Retarget variable references to the cloned variables + // Must iterate all sibling statements, not just the first + if (!varMap.empty()) { + for (AstNode* stmtp = bodyp; stmtp; stmtp = stmtp->nextp()) { + stmtp->foreach([&](AstVarRef* refp) { + auto it = varMap.find(refp->varp()); + if (it != varMap.end()) refp->varp(it->second); + }); + } + } + + // Replace the statement with the inlined body + stmtExprp->addNextHere(bodyp); + VL_DO_DANGLING(stmtExprp->unlinkFrBack()->deleteTree(), stmtExprp); + } + } + +public: + // CONSTRUCTORS + explicit InlineCFuncsVisitor(AstNetlist* nodep) + : m_threshold1{v3Global.opt.inlineCFuncs()} + , m_threshold2{v3Global.opt.inlineCFuncsProduct()} { + // Don't inline when profiling or tracing + if (v3Global.opt.profCFuncs() || v3Global.opt.trace()) return; + // Process modules one at a time for better cache behavior + iterateAndNextNull(nodep->modulesp()); + } + ~InlineCFuncsVisitor() override { + V3Stats::addStat("Optimizations, Inlined CFuncs", m_statInlined); + } +}; + +//###################################################################### +// InlineCFuncs class functions + +void V3InlineCFuncs::inlineAll(AstNetlist* nodep) { + UINFO(2, __FUNCTION__ << ":"); + { InlineCFuncsVisitor{nodep}; } // Destruct before checking + V3Global::dumpCheckGlobalTree("inlinecfuncs", 0, dumpTreeEitherLevel() >= 6); +} diff --git a/src/V3InlineCFuncs.h b/src/V3InlineCFuncs.h new file mode 100644 index 000000000..07c900fd8 --- /dev/null +++ b/src/V3InlineCFuncs.h @@ -0,0 +1,30 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// DESCRIPTION: Verilator: Inline small CFuncs into their callers +// +// Code available from: https://verilator.org +// +//************************************************************************* +// +// Copyright 2003-2025 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//************************************************************************* + +#ifndef VERILATOR_V3INLINECFUNCS_H_ +#define VERILATOR_V3INLINECFUNCS_H_ + +#include "config_build.h" +#include "verilatedos.h" + +class AstNetlist; + +class V3InlineCFuncs final { +public: + static void inlineAll(AstNetlist* nodep) VL_MT_DISABLED; +}; + +#endif // Guard diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index 1ce93ff9f..a3c62b46d 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -2529,7 +2529,13 @@ class LinkDotIfaceVisitor final : public VNVisitor { void visit(AstModportVarRef* nodep) override { // IfaceVisitor:: UINFO(5, " fiv: " << nodep); iterateChildren(nodep); - VSymEnt* const symp = m_curSymp->findIdFallback(nodep->name()); + VSymEnt* symp = nullptr; + if (nodep->exprp()) { + nodep->v3warn(E_UNSUPPORTED, + "Unsupported: Modport expressions (IEEE 1800-2023 25.5.4)"); + } else { + symp = m_curSymp->findIdFallback(nodep->name()); + } if (!symp) { nodep->v3error("Modport item not found: " << nodep->prettyNameQ()); } else if (AstVar* const varp = VN_CAST(symp->nodep(), Var)) { diff --git a/src/V3Options.cpp b/src/V3Options.cpp index 306bced64..9e775a96d 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -1528,6 +1528,8 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, }).notForRerun(); DECL_OPTION("-if-depth", Set, &m_ifDepth); DECL_OPTION("-ignc", OnOff, &m_ignc).undocumented(); + DECL_OPTION("-inline-cfuncs", Set, &m_inlineCFuncs); + DECL_OPTION("-inline-cfuncs-product", Set, &m_inlineCFuncsProduct); DECL_OPTION("-inline-mult", Set, &m_inlineMult); DECL_OPTION("-instr-count-dpi", CbVal, [this, fl](int val) { m_instrCountDpi = val; diff --git a/src/V3Options.h b/src/V3Options.h index 1af02e49c..13ebcf726 100644 --- a/src/V3Options.h +++ b/src/V3Options.h @@ -319,6 +319,8 @@ private: int m_hierChild = 0; // main switch: --hierarchical-child int m_hierThreads = 0; // main switch: --hierarchical-threads int m_ifDepth = 0; // main switch: --if-depth + int m_inlineCFuncs = 20; // main switch: --inline-cfuncs + int m_inlineCFuncsProduct = 200; // main switch: --inline-cfuncs-product int m_inlineMult = 2000; // main switch: --inline-mult int m_instrCountDpi = 200; // main switch: --instr-count-dpi bool m_jsonEditNums = true; // main switch: --no-json-edit-nums @@ -595,6 +597,8 @@ public: int expandLimit() const { return m_expandLimit; } int gateStmts() const { return m_gateStmts; } int ifDepth() const { return m_ifDepth; } + int inlineCFuncs() const { return m_inlineCFuncs; } + int inlineCFuncsProduct() const { return m_inlineCFuncsProduct; } int inlineMult() const { return m_inlineMult; } int instrCountDpi() const { return m_instrCountDpi; } int localizeMaxSize() const { return m_localizeMaxSize; } diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp index 624176bc9..556f5abd0 100644 --- a/src/V3Randomize.cpp +++ b/src/V3Randomize.cpp @@ -2634,6 +2634,7 @@ class RandomizeVisitor final : public VNVisitor { const std::string name = "__Vrandcase" + cvtToStr(m_randCaseNum++); AstVar* const randVarp = new AstVar{fl, VVarType::BLOCKTEMP, name, sumDTypep}; randVarp->noSubst(true); + randVarp->lifetime(VLifetime::AUTOMATIC_EXPLICIT); if (m_ftaskp) randVarp->funcLocal(true); AstNodeExpr* sump = new AstConst{fl, AstConst::WidthedValue{}, 64, 0}; AstNodeIf* const firstIfsp diff --git a/src/V3SenExprBuilder.h b/src/V3SenExprBuilder.h index ddedc20ed..ddbfbbba9 100644 --- a/src/V3SenExprBuilder.h +++ b/src/V3SenExprBuilder.h @@ -126,9 +126,12 @@ private: // Add post update if it does not exist yet if (m_hasPostUpdate.emplace(*exprp).second) { if (!isSupportedDType(exprp->dtypep())) { - exprp->v3warn(E_UNSUPPORTED, - "Unsupported: Cannot detect changes on expression of complex type" - " (see combinational cycles reported by UNOPTFLAT)"); + exprp->v3warn( + E_UNSUPPORTED, + "Unsupported: Cannot detect changes on expression of complex type " + << exprp->dtypep()->prettyDTypeNameQ() << "\n" + << exprp->warnMore() + << "... May be caused by combinational cycles reported with UNOPTFLAT"); return prevp; } diff --git a/src/Verilator.cpp b/src/Verilator.cpp index 363a50b86..3043c0c71 100644 --- a/src/Verilator.cpp +++ b/src/Verilator.cpp @@ -63,6 +63,7 @@ #include "V3Graph.h" #include "V3HierBlock.h" #include "V3Inline.h" +#include "V3InlineCFuncs.h" #include "V3Inst.h" #include "V3Interface.h" #include "V3LibMap.h" @@ -565,6 +566,11 @@ static void process() { V3Reloop::reloopAll(v3Global.rootp()); } + if (v3Global.opt.inlineCFuncs()) { + // Inline small CFuncs to reduce function call overhead + V3InlineCFuncs::inlineAll(v3Global.rootp()); + } + // Fix very deep expressions // Mark evaluation functions as member functions, if needed. V3Depth::depthAll(v3Global.rootp()); diff --git a/src/verilog.y b/src/verilog.y index 4231b47fe..078ddd850 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -1679,8 +1679,7 @@ modportPortsDeclList: // We track the type as with the V2k series of defines, then create as each ID is seen. modportPortsDecl: // // IEEE: modport_simple_ports_declaration - port_direction modportSimplePortOrTFPort { $$ = new AstModportVarRef{$2, *$2, GRAMMARP->m_varIO}; - GRAMMARP->m_modportImpExpActive = false;} + port_direction { GRAMMARP->m_modportImpExpActive = false; } modportSimplePortOrTFPort { $$ = $3; } // // IEEE: modport_clocking_declaration | yCLOCKING idAny/*clocking_identifier*/ { $$ = new AstModportClockingRef{$1, *$2}; } // // IEEE: yIMPORT modport_tf_port @@ -1700,19 +1699,20 @@ modportPortsDecl: { $$ = nullptr; BBUNSUP($1, "Unsupported: Modport export with prototype"); DEL($2); } // Continuations of above after a comma. // // IEEE: modport_simple_ports_declaration - | modportSimplePortOrTFPort { $$ = GRAMMARP->m_modportImpExpActive ? + | modportSimplePortOrTFPort { $$ = $1; } + ; + +modportSimplePortOrTFPort:// IEEE: modport_simple_port or modport_tf_port, depending what keyword was earlier + idAny { $$ = GRAMMARP->m_modportImpExpActive ? static_cast( new AstModportFTaskRef{ $1, *$1, GRAMMARP->m_modportImpExpLastIsExport} ) : static_cast( new AstModportVarRef{ $1, *$1, GRAMMARP->m_varIO} ); } - ; - -modportSimplePortOrTFPort:// IEEE: modport_simple_port or modport_tf_port, depending what keyword was earlier - idAny { $$ = $1; } - | '.' idAny '(' ')' { $$ = $2; BBUNSUP($1, "Unsupported: Modport dotted port name"); } - | '.' idAny '(' expr ')' { $$ = $2; BBUNSUP($1, "Unsupported: Modport dotted port name"); } + | '.' idAny '(' ')' { $$ = new AstModportVarRef{$2, *$2, GRAMMARP->m_varIO}; + BBUNSUP($4, "Unsupported: Modport empty expression"); } + | '.' idAny '(' expr ')' { $$ = new AstModportVarRef{$2, *$2, $4, GRAMMARP->m_varIO}; } ; //************************************************ diff --git a/test_regress/t/t_alias_force.v b/test_regress/t/t_alias_force.v index b7631a871..92e782e59 100644 --- a/test_regress/t/t_alias_force.v +++ b/test_regress/t/t_alias_force.v @@ -22,11 +22,13 @@ module t ( /*AUTOARG*/ force a = 16'h1234; if (a != 16'h1234 || a != b) $stop; release a; - end else if (cyc == 2) begin + end + else if (cyc == 2) begin force b = 16'h5678; if (a != 16'h5678 || a != b) $stop; release b; - end else if (cyc == 3) begin + end + else if (cyc == 3) begin $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_alias_hier_ref_bad.v b/test_regress/t/t_alias_hier_ref_bad.v index 3487fd1c4..f17a9cdcf 100644 --- a/test_regress/t/t_alias_hier_ref_bad.v +++ b/test_regress/t/t_alias_hier_ref_bad.v @@ -12,7 +12,7 @@ module t ( /*AUTOARG*/ ); input clk; - reg [15:0] out; + reg [15:0] out; wire [15:0] a; alias a = sub_i.btw; @@ -29,7 +29,7 @@ module sub ( output wire [15:0] out ); - reg [31:0] counter = 32'h0; + reg [31:0] counter = 32'h0; wire [15:0] btw; assign btw = {counter[15:0]}; diff --git a/test_regress/t/t_alw_reorder_inlined_func.v b/test_regress/t/t_alw_reorder_inlined_func.v index da8fc94cd..512fb2ebf 100644 --- a/test_regress/t/t_alw_reorder_inlined_func.v +++ b/test_regress/t/t_alw_reorder_inlined_func.v @@ -4,8 +4,10 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: $time=%0t got='h%x exp='h%x\n", `__FILE__,`__LINE__, $time, (got), (exp)); `stop; end while(0) +// verilog_format: on module t; @@ -18,15 +20,16 @@ module t; // Constant 1 set in initial block, but not known at compile time logic enable = 1'b0; - int array [32]; + int array[32]; function automatic int get(logic en, logic [4:0] idx); - if (en) begin // Always taken, but need the 'if' to show bug + if (en) begin // Always taken, but need the 'if' to show bug int tmp; idx = ~idx; tmp = array[~idx]; return tmp; - end else begin + end + else begin return 0; end endfunction diff --git a/test_regress/t/t_alw_sen_compare.v b/test_regress/t/t_alw_sen_compare.v index f2edfb4c0..16f121f2d 100644 --- a/test_regress/t/t_alw_sen_compare.v +++ b/test_regress/t/t_alw_sen_compare.v @@ -5,13 +5,16 @@ // SPDX-License-Identifier: CC0-1.0 module top; - sub inst( + sub inst ( .a({128{1'b1}}), .b({128{1'b1}}) ); endmodule -module sub(a, b); +module sub ( + a, + b +); input [127:0] a; input [127:0] b; always @(a or b) begin diff --git a/test_regress/t/t_array_index_side.v b/test_regress/t/t_array_index_side.v index c6c38d7fc..1e2e1c151 100644 --- a/test_regress/t/t_array_index_side.v +++ b/test_regress/t/t_array_index_side.v @@ -4,8 +4,10 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on class Cls; int m_index; diff --git a/test_regress/t/t_array_method_map.out b/test_regress/t/t_array_method_map.out index a57e239a2..054088ab2 100644 --- a/test_regress/t/t_array_method_map.out +++ b/test_regress/t/t_array_method_map.out @@ -1,11 +1,11 @@ -%Error-UNSUPPORTED: t/t_array_method_map.v:17:15: Unsupported: Array 'map' method (IEEE 1800-2023 7.12.5) +%Error-UNSUPPORTED: t/t_array_method_map.v:19:15: Unsupported: Array 'map' method (IEEE 1800-2023 7.12.5) : ... note: In instance 't' - 17 | res = a.map(el) with (el == 200); + 19 | res = a.map(el) with (el == 200); | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error: t/t_array_method_map.v:17:15: Unknown built-in array method 'map' +%Error: t/t_array_method_map.v:19:15: Unknown built-in array method 'map' : ... note: In instance 't' - 17 | res = a.map(el) with (el == 200); + 19 | res = a.map(el) with (el == 200); | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_array_method_map.v b/test_regress/t/t_array_method_map.v index d764ca90c..7fda8036d 100644 --- a/test_regress/t/t_array_method_map.v +++ b/test_regress/t/t_array_method_map.v @@ -4,8 +4,10 @@ // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop -`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; diff --git a/test_regress/t/t_assert_elab_p.v b/test_regress/t/t_assert_elab_p.v index 3699c80c4..92a95bcc1 100644 --- a/test_regress/t/t_assert_elab_p.v +++ b/test_regress/t/t_assert_elab_p.v @@ -25,7 +25,8 @@ module t #( .ID_T(ID_T), .STAGE_IDS(STAGE_IDS) ) pipe ( - .*); + .* + ); initial $finish; diff --git a/test_regress/t/t_assert_future.v b/test_regress/t/t_assert_future.v index ef88c6843..29ce13888 100644 --- a/test_regress/t/t_assert_future.v +++ b/test_regress/t/t_assert_future.v @@ -10,11 +10,8 @@ // verilog_format: on module t ( - /*AUTOARG*/ - // Inputs - clk - ); - input clk; + input clk +); global clocking @(posedge clk); endclocking diff --git a/test_regress/t/t_assert_future_bad.out b/test_regress/t/t_assert_future_bad.out index 3cfa347d0..1856d9ba5 100644 --- a/test_regress/t/t_assert_future_bad.out +++ b/test_regress/t/t_assert_future_bad.out @@ -1,22 +1,22 @@ -%Error: t/t_assert_future_bad.v:18:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4) +%Error: t/t_assert_future_bad.v:16:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4) : ... note: In instance 't' - 18 | else $display("Future=%0d", $future_gclk(a)); + 16 | else $display("Future=%0d", $future_gclk(a)); | ^~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_assert_future_bad.v:21:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4) +%Error: t/t_assert_future_bad.v:19:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4) : ... note: In instance 't' - 21 | else $display("Future=%0d", $rising_gclk(a)); + 19 | else $display("Future=%0d", $rising_gclk(a)); | ^~~~~~~~~~~~ -%Error: t/t_assert_future_bad.v:24:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4) +%Error: t/t_assert_future_bad.v:22:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4) : ... note: In instance 't' - 24 | else $display("Future=%0d", $falling_gclk(a)); + 22 | else $display("Future=%0d", $falling_gclk(a)); | ^~~~~~~~~~~~~ -%Error: t/t_assert_future_bad.v:27:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4) +%Error: t/t_assert_future_bad.v:25:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4) : ... note: In instance 't' - 27 | else $display("Future=%0d", $steady_gclk(a)); + 25 | else $display("Future=%0d", $steady_gclk(a)); | ^~~~~~~~~~~~ -%Error: t/t_assert_future_bad.v:30:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4) +%Error: t/t_assert_future_bad.v:28:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4) : ... note: In instance 't' - 30 | else $display("Future=%0d", $changing_gclk(a)); + 28 | else $display("Future=%0d", $changing_gclk(a)); | ^~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_assert_future_bad.v b/test_regress/t/t_assert_future_bad.v index d6b7926d4..f8e28a4bf 100644 --- a/test_regress/t/t_assert_future_bad.v +++ b/test_regress/t/t_assert_future_bad.v @@ -4,12 +4,10 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module t ( /*AUTOARG*/ - // Inputs - a, clk - ); - input a; - input clk; +module t ( + input a, + input clk +); global clocking @(posedge clk); endclocking diff --git a/test_regress/t/t_assert_future_unsup.out b/test_regress/t/t_assert_future_unsup.out index 819a4484e..909e613f2 100644 --- a/test_regress/t/t_assert_future_unsup.out +++ b/test_regress/t/t_assert_future_unsup.out @@ -1,6 +1,6 @@ -%Error-UNSUPPORTED: t/t_assert_future_unsup.v:21:54: Unsupported/illegal: Future value function used with expression with operator FUNCREF 'func' +%Error-UNSUPPORTED: t/t_assert_future_unsup.v:19:54: Unsupported/illegal: Future value function used with expression with operator FUNCREF 'func' : ... note: In instance 't' - 21 | assert property (@(posedge clk) $future_gclk(a) == func(a)); + 19 | assert property (@(posedge clk) $future_gclk(a) == func(a)); | ^~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_assert_future_unsup.v b/test_regress/t/t_assert_future_unsup.v index 77282bb83..542ea17af 100644 --- a/test_regress/t/t_assert_future_unsup.v +++ b/test_regress/t/t_assert_future_unsup.v @@ -4,12 +4,10 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module t ( /*AUTOARG*/ - // Inputs - a, clk - ); - input a; - input clk; +module t ( + input a, + input clk +); function logic func(input logic i); return i; diff --git a/test_regress/t/t_assert_implication_coverage.v b/test_regress/t/t_assert_implication_coverage.v index edc613f52..8b4e5539c 100644 --- a/test_regress/t/t_assert_implication_coverage.v +++ b/test_regress/t/t_assert_implication_coverage.v @@ -4,13 +4,12 @@ // without warranty, 2025 by Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk +module t ( + input clk ); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; Test test ( /*AUTOINST*/ @@ -19,13 +18,13 @@ module t (/*AUTOARG*/ .cyc(cyc) ); - always @ (posedge clk) begin - if (cyc!=0) begin + always @(posedge clk) begin + if (cyc != 0) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $display("cyc=%0d", cyc); `endif - if (cyc==10) begin + if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end @@ -35,7 +34,9 @@ module t (/*AUTOARG*/ endmodule // Interface for data validation with coverage -interface data_valid_if (input logic clk); +interface data_valid_if ( + input logic clk +); logic enable_invalid_data_checks; logic valid; logic [7:0] data; @@ -49,16 +50,15 @@ interface data_valid_if (input logic clk); endinterface -module Test - ( - input clk, - input integer cyc - ); +module Test ( + input clk, + input integer cyc +); logic rst_n; // Instantiate the interface - data_valid_if dv_if(clk); + data_valid_if dv_if (clk); // Reset logic initial begin diff --git a/test_regress/t/t_assert_pre.v b/test_regress/t/t_assert_pre.v index 64ee99eb2..c8ce196ab 100644 --- a/test_regress/t/t_assert_pre.v +++ b/test_regress/t/t_assert_pre.v @@ -4,15 +4,14 @@ // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop -`define checkh(gotv, - expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on -module t ( /*AUTOARG*/ - // Inputs - clk +module t ( + input clk ); - input clk; bit toggle = 0; int inc = 0; @@ -49,7 +48,8 @@ module t ( /*AUTOARG*/ `endif if (cyc % 3 == 0) begin toggle <= 1; - end else begin + end + else begin toggle <= 0; end diff --git a/test_regress/t/t_assign_automatic_bad.out b/test_regress/t/t_assign_automatic_bad.out index 393ec33ca..11b828a98 100644 --- a/test_regress/t/t_assign_automatic_bad.out +++ b/test_regress/t/t_assign_automatic_bad.out @@ -1,34 +1,34 @@ -%Error: t/t_assign_automatic_bad.v:35:10: Dynamically-sized variable not allowed in continuous assignment (IEEE 1800-2023 6.21): 'bad_dyn5' +%Error: t/t_assign_automatic_bad.v:36:10: Dynamically-sized variable not allowed in continuous assignment (IEEE 1800-2023 6.21): 'bad_dyn5' : ... note: In instance 't' - 35 | assign bad_dyn5[0] = empty_dyn; + 36 | assign bad_dyn5[0] = empty_dyn; | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_assign_automatic_bad.v:37:12: Automatic lifetime variable not allowed in continuous assignment (IEEE 1800-2023 6.21): 'm_bad1' +%Error: t/t_assign_automatic_bad.v:38:12: Automatic lifetime variable not allowed in continuous assignment (IEEE 1800-2023 6.21): 'm_bad1' : ... note: In instance 't' - 37 | assign c.m_bad1 = 2; + 38 | assign c.m_bad1 = 2; | ^~~~~~ -%Error: t/t_assign_automatic_bad.v:47:5: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'bad_dyn6' +%Error: t/t_assign_automatic_bad.v:48:5: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'bad_dyn6' : ... note: In instance 't' - 47 | bad_dyn6[0] <= 2; + 48 | bad_dyn6[0] <= 2; | ^~~~~~~~ -%Error: t/t_assign_automatic_bad.v:49:5: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'bad_queue' +%Error: t/t_assign_automatic_bad.v:50:5: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'bad_queue' : ... note: In instance 't' - 49 | bad_queue[0] <= 2; + 50 | bad_queue[0] <= 2; | ^~~~~~~~~ -%Error: t/t_assign_automatic_bad.v:51:5: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'bad_assoc' +%Error: t/t_assign_automatic_bad.v:52:5: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'bad_assoc' : ... note: In instance 't' - 51 | bad_assoc[0] <= 2; + 52 | bad_assoc[0] <= 2; | ^~~~~~~~~ -%Error: t/t_assign_automatic_bad.v:54:7: Automatic lifetime variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'm_bad2' +%Error: t/t_assign_automatic_bad.v:55:7: Automatic lifetime variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'm_bad2' : ... note: In instance 't' - 54 | c.m_bad2 <= 2; + 55 | c.m_bad2 <= 2; | ^~~~~~ -%Error: t/t_assign_automatic_bad.v:56:10: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 's_dyn' +%Error: t/t_assign_automatic_bad.v:57:10: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 's_dyn' : ... note: In instance 't' - 56 | Cls::s_dyn[0] <= 2; + 57 | Cls::s_dyn[0] <= 2; | ^~~~~ -%Error: t/t_assign_automatic_bad.v:58:26: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 's_dyn' - : ... note: In instance 't' - 58 | clist[bad_dyn6[0]++].s_dyn[0] <= '1; - | ^~~~~ +%Error: t/t_assign_automatic_bad.v:63:7: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 's_dyn' + : ... note: In instance 't' + 63 | ].s_dyn[0] <= '1; + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_assign_automatic_bad.v b/test_regress/t/t_assign_automatic_bad.v index 90159e5ce..dca14c9ba 100644 --- a/test_regress/t/t_assign_automatic_bad.v +++ b/test_regress/t/t_assign_automatic_bad.v @@ -18,8 +18,9 @@ class Cls; int m_bad2; endclass -module t(clk); - input clk; +module t ( + input clk +); Cls c; @@ -46,16 +47,20 @@ module t(clk); always @(posedge clk) begin bad_dyn6[0] <= 2; // <--- Error: nonblocking dynarray element bad_dyn6 <= empty_dyn; // <--- OK: nonblocking dynarray assignment, not to its element - bad_queue[0] <= 2; // Error: nonblocking queue element assignment - bad_queue <= empty_queue; // OK: nonblocking assignment to queue itself, not to its element - bad_assoc[0] <= 2; // Error: nonblocking associative array element assignment + bad_queue[0] <= 2; // Error: nonblocking queue element assignment + bad_queue <= empty_queue; // OK: nonblocking assignment to queue itself, not to its element + bad_assoc[0] <= 2; // Error: nonblocking associative array element assignment bad_assoc <= empty_assoc; // OK: nonblocking assignment to associative array itself, not to its element Cls::s_ok2 <= 2; // OK: nonblocking class static c.m_bad2 <= 2; // <--- Error: nonblocking class automatic Cls::s_dyn <= 2; // OK: nonblocking class static dynarray assignment, not to its element Cls::s_dyn[0] <= 2; // Error: nonblocking class static dynarray element - clist[bad_dyn6[0]++].s_dyn <= '1; // OK: direct nonblocking assignment to dynamically-sized array - clist[bad_dyn6[0]++].s_dyn[0] <= '1; // Error: nonblocking assigment to dynamically-sized array element + clist[ + bad_dyn6[0]++ + ].s_dyn <= '1; // OK: direct nonblocking assignment to dynamically-sized array + clist[ + bad_dyn6[0]++ + ].s_dyn[0] <= '1; // Error: nonblocking assigment to dynamically-sized array element mt(ok_7); $stop; end diff --git a/test_regress/t/t_assigndly_deep_ref.v b/test_regress/t/t_assigndly_deep_ref.v index 643b08226..9393c161d 100644 --- a/test_regress/t/t_assigndly_deep_ref.v +++ b/test_regress/t/t_assigndly_deep_ref.v @@ -38,8 +38,8 @@ class Bar; endclass module t; - Iface iface(); - Iface iface2(); + Iface iface (); + Iface iface2 (); task clockSome(); #2; diff --git a/test_regress/t/t_assigndly_deep_ref_array.v b/test_regress/t/t_assigndly_deep_ref_array.v index 4bf3eb9ce..4b9b12459 100644 --- a/test_regress/t/t_assigndly_deep_ref_array.v +++ b/test_regress/t/t_assigndly_deep_ref_array.v @@ -5,13 +5,13 @@ // SPDX-License-Identifier: CC0-1.0 interface Iface; - bit clk; - int x[2:0]; + bit clk; + int x[2:0]; - clocking cb @(posedge clk); - default input #0 output #0; - inout x; - endclocking + clocking cb @(posedge clk); + default input #0 output #0; + inout x; + endclocking endinterface class Foo; @@ -42,8 +42,8 @@ class Bar; endclass module t; - Iface iface(); - Iface iface2(); + Iface iface (); + Iface iface2 (); task clockSome(); #2; diff --git a/test_regress/t/t_assoc_enum.v b/test_regress/t/t_assoc_enum.v index 485e3205f..24e756851 100644 --- a/test_regress/t/t_assoc_enum.v +++ b/test_regress/t/t_assoc_enum.v @@ -4,9 +4,11 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on class X; typedef enum int { @@ -31,14 +33,11 @@ class X; endclass -module t;/*AUTOARG*/ - - -initial begin - X x = new; - $finish; -end - +module t; + initial begin + X x = new; + $finish; + end endmodule diff --git a/test_regress/t/t_assoc_method_map.v b/test_regress/t/t_assoc_method_map.v index 673f77d72..1003f7742 100644 --- a/test_regress/t/t_assoc_method_map.v +++ b/test_regress/t/t_assoc_method_map.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 `define stop $stop -`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; diff --git a/test_regress/t/t_assoc_wildcard_map.out b/test_regress/t/t_assoc_wildcard_map.out index aa3a972bb..91dae9ed5 100644 --- a/test_regress/t/t_assoc_wildcard_map.out +++ b/test_regress/t/t_assoc_wildcard_map.out @@ -1,6 +1,6 @@ -%Error-UNSUPPORTED: t/t_assoc_wildcard_map.v:17:15: Unsupported: Wildcard array 'map' method (IEEE 1800-2023 7.12.5) +%Error-UNSUPPORTED: t/t_assoc_wildcard_map.v:19:15: Unsupported: Wildcard array 'map' method (IEEE 1800-2023 7.12.5) : ... note: In instance 't' - 17 | res = a.map(el) with (el == 2); + 19 | res = a.map(el) with (el == 2); | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_assoc_wildcard_map.v b/test_regress/t/t_assoc_wildcard_map.v index 6fbcffd38..a5e2f012a 100644 --- a/test_regress/t/t_assoc_wildcard_map.v +++ b/test_regress/t/t_assoc_wildcard_map.v @@ -4,8 +4,10 @@ // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop -`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; diff --git a/test_regress/t/t_bitsel_concat.v b/test_regress/t/t_bitsel_concat.v index d869271b2..c0d687e00 100644 --- a/test_regress/t/t_bitsel_concat.v +++ b/test_regress/t/t_bitsel_concat.v @@ -9,7 +9,10 @@ // warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); +// verilog_format: off +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on // Test IEEE 1800-2023 concat bit selects, function bit selects, method bit selects diff --git a/test_regress/t/t_bitsel_lvalue.v b/test_regress/t/t_bitsel_lvalue.v index 83359a594..da48ee063 100644 --- a/test_regress/t/t_bitsel_lvalue.v +++ b/test_regress/t/t_bitsel_lvalue.v @@ -4,17 +4,16 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module t - ( - input wire [ 31:0] foo, - output reg [144:0] bar, - output reg [144:0] bar2, - output reg [144:0] bar3, - output reg [144:0] bar4 - ); - // verilator lint_off SELRANGE - assign bar[159:128] = foo; - assign bar2[159] = foo[1]; - assign bar3[159 -: 32] = foo; - assign bar4[128 +: 32] = foo; +module t ( + input wire [31:0] foo, + output reg [144:0] bar, + output reg [144:0] bar2, + output reg [144:0] bar3, + output reg [144:0] bar4 +); + // verilator lint_off SELRANGE + assign bar[159:128] = foo; + assign bar2[159] = foo[1]; + assign bar3[159-:32] = foo; + assign bar4[128+:32] = foo; endmodule diff --git a/test_regress/t/t_c_width_bad.out b/test_regress/t/t_c_width_bad.out index d8a3bb4ae..ff7712f6b 100644 --- a/test_regress/t/t_c_width_bad.out +++ b/test_regress/t/t_c_width_bad.out @@ -1,6 +1,6 @@ -%Error-UNSUPPORTED: t/t_c_width_bad.v:9:22: Unsupported: $c can't generate wider than 64 bits +%Error-UNSUPPORTED: t/t_c_width_bad.v:9:21: Unsupported: $c can't generate wider than 64 bits : ... note: In instance 't' - 9 | bit [99:0] wide = $c100("0"); - | ^~~~~ + 9 | bit [99:0] wide = $c100("0"); + | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_c_width_bad.v b/test_regress/t/t_c_width_bad.v index 04bedf1c2..18bfe5d84 100644 --- a/test_regress/t/t_c_width_bad.v +++ b/test_regress/t/t_c_width_bad.v @@ -6,8 +6,8 @@ module t; - bit [99:0] wide = $c100("0"); + bit [99:0] wide = $c100("0"); - initial $display("%d", wide); + initial $display("%d", wide); endmodule diff --git a/test_regress/t/t_cast_stream.v b/test_regress/t/t_cast_stream.v index a2c426d9d..05c75c6d8 100644 --- a/test_regress/t/t_cast_stream.v +++ b/test_regress/t/t_cast_stream.v @@ -4,8 +4,10 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on typedef enum { UVM_TLM_READ_COMMAND, diff --git a/test_regress/t/t_class_defaultparam_import.v b/test_regress/t/t_class_defaultparam_import.v index e73287e6f..9788346f5 100644 --- a/test_regress/t/t_class_defaultparam_import.v +++ b/test_regress/t/t_class_defaultparam_import.v @@ -5,8 +5,11 @@ // SPDX-License-Identifier: CC0-1.0 package foo; - class bar#(type T=int); - endclass -endpackage; + class bar #( + type T = int + ); + endclass +endpackage +; import foo::bar; diff --git a/test_regress/t/t_class_extern_typeref.v b/test_regress/t/t_class_extern_typeref.v index 3eb715e5c..cabfb23ea 100644 --- a/test_regress/t/t_class_extern_typeref.v +++ b/test_regress/t/t_class_extern_typeref.v @@ -4,7 +4,9 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -class uvm_process_guard#(type T=int); +class uvm_process_guard #( + type T = int +); T m_context; extern function T get_context(); extern function new(T ctxt); diff --git a/test_regress/t/t_class_hier_construction.v b/test_regress/t/t_class_hier_construction.v index e62488136..116f4815c 100644 --- a/test_regress/t/t_class_hier_construction.v +++ b/test_regress/t/t_class_hier_construction.v @@ -4,9 +4,11 @@ // any use, without warranty, 2025 by Petr Nohavica // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on interface class IBottomMid; pure virtual function void moo(int i); @@ -48,7 +50,7 @@ class middle_class extends bottom_class implements IMid, IBottom; endfunction virtual function string bar(); - return name; + return name; endfunction endclass @@ -75,10 +77,10 @@ module t; top_class t = s; IMid im; - `checks( b.name, "middle ahoj 42" ); - `checks( s.name, "middle ahoj 42" ); - `checks( t.name, "middle ahoj 42" ); - `checkh( t.i, 42); + `checks(b.name, "middle ahoj 42"); + `checks(s.name, "middle ahoj 42"); + `checks(t.name, "middle ahoj 42"); + `checkh(t.i, 42); `checks(s.bar(), "middle ahoj 42"); im = s; im.moo(42); diff --git a/test_regress/t/t_class_modscope.v b/test_regress/t/t_class_modscope.v index a2cfb24cd..8caa24dbf 100644 --- a/test_regress/t/t_class_modscope.v +++ b/test_regress/t/t_class_modscope.v @@ -4,10 +4,12 @@ // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on -module m(); +module m (); class c; static function void fstatic(); `checkh(v, 42); @@ -23,7 +25,7 @@ module m(); int v; initial begin - v=42; + v = 42; `checkh(v, 42); c::fstatic(); classinst = new(); diff --git a/test_regress/t/t_class_param_extends_static_member_function_access.v b/test_regress/t/t_class_param_extends_static_member_function_access.v index 09cf19ee2..60ca13c37 100644 --- a/test_regress/t/t_class_param_extends_static_member_function_access.v +++ b/test_regress/t/t_class_param_extends_static_member_function_access.v @@ -4,16 +4,20 @@ // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 -class Class1 #(type T); +class Class1 #( + type T +); static function int get_p(); return 7; endfunction endclass -class Class2 #(type T) extends Class1 #(T); - static function int get_p2; - return T::get_p(); - endfunction +class Class2 #( + type T +) extends Class1 #(T); + static function int get_p2; + return T::get_p(); + endfunction endclass module t; diff --git a/test_regress/t/t_class_param_super.v b/test_regress/t/t_class_param_super.v index 9f90de633..1b26f8812 100644 --- a/test_regress/t/t_class_param_super.v +++ b/test_regress/t/t_class_param_super.v @@ -5,14 +5,14 @@ // SPDX-License-Identifier: CC0-1.0 class base #( - type T = int + type T = int ); - function void fbase(); - endfunction + function void fbase(); + endfunction endclass class ext extends base; - function void fext(); - super.fbase(); - endfunction + function void fext(); + super.fbase(); + endfunction endclass diff --git a/test_regress/t/t_class_param_typedef3.v b/test_regress/t/t_class_param_typedef3.v index 6472b906c..9c1557ce0 100644 --- a/test_regress/t/t_class_param_typedef3.v +++ b/test_regress/t/t_class_param_typedef3.v @@ -4,40 +4,44 @@ // without warranty. // SPDX-License-Identifier: CC0-1.0 -class func_c #(parameter p_width=4); - static function logic[p_width-1:0] func( - input logic[p_width-1:0] inb - ); - func = inb; - endfunction +class func_c #( + parameter p_width = 4 +); + static function logic [p_width-1:0] func(input logic [p_width-1:0] inb); + func = inb; + endfunction endclass -module modA #(parameter p_width = 7)( - input logic [p_width-1:0] sig_a - ,output logic [p_width-1:0] sig_b +module modA #( + parameter p_width = 7 +) ( + input logic [p_width-1:0] sig_a, + output logic [p_width-1:0] sig_b ); - assign sig_b = func_c#(p_width)::func(sig_a); + assign sig_b = func_c#(p_width)::func(sig_a); endmodule -module the_top(); - localparam int Size = 3; +module the_top (); + localparam int Size = 3; - logic [Size-1:0] sig_a; - logic [Size-1:0] sig_b; + logic [Size-1:0] sig_a; + logic [Size-1:0] sig_b; - modA #(.p_width(Size)) modA( - .sig_a(sig_a) - ,.sig_b(sig_b) - ); + modA #( + .p_width(Size) + ) modA ( + .sig_a(sig_a), + .sig_b(sig_b) + ); - //assign sig_b = func_c#(p_width)::func(inb_i); + //assign sig_b = func_c#(p_width)::func(inb_i); - initial begin - sig_a = 'h3; - #1; - $display("sig_a=%d, sig_b=%d", sig_a, sig_b); - if(sig_b != 'h3) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + sig_a = 'h3; + #1; + $display("sig_a=%d, sig_b=%d", sig_a, sig_b); + if (sig_b != 'h3) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_param_typedef4.v b/test_regress/t/t_class_param_typedef4.v index a3b623ca5..9af53474f 100644 --- a/test_regress/t/t_class_param_typedef4.v +++ b/test_regress/t/t_class_param_typedef4.v @@ -4,39 +4,43 @@ // without warranty. // SPDX-License-Identifier: CC0-1.0 -class func_c #(parameter p_width=4); - static function logic[p_width-1:0] func( - input logic[p_width-1:0] inb - ); +class func_c #( + parameter p_width = 4 +); + static function logic [p_width-1:0] func(input logic [p_width-1:0] inb); func = inb; endfunction endclass -module modA #(parameter p_width = 7)( - input logic [p_width-1:0] sig_a - ,output logic [p_width-1:0] sig_b +module modA #( + parameter p_width = 7 +) ( + input logic [p_width-1:0] sig_a, + output logic [p_width-1:0] sig_b ); assign sig_b = func_c#(p_width)::func(sig_a); endmodule -module the_top(); +module the_top (); localparam int Size = 3; logic [Size-1:0] sig_a; logic [Size-1:0] sig_b; logic [Size-1:0] sig_c; - modA #(.p_width(Size)) modA( - .sig_a(sig_a) - ,.sig_b(sig_b) + modA #( + .p_width(Size) + ) modA ( + .sig_a(sig_a), + .sig_b(sig_b) ); initial begin sig_a = 'h3; sig_c = func_c#(Size)::func('h5); #1; - if(sig_b != 'h3) $stop; - if(sig_c != 'h5) $stop; + if (sig_b != 'h3) $stop; + if (sig_c != 'h5) $stop; $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_class_param_typedef5.v b/test_regress/t/t_class_param_typedef5.v index 29a7e9942..201778abb 100644 --- a/test_regress/t/t_class_param_typedef5.v +++ b/test_regress/t/t_class_param_typedef5.v @@ -4,40 +4,42 @@ // without warranty. // SPDX-License-Identifier: CC0-1.0 -class func_c #(parameter p_width=4); - typedef struct packed { - logic[p_width-1:0] data; - } my_type_t; - static function my_type_t func( - input logic[p_width-1:0] inb - ); +class func_c #( + parameter p_width = 4 +); + typedef struct packed {logic [p_width-1:0] data;} my_type_t; + static function my_type_t func(input logic [p_width-1:0] inb); func.data = inb; endfunction endclass -module modA #(parameter p_width = 7)( - input func_c#(p_width)::my_type_t sig_a, - output func_c#(p_width)::my_type_t sig_b +module modA #( + parameter p_width = 7 +) ( + input func_c#(p_width)::my_type_t sig_a, + output func_c#(p_width)::my_type_t sig_b ); assign sig_b.data = func_c#(p_width)::func(sig_a); endmodule -module the_top(); +module the_top (); localparam int Size = 3; - func_c#(Size)::my_type_t sig_a, sig_b, sig_c; + func_c #(Size)::my_type_t sig_a, sig_b, sig_c; - modA #(.p_width(Size)) modA( - .sig_a(sig_a), - .sig_b(sig_b) + modA #( + .p_width(Size) + ) modA ( + .sig_a(sig_a), + .sig_b(sig_b) ); initial begin sig_a.data = 'h3; sig_c.data = func_c#(Size)::func('h5); #1; - if(sig_b.data != 'h3) $stop; - if(sig_c.data != 'h5) $stop; + if (sig_b.data != 'h3) $stop; + if (sig_c.data != 'h5) $stop; $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_class_param_typedef6.v b/test_regress/t/t_class_param_typedef6.v index 53f200f0e..acad6af63 100644 --- a/test_regress/t/t_class_param_typedef6.v +++ b/test_regress/t/t_class_param_typedef6.v @@ -4,28 +4,22 @@ // without warranty. // SPDX-License-Identifier: CC0-1.0 - +// verilog_format: off `define stop $stop -`define checkd(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0d exp=%0d\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on class pipeline_class #( - parameter type XWORD = logic + parameter type XWORD = logic ); - typedef struct packed { - XWORD pc; - } if_id_t; + typedef struct packed {XWORD pc;} if_id_t; endclass module pipe_reg #( - parameter type T = logic -)(); + parameter type T = logic +) (); initial begin #1; `checkd($bits(T), 8); @@ -35,9 +29,9 @@ endmodule module the_top #() (); typedef logic [7:0] my_t; - typedef pipeline_class #(my_t)::if_id_t if_id2_t; + typedef pipeline_class#(my_t)::if_id_t if_id2_t; typedef if_id2_t if_id_t; - pipe_reg #(if_id_t) if_id_reg(); + pipe_reg #(if_id_t) if_id_reg (); initial begin #1; diff --git a/test_regress/t/t_class_param_upcast.v b/test_regress/t/t_class_param_upcast.v index d82f1320a..356780af1 100644 --- a/test_regress/t/t_class_param_upcast.v +++ b/test_regress/t/t_class_param_upcast.v @@ -4,7 +4,9 @@ // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 -class factory #(type T); +class factory #( + type T +); static function T create; T obj = new; return obj; @@ -24,10 +26,9 @@ endclass module t; initial begin foo f; - if (bit'($random)) - f = bar::create; - else - f = factory#(foo)::create(); + if (bit'($random)) f = bar::create; + else f = factory#(foo)::create(); $finish; end -endmodule; +endmodule +; diff --git a/test_regress/t/t_class_scope_import_bad.out b/test_regress/t/t_class_scope_import_bad.out index 6e1064205..f2fd13b82 100644 --- a/test_regress/t/t_class_scope_import_bad.out +++ b/test_regress/t/t_class_scope_import_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_class_scope_import_bad.v:11:11: Import statement directly within a class scope is illegal - 11 | import pkg::*; - | ^~~ +%Error: t/t_class_scope_import_bad.v:11:10: Import statement directly within a class scope is illegal + 11 | import pkg::*; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_class_scope_import_bad.v b/test_regress/t/t_class_scope_import_bad.v index 0306ffa6a..8bf6cee96 100644 --- a/test_regress/t/t_class_scope_import_bad.v +++ b/test_regress/t/t_class_scope_import_bad.v @@ -8,8 +8,8 @@ package pkg; endpackage class genericClass; - import pkg::*; + import pkg::*; endclass -module tb_top(); +module tb_top (); endmodule diff --git a/test_regress/t/t_class_super_new_noextend_bad.out b/test_regress/t/t_class_super_new_noextend_bad.out index b41a37a55..167ec6f0b 100644 --- a/test_regress/t/t_class_super_new_noextend_bad.out +++ b/test_regress/t/t_class_super_new_noextend_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_class_super_new_noextend_bad.v:10:12: 'super' used on non-extended class (IEEE 1800-2023 8.15) - 10 | super.new(); - | ^ +%Error: t/t_class_super_new_noextend_bad.v:10:10: 'super' used on non-extended class (IEEE 1800-2023 8.15) + 10 | super.new(); + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_class_super_new_noextend_bad.v b/test_regress/t/t_class_super_new_noextend_bad.v index 2e41d3bdd..7ea862a47 100644 --- a/test_regress/t/t_class_super_new_noextend_bad.v +++ b/test_regress/t/t_class_super_new_noextend_bad.v @@ -6,7 +6,7 @@ // class Cls; - function new(); - super.new(); // Bad - no extends - endfunction + function new(); + super.new(); // Bad - no extends + endfunction endclass diff --git a/test_regress/t/t_class_to_basic_assignment_bad.out b/test_regress/t/t_class_to_basic_assignment_bad.out index a1b195381..51964f446 100755 --- a/test_regress/t/t_class_to_basic_assignment_bad.out +++ b/test_regress/t/t_class_to_basic_assignment_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_class_to_basic_assignment_bad.v:26:29: Assign RHS 'class{}Foo' cannot be assigned to non-class 'int' - 26 | new_node.phase_done = get(); - | ^ +%Error: t/t_class_to_basic_assignment_bad.v:26:27: Assign RHS 'class{}Foo' cannot be assigned to non-class 'int' + 26 | new_node.phase_done = get(); + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_class_to_basic_assignment_bad.v b/test_regress/t/t_class_to_basic_assignment_bad.v index e0f020cce..711841e7b 100644 --- a/test_regress/t/t_class_to_basic_assignment_bad.v +++ b/test_regress/t/t_class_to_basic_assignment_bad.v @@ -12,21 +12,21 @@ class Foo; return ans; endfunction - static function int create (); + static function int create(); return 3; endfunction - function string get_name (); + function string get_name(); return "bar"; endfunction function void add(Foo phase); Foo new_node; if (new_node.get_name() == "run") begin - new_node.phase_done = get(); + new_node.phase_done = get(); end else begin - new_node.phase_done = create(); + new_node.phase_done = create(); end endfunction endclass diff --git a/test_regress/t/t_clocking_input_0_delay.v b/test_regress/t/t_clocking_input_0_delay.v index 8169dc5a0..0a74dd834 100644 --- a/test_regress/t/t_clocking_input_0_delay.v +++ b/test_regress/t/t_clocking_input_0_delay.v @@ -4,7 +4,7 @@ // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 -`timescale 1ms/1ns +`timescale 1ms / 1ns module t; bit clk = 0; bit data = 1; @@ -21,12 +21,11 @@ module t; end initial begin - #4 - if (data != 1) $stop; + #4 if (data != 1) $stop; if (cb.data != 0) $stop; #1; #1step; - if(cb.data != 0) $stop; + if (cb.data != 0) $stop; $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_clocking_input_default.v b/test_regress/t/t_clocking_input_default.v index 00a21752f..5832f7e80 100644 --- a/test_regress/t/t_clocking_input_default.v +++ b/test_regress/t/t_clocking_input_default.v @@ -4,7 +4,7 @@ // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 -`timescale 1ms/1ns +`timescale 1ms / 1ns module t; bit clk = 0; bit data = 1; @@ -21,12 +21,11 @@ module t; end initial begin - #4 - if(data != 1 ) $stop; - if(cb.data != 0) $stop; + #4 if (data != 1) $stop; + if (cb.data != 0) $stop; #1; #1step; - if(cb.data != 1) $stop; + if (cb.data != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_config_work.v b/test_regress/t/t_config_work.v index 21f68b5fa..d82e87e3e 100644 --- a/test_regress/t/t_config_work.v +++ b/test_regress/t/t_config_work.v @@ -6,7 +6,7 @@ module t; // Test --work allows selecting two different libraries for these instances - m1 u_1(); - m2 u_2(); + m1 u_1 (); + m2 u_2 (); final $write("*-* All Finished *-*\n"); endmodule diff --git a/test_regress/t/t_config_work__liba.v b/test_regress/t/t_config_work__liba.v index 539d98c20..e41e44fc4 100644 --- a/test_regress/t/t_config_work__liba.v +++ b/test_regress/t/t_config_work__liba.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 module m1; - m3 u_13(); + m3 u_13 (); initial $display("liba:m1 %%m=%m %%l=%l"); endmodule diff --git a/test_regress/t/t_config_work__libb.v b/test_regress/t/t_config_work__libb.v index b756b5fa5..96b61c137 100644 --- a/test_regress/t/t_config_work__libb.v +++ b/test_regress/t/t_config_work__libb.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 module m2; - m3 u_23(); + m3 u_23 (); initial $display("libb:m2 %%m=%m %%l=%l"); endmodule diff --git a/test_regress/t/t_constraint_global_arr_unsup.v b/test_regress/t/t_constraint_global_arr_unsup.v index 991334e27..8cf37ffb9 100755 --- a/test_regress/t/t_constraint_global_arr_unsup.v +++ b/test_regress/t/t_constraint_global_arr_unsup.v @@ -73,11 +73,13 @@ module t_constraint_global_arr_unsup; o.m_mid_arr[1].m_arr[2].m_y == 400) begin $display("*-* All Finished *-*"); $finish; - end else begin + end + else begin $display("*-* FAILED *-*"); $stop; end - end else begin + end + else begin $display("*-* FAILED: randomize() returned 0 *-*"); $stop; end diff --git a/test_regress/t/t_constraint_global_randMode.v b/test_regress/t/t_constraint_global_randMode.v index e5906e54c..19920ce37 100755 --- a/test_regress/t/t_constraint_global_randMode.v +++ b/test_regress/t/t_constraint_global_randMode.v @@ -6,9 +6,7 @@ class RandomValue; rand int value; - constraint small_int_c { - value < 10; - } + constraint small_int_c {value < 10;} task disable_val(); value.rand_mode(0); endtask diff --git a/test_regress/t/t_constraint_json_only.out b/test_regress/t/t_constraint_json_only.out index f41cdf173..cc4efdef4 100644 --- a/test_regress/t/t_constraint_json_only.out +++ b/test_regress/t/t_constraint_json_only.out @@ -59,9 +59,9 @@ {"type":"BASICDTYPE","name":"logic","addr":"(GB)","loc":"d,22:14,22:15","dtypep":"(GB)","keyword":"logic","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(OB)","loc":"d,25:21,25:22","dtypep":"(OB)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"string","addr":"(M)","loc":"d,73:7,73:13","dtypep":"(M)","keyword":"string","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"int","addr":"(Q)","loc":"d,8:9,8:12","dtypep":"(Q)","keyword":"int","range":"31:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"int","addr":"(Q)","loc":"d,8:9,8:12","dtypep":"(Q)","keyword":"int","range":"31:0","generic":true,"signed":true,"rangep": []}, {"type":"BASICDTYPE","name":"bit","addr":"(U)","loc":"d,11:9,11:12","dtypep":"(U)","keyword":"bit","generic":true,"rangep": []}, - {"type":"UNPACKARRAYDTYPE","name":"","addr":"(Y)","loc":"d,15:18,15:19","dtypep":"(Y)","isCompound":false,"declRange":"[0:1]","generic":false,"refDTypep":"(Q)","childDTypep": [], + {"type":"UNPACKARRAYDTYPE","name":"","addr":"(Y)","loc":"d,15:18,15:19","dtypep":"(Y)","isCompound":false,"declRange":"[0:1]","generic":false,"signed":true,"refDTypep":"(Q)","childDTypep": [], "rangep": [ {"type":"RANGE","name":"","addr":"(PB)","loc":"d,15:18,15:19","ascending":true,"fromBracket":true, "leftp": [ diff --git a/test_regress/t/t_cover_sys_line_expr.out b/test_regress/t/t_cover_sys_line_expr.out index 5824d5a89..27a3a73fc 100644 --- a/test_regress/t/t_cover_sys_line_expr.out +++ b/test_regress/t/t_cover_sys_line_expr.out @@ -5,12 +5,9 @@ // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 - module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; + module t ( + input clk + ); int cyc, bump, result; logic foo; @@ -326,7 +323,7 @@ -000000 point: comment=else hier=top.t 000010 cyc <= cyc + 1; +000010 point: comment=block hier=top.t -%000009 if (cyc==9) begin +%000009 if (cyc == 9) begin -000001 point: comment=if hier=top.t -000009 point: comment=else hier=top.t %000001 $write("*-* All Finished *-*\n"); @@ -334,6 +331,6 @@ %000001 $finish; -000001 point: comment=if hier=top.t end - end + end endmodule diff --git a/test_regress/t/t_cover_sys_line_expr.v b/test_regress/t/t_cover_sys_line_expr.v index d83664aa0..02a13b068 100644 --- a/test_regress/t/t_cover_sys_line_expr.v +++ b/test_regress/t/t_cover_sys_line_expr.v @@ -4,12 +4,9 @@ // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; +module t ( + input clk +); int cyc, bump, result; logic foo; @@ -73,9 +70,9 @@ module t (/*AUTOARG*/ if (($sformatf("abc") != "abc") && foo) bump <= bump + 1; if (foo && foo) bump <= bump + 1; cyc <= cyc + 1; - if (cyc==9) begin + if (cyc == 9) begin $write("*-* All Finished *-*\n"); $finish; end - end + end endmodule diff --git a/test_regress/t/t_covergroup_in_class_duplicate_bad.out b/test_regress/t/t_covergroup_in_class_duplicate_bad.out index bebff3b94..448415232 100755 --- a/test_regress/t/t_covergroup_in_class_duplicate_bad.out +++ b/test_regress/t/t_covergroup_in_class_duplicate_bad.out @@ -1,8 +1,8 @@ -%Error: t/t_covergroup_in_class_duplicate_bad.v:13:16: Duplicate declaration of CLASS '__vlAnonCG_embeddedCg': '__vlAnonCG_embeddedCg' - 13 | covergroup embeddedCg; - | ^~~~~~~~~~ - t/t_covergroup_in_class_duplicate_bad.v:9:16: ... Location of original declaration - 9 | covergroup embeddedCg; - | ^~~~~~~~~~ +%Error: t/t_covergroup_in_class_duplicate_bad.v:13:14: Duplicate declaration of CLASS '__vlAnonCG_embeddedCg': '__vlAnonCG_embeddedCg' + 13 | covergroup embeddedCg; + | ^~~~~~~~~~ + t/t_covergroup_in_class_duplicate_bad.v:9:14: ... Location of original declaration + 9 | covergroup embeddedCg; + | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_covergroup_in_class_duplicate_bad.v b/test_regress/t/t_covergroup_in_class_duplicate_bad.v index c94ed0729..c7e7b94eb 100644 --- a/test_regress/t/t_covergroup_in_class_duplicate_bad.v +++ b/test_regress/t/t_covergroup_in_class_duplicate_bad.v @@ -6,11 +6,11 @@ /* verilator lint_off COVERIGN */ class myClass; - covergroup embeddedCg; + covergroup embeddedCg; - endgroup + endgroup - covergroup embeddedCg; + covergroup embeddedCg; - endgroup + endgroup endclass diff --git a/test_regress/t/t_define_override.v b/test_regress/t/t_define_override.v index 6a5eee1ff..5ffb45cb7 100644 --- a/test_regress/t/t_define_override.v +++ b/test_regress/t/t_define_override.v @@ -10,11 +10,10 @@ `define STRINGIFY(x) `"x`" -module test ( -); - initial begin - $display("TEST_MACRO %s", `STRINGIFY(`TEST_MACRO)); - $finish; - end +module test (); + initial begin + $display("TEST_MACRO %s", `STRINGIFY(`TEST_MACRO)); + $finish; + end endmodule diff --git a/test_regress/t/t_delay_1step.v b/test_regress/t/t_delay_1step.v index baa82dcdb..c8f33d7d4 100644 --- a/test_regress/t/t_delay_1step.v +++ b/test_regress/t/t_delay_1step.v @@ -5,13 +5,12 @@ // SPDX-License-Identifier: CC0-1.0 module t; - timeunit 10s; - timeprecision 1s; + timeunit 10s; timeprecision 1s; initial begin #1; if ($time != 1) $stop; - repeat(10) #1step; + repeat (10) #1step; if ($time != 2) $stop; #10; $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_dfg_bin_to_one_hot.v b/test_regress/t/t_dfg_bin_to_one_hot.v index bd27f5b38..260a0a78c 100644 --- a/test_regress/t/t_dfg_bin_to_one_hot.v +++ b/test_regress/t/t_dfg_bin_to_one_hot.v @@ -4,14 +4,14 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop -`define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: cyc=%0d got='h%x exp='h%x\n", `__FILE__,`__LINE__, cyc, (got), (exp)); `stop; end while(0) +`define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: cyc=%0d got='h%x exp='h%x\n", `__FILE__,`__LINE__, cyc, (gotv), (expv)); `stop; end while(0) +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); reg [31:0] cyc = 0; reg [6:0] cntA = 0; diff --git a/test_regress/t/t_dfg_circular_merged_scc.v b/test_regress/t/t_dfg_circular_merged_scc.v index c9ccaddb9..9f976e0b4 100644 --- a/test_regress/t/t_dfg_circular_merged_scc.v +++ b/test_regress/t/t_dfg_circular_merged_scc.v @@ -4,24 +4,28 @@ // any use, without warranty, 2025 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 -module mul (input [8:0] A, input [16:0] B, output [25:0] Y); +module mul ( + input [8:0] A, + input [16:0] B, + output [25:0] Y +); assign Y = $signed(A) * $signed(B); endmodule module A; wire [26:0] C; wire [26:0] D; - wire [8:0] E; + wire [8:0] E; // This yields a circular DFG with a fairly special form that used to trip // decomposition. mul mul ( - .A(9'd10), - .B(17'h0cccd), - .Y({ C[26], C[9:0], D[15:1] }) + .A(9'd10), + .B(17'h0cccd), + .Y({C[26], C[9:0], D[15:1]}) ); - assign E = { C[8:0] }; + assign E = {C[8:0]}; assign C[25:10] = {16{C[26]}}; endmodule diff --git a/test_regress/t/t_dfg_oob_sel_rvalue.v b/test_regress/t/t_dfg_oob_sel_rvalue.v index 0413788b4..e27ad0333 100644 --- a/test_regress/t/t_dfg_oob_sel_rvalue.v +++ b/test_regress/t/t_dfg_oob_sel_rvalue.v @@ -5,16 +5,16 @@ // SPDX-License-Identifier: CC0-1.0 -module t( - input logic [0:0][2:0] i, - output logic o +module t ( + input logic [0:0][2:0] i, + output logic o ); always_comb begin o = 1'b0; // verilator unroll_full - for (int n = 0 ; n < 3; ++n) begin - o = o | i[n] == 3'd0; // Intentionally out of bounds + for (int n = 0; n < 3; ++n) begin + o = o | i[n] == 3'd0; // Intentionally out of bounds end end diff --git a/test_regress/t/t_dfg_regularize_clk.v b/test_regress/t/t_dfg_regularize_clk.v index ed833c7c2..4dc240b79 100644 --- a/test_regress/t/t_dfg_regularize_clk.v +++ b/test_regress/t/t_dfg_regularize_clk.v @@ -4,9 +4,10 @@ // without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop -`define checkd(gotv, - expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module sub ( input clk, diff --git a/test_regress/t/t_dfg_result_var_ext_write.v b/test_regress/t/t_dfg_result_var_ext_write.v index 5ce0e6828..3c41156bf 100644 --- a/test_regress/t/t_dfg_result_var_ext_write.v +++ b/test_regress/t/t_dfg_result_var_ext_write.v @@ -4,8 +4,10 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop -`define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: $time=%0t got='h%x exp='h%x\n", `__FILE__,`__LINE__, $time, (got), (exp)); `stop; end while(0) +`define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: $time=%0t got='h%x exp='h%x\n", `__FILE__,`__LINE__, $time, (gotv), (expv)); `stop; end while(0) +// verilog_format: on module top; diff --git a/test_regress/t/t_dfg_true_cycle_bad.out b/test_regress/t/t_dfg_true_cycle_bad.out index 9ab0466c3..ca504772f 100644 --- a/test_regress/t/t_dfg_true_cycle_bad.out +++ b/test_regress/t/t_dfg_true_cycle_bad.out @@ -4,6 +4,6 @@ ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message. t/t_dfg_true_cycle_bad.v:10:23: Example path: o - t/t_dfg_true_cycle_bad.v:12:22: Example path: ASSIGNW + t/t_dfg_true_cycle_bad.v:12:20: Example path: ASSIGNW t/t_dfg_true_cycle_bad.v:10:23: Example path: o %Error: Exiting due to diff --git a/test_regress/t/t_dfg_true_cycle_bad.v b/test_regress/t/t_dfg_true_cycle_bad.v index 26791e7d0..98186cdb4 100644 --- a/test_regress/t/t_dfg_true_cycle_bad.v +++ b/test_regress/t/t_dfg_true_cycle_bad.v @@ -6,11 +6,11 @@ `default_nettype none -module t( +module t ( output wire [9:0] o ); - assign o[1:0] = o[9:8]; - assign o[3:2] = o[1:0]; - assign o[7:4] = 4'(o[3:2]); - assign o[9:8] = o[5:4]; + assign o[1:0] = o[9:8]; + assign o[3:2] = o[1:0]; + assign o[7:4] = 4'(o[3:2]); + assign o[9:8] = o[5:4]; endmodule diff --git a/test_regress/t/t_disable_bad.out b/test_regress/t/t_disable_bad.out index 35f743a9b..d708f635c 100644 --- a/test_regress/t/t_disable_bad.out +++ b/test_regress/t/t_disable_bad.out @@ -1,8 +1,8 @@ -%Error: t/t_disable_bad.v:9:15: Can't find definition of block/task: 'abcd' - 9 | disable abcd; - | ^~~~ +%Error: t/t_disable_bad.v:9:13: Can't find definition of block/task: 'abcd' + 9 | disable abcd; + | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: Internal Error: t/t_disable_bad.v:9:7: ../V3LinkJump.cpp:#: Unlinked disable statement - 9 | disable abcd; - | ^~~~~~~ +%Error: Internal Error: t/t_disable_bad.v:9:5: ../V3LinkJump.cpp:#: Unlinked disable statement + 9 | disable abcd; + | ^~~~~~~ ... This fatal error may be caused by the earlier error(s); resolve those first. diff --git a/test_regress/t/t_disable_bad.v b/test_regress/t/t_disable_bad.v index b056b1b7f..4d867b2da 100644 --- a/test_regress/t/t_disable_bad.v +++ b/test_regress/t/t_disable_bad.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - disable abcd; - end -endmodule: t + initial begin + disable abcd; + end +endmodule : t diff --git a/test_regress/t/t_disable_inside.v b/test_regress/t/t_disable_inside.v index 9b956abfc..3292a3ef0 100644 --- a/test_regress/t/t_disable_inside.v +++ b/test_regress/t/t_disable_inside.v @@ -10,7 +10,7 @@ module t; fork : fork_blk begin #1; - disable fork_blk; // Disables both forked processes + disable fork_blk; // Disables both forked processes $stop; end begin @@ -32,7 +32,7 @@ module t; fork begin : fork_branch #1; - disable fork_branch; // Disables only this branch of the fork + disable fork_branch; // Disables only this branch of the fork $stop; end begin diff --git a/test_regress/t/t_display_merge.py b/test_regress/t/t_display_merge.py index 21d0b3b95..43eefcbe0 100755 --- a/test_regress/t/t_display_merge.py +++ b/test_regress/t/t_display_merge.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('simulator_st') -test.compile(verilator_flags2=["--stats"]) +test.compile(verilator_flags2=["--stats", "--inline-cfuncs", "0"]) test.execute(expect_filename=test.golden_filename) diff --git a/test_regress/t/t_dist_warn_coverage.py b/test_regress/t/t_dist_warn_coverage.py index 35a6bb608..0e601d4f0 100755 --- a/test_regress/t/t_dist_warn_coverage.py +++ b/test_regress/t/t_dist_warn_coverage.py @@ -18,82 +18,115 @@ Suppressed = {} for s in [ # Cannot hit, and comment as to why # Instead of adding here, consider adding a LCOV_EXCL_LINE/START/STOP to the sources on the message - ' exited with ', # Is hit; driver.py filters out - ' loading non-variable', # Instead 'storing to parameter' or syntax error + 'exited with', # Is hit; driver.py filters out + 'loading non-variable', # Instead 'storing to parameter' or syntax error + 'does not allow ' + ' in the middle of literal', # Is covered, this parser misses it due to quote 'Assigned pin is neither input nor output', # Instead earlier error 'Define missing argument \'', # Instead get Define passed too many arguments 'Define or directive not defined: `', # Instead V3ParseImp will warn - 'Expecting define formal arguments. Found: ', # Instead define syntax error - 'Syntax error: Range \':\', \'+:\' etc are not allowed in the instance ', # Instead get syntax error + 'Expecting define formal arguments. Found:', # Instead define syntax error + 'Syntax error: Range \':\', \'+:\' etc are not allowed in the instance', # Instead get syntax error 'dynamic new() not expected in this context (expected under an assign)', # Instead get syntax error # Not yet analyzed - '--pipe-filter protocol error, unexpected: ', + '$VERILATOR_ROOT needs to be in environment', + '--pipe-filter protocol error, unexpected:', '--pipe-filter returned bad status', - 'Array initialization has too few elements, need element ', + '--pipe-filter: stdin/stdout closed before pipe opened', + '--pipe-filter: write to closed file', + 'Array initialization has too few elements, need element', + 'Assigning >32 bit to unranged parameter (defaults to 32 bits)', 'Assignment pattern with no members', - 'Can\'t find varpin scope of ', - 'Can\'t read annotation file: ', + 'Can\'t find varpin scope of', + 'Can\'t read annotation file:', 'Can\'t resolve module reference: \'', - 'Can\'t write file: ', - 'Expected data type, not a ', + 'Can\'t write file:', + 'Circular logic when ordering code (non-cutable edge loop)', + 'Expected data type, not a', 'Extern declaration\'s scope is not a defined class', - 'File not found: ', + 'File not found:', 'Format to $display-like function must have constant format string', - 'Forward typedef used as class/package does not resolve to class/package: ', - 'Illegal +: or -: select; type already selected, or bad dimension: ', - 'Illegal bit or array select; type already selected, or bad dimension: ', - 'Illegal range select; type already selected, or bad dimension: ', - 'Interface port declaration ', - 'Modport item is not a function/task: ', - 'Modport item is not a variable: ', + 'Forward typedef used as class/package does not resolve to class/package:', + 'Illegal +: or -: select; type already selected, or bad dimension:', + 'Illegal bit or array select; type already selected, or bad dimension:', + 'Illegal range select; type already selected, or bad dimension:', + 'Instance pin connected by name with empty reference:', + 'Interface port declaration', + 'Invalid reference: Process might outlive variable', + 'Modport item is not a function/task:', + 'Modport item is not a variable:', 'Modport not referenced as .', - 'Modport not referenced from underneath an interface: ', - 'Non-interface used as an interface: ', - 'Parameter type pin value isn\'t a type: Param ', - 'Parameter type variable isn\'t a type: Param ', + 'Modport not referenced from underneath an interface:', + 'Need $SYSTEMC_INCLUDE in environment or when Verilator configured,', + 'Non-interface used as an interface:', + 'Parameter type pin value isn\'t a type: Param', + 'Parameter type variable isn\'t a type: Param', 'Pattern replication value of 0 is not legal.', 'Signals inside functions/tasks cannot be marked forceable', 'Slice size cannot be zero.', - 'Slices of arrays in assignments have different unpacked dimensions, ', - 'String of ', - 'Symbol matching ', + 'Slices of arrays in assignments have different unpacked dimensions,', + 'String of', + 'Symbol matching', 'Unexpected connection to arrayed port', 'Unsized numbers/parameters not allowed in streams.', - 'Unsupported RHS tristate construct: ', + 'Unsupported (or syntax error): Foreach on this array\'s construct', + 'Unsupported LHS node type in array assignment', + 'Unsupported RHS tristate construct:', 'Unsupported or syntax error: Unsized range in instance or other declaration', 'Unsupported pullup/down (weak driver) construct.', - 'Unsupported tristate port expression: ', + 'Unsupported tristate construct (not in propagation graph):', + 'Unsupported tristate port expression:', + 'Unsupported/unknown built-in queue method', 'Unsupported: $bits for queue', 'Unsupported: &&& expression', 'Unsupported: 4-state numbers in this context', + 'Unsupported: Assignments with signal strength with LHS of type:', 'Unsupported: Bind with instance list', - 'Unsupported: Concatenation to form ', - 'Unsupported: Modport dotted port name', + 'Unsupported: Cannot detect changes on expression of complex type', + 'Unsupported: Cast to', + 'Unsupported: Concatenation to form', + 'Unsupported: Creating tristate signal not underneath a module:', + 'Unsupported: Default value on module inout/ref/constref:', + 'Unsupported: Modport empty expression', 'Unsupported: Modport export with prototype', 'Unsupported: Modport import with prototype', + 'Unsupported: Non-constant default value in missing argument', + 'Unsupported: Non-constant index when passing interface to module', 'Unsupported: Only one PSL clock allowed per assertion', - 'Unsupported: Per-bit array instantiations ', - 'Unsupported: Public functions with >64 bit outputs; ', - 'Unsupported: Replication to form ', + 'Unsupported: Per-bit array instantiations', + 'Unsupported: Public functions with >64 bit outputs;', + 'Unsupported: Public functions with return > 64 bits wide.', + 'Unsupported: Release statement argument is too complex array select', + 'Unsupported: Replication to form', + 'Unsupported: Shifting of by over 32-bit number isn\'t supported.', 'Unsupported: Size-changing cast on non-basic data type', 'Unsupported: Slice of non-constant bounds', + 'Unsupported: Stream operation on a variable of a type', 'Unsupported: Unclocked assertion', + 'Unsupported: Using --protect-ids with public function', 'Unsupported: Verilog 1995 deassign', - 'Unsupported: Verilog 1995 gate primitive: ', + 'Unsupported: Verilog 1995 gate primitive:', 'Unsupported: [] dimensions', 'Unsupported: \'default :/\' constraint', 'Unsupported: \'{} .* patterns', 'Unsupported: assertion items in clocking blocks', - 'Unsupported: don\'t know how to deal with ', + 'Unsupported: don\'t know how to deal with', + 'Unsupported: extern constraint definition with class-in-class', 'Unsupported: extern forkjoin', 'Unsupported: extern task', 'Unsupported: modport export', 'Unsupported: no_inline for tasks', + 'Unsupported: non-const assert directive type expression', 'Unsupported: property port \'local\'', + 'Unsupported: randsequence production function variable', 'Unsupported: repeat event control', - 'Unsupported: static cast to ', + 'Unsupported: static cast to', 'Unsupported: super', 'Unsupported: with[] stream expression', + 'expected non-complex non-double', + 'is not an unpacked array, but is in an unpacked array context', + 'loading other than unpacked-array variable', + 'loading other than unpacked/associative-array variable', ]: Suppressed[s] = True @@ -106,7 +139,8 @@ def read_messages(): continue with open(filename, 'r', encoding="utf8") as fh: lineno = 0 - read_next = None + statement = "" + statement_lineno = 0 excl = False excl_next = False @@ -118,36 +152,52 @@ def read_messages(): if re.match(r'^\s*/\*', line): continue excl = excl_next + # print(('C ' if (statement != "") else 'L') + line) + if 'LCOV_EXCL_START' in line: excl = True excl_next = True if 'LCOV_EXCL_STOP' in line: excl_next = False # Reenables coverage on next line, not this one - if re.search(r'\b(v3error|v3warn|v3fatal|BBUNSUP)\b\($', line): - if 'LCOV_EXCL_LINE' not in line: - read_next = True + if 'LCOV_EXCL_LINE' in line: + excl = True + if excl: + statement = "" continue - m = re.search(r'.*\b(v3error|v3warn|v3fatal|BBUNSUP)\b(.*)', line) + + line = re.sub(r'\\n', '', line) + line = re.sub(r'\s+//.*', '', line) + line = line.rstrip() + + m = re.search(r'\b((v3error|v3warn|v3fatal|BBUNSUP)\b.*)', line) if m: - line = m.group(2) - if 'LCOV_EXCL_LINE' not in line: - read_next = True - if read_next: - read_next = False - if 'LCOV_EXCL_LINE' in line: - continue - if excl: - continue - if "\\" in line: # \" messes up next part - continue - m = re.search(r'"([^"]*)"', line) - if m: - msg = m.group(1) - fileline = filename + ":" + str(lineno) - # print("FFFF " + fileline + ": " + msg + " LL " + line) - Messages[msg] = {} - Messages[msg]['fileline'] = fileline - Messages[msg]['line'] = origline + statement = m.group(1) + statement_lineno = lineno + + if statement == "": + continue + statement += line + + if ');' not in statement: + continue # Keep reading lines until get end of statement + + if '\\"' in statement: + continue # Parser messes these up + + # print("SSS " + statement) + + m = re.search(r'"([^"]*)"', statement) + if m: + msg = m.group(1) + msg = re.sub(r'\s+$', '', msg) + msg = re.sub(r'^\s+', '', msg) + fileline = filename + ":" + str(statement_lineno) + # print("FFFF " + fileline + ": " + msg + " LL " + statement) + Messages[msg] = {} + Messages[msg]['fileline'] = fileline + Messages[msg]['line'] = statement + + statement = "" print("Number of messages = " + str(len(Messages))) diff --git a/test_regress/t/t_dpi_inline_new.v b/test_regress/t/t_dpi_inline_new.v index c14dc4927..ef8a8dd89 100644 --- a/test_regress/t/t_dpi_inline_new.v +++ b/test_regress/t/t_dpi_inline_new.v @@ -9,8 +9,10 @@ package pyhdl_if; typedef chandle PyObject; - import "DPI-C" context function PyObject _pyhdl_if_PyTuple_GetItem(input PyObject p0, - input longint unsigned p1); + import "DPI-C" context function PyObject _pyhdl_if_PyTuple_GetItem( + input PyObject p0, + input longint unsigned p1 + ); function PyObject PyTuple_GetItem(input PyObject p0, input longint unsigned p1); return _pyhdl_if_PyTuple_GetItem(p0, p1); @@ -32,11 +34,9 @@ package pyhdl_if; endpackage -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); import pyhdl_if::*; diff --git a/test_regress/t/t_dump_json.out b/test_regress/t/t_dump_json.out index ae02480e0..08fc076f9 100644 --- a/test_regress/t/t_dump_json.out +++ b/test_regress/t/t_dump_json.out @@ -9,7 +9,7 @@ ],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"cyc","addr":"(K)","loc":"e,13:12,13:15","dtypep":"UNLINKED","origName":"cyc","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"integer","addr":"(L)","loc":"e,13:4,13:11","dtypep":"(L)","keyword":"integer","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"integer","addr":"(L)","loc":"e,13:4,13:11","dtypep":"(L)","keyword":"integer","range":"31:0","generic":false,"signed":true,"rangep": []} ],"delayp": [], "valuep": [ {"type":"CONST","name":"?32?sh0","addr":"(M)","loc":"e,13:18,13:19","dtypep":"(N)"} @@ -1217,7 +1217,7 @@ {"type":"TYPEDEFFWD","name":"T","addr":"(GS)","loc":"d,34:12,34:13","fwdType":"none"}, {"type":"VAR","name":"m_bound","addr":"(HS)","loc":"d,36:19,36:26","dtypep":"UNLINKED","origName":"m_bound","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(IS)","loc":"d,36:15,36:18","dtypep":"(IS)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(IS)","loc":"d,36:15,36:18","dtypep":"(IS)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"m_queue","addr":"(JS)","loc":"d,37:17,37:24","dtypep":"UNLINKED","origName":"m_queue","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ @@ -1233,7 +1233,7 @@ "stmtsp": [ {"type":"VAR","name":"bound","addr":"(PS)","loc":"d,39:22,39:27","dtypep":"UNLINKED","origName":"bound","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(QS)","loc":"d,39:18,39:21","dtypep":"(QS)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(QS)","loc":"d,39:18,39:21","dtypep":"(QS)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"delayp": [], "valuep": [ {"type":"CONST","name":"?32?sh0","addr":"(RS)","loc":"d,39:30,39:31","dtypep":"(N)"} @@ -1248,7 +1248,7 @@ ],"scopeNamep": []}, {"type":"FUNC","name":"num","addr":"(VS)","loc":"d,43:18,43:21","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"num", "fvarp": [ - {"type":"BASICDTYPE","name":"int","addr":"(WS)","loc":"d,43:14,43:17","dtypep":"(WS)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(WS)","loc":"d,43:14,43:17","dtypep":"(WS)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"classOrPackagep": [], "stmtsp": [ {"type":"RETURN","name":"","addr":"(XS)","loc":"d,44:7,44:13", @@ -1334,7 +1334,7 @@ ],"scopeNamep": []}, {"type":"FUNC","name":"try_put","addr":"(CU)","loc":"d,55:18,55:25","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"try_put", "fvarp": [ - {"type":"BASICDTYPE","name":"int","addr":"(DU)","loc":"d,55:14,55:17","dtypep":"(DU)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(DU)","loc":"d,55:14,55:17","dtypep":"(DU)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"classOrPackagep": [], "stmtsp": [ {"type":"VAR","name":"message","addr":"(EU)","loc":"d,55:28,55:35","dtypep":"UNLINKED","origName":"message","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", @@ -1453,7 +1453,7 @@ ],"scopeNamep": []}, {"type":"FUNC","name":"try_get","addr":"(VV)","loc":"d,72:18,72:25","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"try_get", "fvarp": [ - {"type":"BASICDTYPE","name":"int","addr":"(WV)","loc":"d,72:14,72:17","dtypep":"(WV)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(WV)","loc":"d,72:14,72:17","dtypep":"(WV)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"classOrPackagep": [], "stmtsp": [ {"type":"VAR","name":"message","addr":"(XV)","loc":"d,72:32,72:39","dtypep":"UNLINKED","origName":"message","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", @@ -1557,7 +1557,7 @@ ],"scopeNamep": []}, {"type":"FUNC","name":"try_peek","addr":"(JX)","loc":"d,89:18,89:26","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"try_peek", "fvarp": [ - {"type":"BASICDTYPE","name":"int","addr":"(KX)","loc":"d,89:14,89:17","dtypep":"(KX)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(KX)","loc":"d,89:14,89:17","dtypep":"(KX)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"classOrPackagep": [], "stmtsp": [ {"type":"VAR","name":"message","addr":"(LX)","loc":"d,89:33,89:40","dtypep":"UNLINKED","origName":"message","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", @@ -1606,13 +1606,13 @@ "stmtsp": [ {"type":"VAR","name":"m_keyCount","addr":"(CY)","loc":"d,100:19,100:29","dtypep":"UNLINKED","origName":"m_keyCount","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(DY)","loc":"d,100:15,100:18","dtypep":"(DY)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(DY)","loc":"d,100:15,100:18","dtypep":"(DY)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"delayp": [],"valuep": [],"attrsp": []}, {"type":"FUNC","name":"new","addr":"(EY)","loc":"d,102:14,102:17","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"new","fvarp": [],"classOrPackagep": [], "stmtsp": [ {"type":"VAR","name":"keyCount","addr":"(FY)","loc":"d,102:22,102:30","dtypep":"UNLINKED","origName":"keyCount","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(GY)","loc":"d,102:18,102:21","dtypep":"(GY)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(GY)","loc":"d,102:18,102:21","dtypep":"(GY)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"delayp": [], "valuep": [ {"type":"CONST","name":"?32?sh0","addr":"(HY)","loc":"d,102:33,102:34","dtypep":"(N)"} @@ -1629,7 +1629,7 @@ "stmtsp": [ {"type":"VAR","name":"keyCount","addr":"(MY)","loc":"d,106:27,106:35","dtypep":"UNLINKED","origName":"keyCount","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(NY)","loc":"d,106:23,106:26","dtypep":"(NY)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(NY)","loc":"d,106:23,106:26","dtypep":"(NY)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"delayp": [], "valuep": [ {"type":"CONST","name":"?32?sh1","addr":"(OY)","loc":"d,106:38,106:39","dtypep":"(N)"} @@ -1652,7 +1652,7 @@ "stmtsp": [ {"type":"VAR","name":"keyCount","addr":"(VY)","loc":"d,110:18,110:26","dtypep":"UNLINKED","origName":"keyCount","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(WY)","loc":"d,110:14,110:17","dtypep":"(WY)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(WY)","loc":"d,110:14,110:17","dtypep":"(WY)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"delayp": [], "valuep": [ {"type":"CONST","name":"?32?sh1","addr":"(XY)","loc":"d,110:29,110:30","dtypep":"(N)"} @@ -1699,12 +1699,12 @@ ],"scopeNamep": []}, {"type":"FUNC","name":"try_get","addr":"(NZ)","loc":"d,119:18,119:25","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"try_get", "fvarp": [ - {"type":"BASICDTYPE","name":"int","addr":"(OZ)","loc":"d,119:14,119:17","dtypep":"(OZ)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(OZ)","loc":"d,119:14,119:17","dtypep":"(OZ)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"classOrPackagep": [], "stmtsp": [ {"type":"VAR","name":"keyCount","addr":"(PZ)","loc":"d,119:30,119:38","dtypep":"UNLINKED","origName":"keyCount","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(QZ)","loc":"d,119:26,119:29","dtypep":"(QZ)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(QZ)","loc":"d,119:26,119:29","dtypep":"(QZ)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"delayp": [], "valuep": [ {"type":"CONST","name":"?32?sh1","addr":"(RZ)","loc":"d,119:41,119:42","dtypep":"(N)"} @@ -1753,9 +1753,9 @@ "childDTypep": [ {"type":"DEFIMPLICITDTYPE","name":"__typeimpenum0","addr":"(IAB)","loc":"d,130:13,130:17","dtypep":"UNLINKED","generic":false, "childDTypep": [ - {"type":"ENUMDTYPE","name":"","addr":"(JAB)","loc":"d,130:13,130:17","dtypep":"UNLINKED","enum":true,"generic":false,"refDTypep":"UNLINKED", + {"type":"ENUMDTYPE","name":"","addr":"(JAB)","loc":"d,130:13,130:17","dtypep":"UNLINKED","enum":true,"generic":false,"signed":true,"refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(KAB)","loc":"d,130:18,130:19","dtypep":"(KAB)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(KAB)","loc":"d,130:18,130:19","dtypep":"(KAB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ], "itemsp": [ {"type":"ENUMITEM","name":"FINISHED","addr":"(LAB)","loc":"d,131:7,131:15","dtypep":"UNLINKED","rangep": [], @@ -2025,7 +2025,7 @@ ],"extendsp": []}, {"type":"FUNC","name":"randomize","addr":"(GFB)","loc":"d,242:16,242:25","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"randomize", "fvarp": [ - {"type":"BASICDTYPE","name":"int","addr":"(HFB)","loc":"d,242:12,242:15","dtypep":"(HFB)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(HFB)","loc":"d,242:12,242:15","dtypep":"(HFB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"classOrPackagep": [], "stmtsp": [ {"type":"ASSIGN","name":"","addr":"(IFB)","loc":"d,243:15,243:16","dtypep":"UNLINKED", @@ -2048,11 +2048,11 @@ ],"valuep": []}, {"type":"MEMBERDTYPE","name":"weight","addr":"(QFB)","loc":"d,251:9,251:15","dtypep":"UNLINKED","isConstrainedRand":false,"name":"weight","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(RFB)","loc":"d,251:5,251:8","dtypep":"(RFB)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(RFB)","loc":"d,251:5,251:8","dtypep":"(RFB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"valuep": []}, {"type":"MEMBERDTYPE","name":"goal","addr":"(SFB)","loc":"d,252:9,252:13","dtypep":"UNLINKED","isConstrainedRand":false,"name":"goal","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(TFB)","loc":"d,252:5,252:8","dtypep":"(TFB)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(TFB)","loc":"d,252:5,252:8","dtypep":"(TFB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"valuep": []}, {"type":"MEMBERDTYPE","name":"comment","addr":"(UFB)","loc":"d,253:12,253:19","dtypep":"UNLINKED","isConstrainedRand":false,"name":"comment","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ @@ -2060,15 +2060,15 @@ ],"valuep": []}, {"type":"MEMBERDTYPE","name":"at_least","addr":"(WFB)","loc":"d,254:9,254:17","dtypep":"UNLINKED","isConstrainedRand":false,"name":"at_least","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(XFB)","loc":"d,254:5,254:8","dtypep":"(XFB)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(XFB)","loc":"d,254:5,254:8","dtypep":"(XFB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"valuep": []}, {"type":"MEMBERDTYPE","name":"auto_bin_max","addr":"(YFB)","loc":"d,255:9,255:21","dtypep":"UNLINKED","isConstrainedRand":false,"name":"auto_bin_max","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(ZFB)","loc":"d,255:5,255:8","dtypep":"(ZFB)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(ZFB)","loc":"d,255:5,255:8","dtypep":"(ZFB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"valuep": []}, {"type":"MEMBERDTYPE","name":"cross_num_print_missing","addr":"(AGB)","loc":"d,256:9,256:32","dtypep":"UNLINKED","isConstrainedRand":false,"name":"cross_num_print_missing","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(BGB)","loc":"d,256:5,256:8","dtypep":"(BGB)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(BGB)","loc":"d,256:5,256:8","dtypep":"(BGB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"valuep": []}, {"type":"MEMBERDTYPE","name":"cross_retain_auto_bins","addr":"(CGB)","loc":"d,257:9,257:31","dtypep":"UNLINKED","isConstrainedRand":false,"name":"cross_retain_auto_bins","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ @@ -2097,11 +2097,11 @@ "membersp": [ {"type":"MEMBERDTYPE","name":"weight","addr":"(NGB)","loc":"d,264:9,264:15","dtypep":"UNLINKED","isConstrainedRand":false,"name":"weight","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(OGB)","loc":"d,264:5,264:8","dtypep":"(OGB)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(OGB)","loc":"d,264:5,264:8","dtypep":"(OGB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"valuep": []}, {"type":"MEMBERDTYPE","name":"goal","addr":"(PGB)","loc":"d,265:9,265:13","dtypep":"UNLINKED","isConstrainedRand":false,"name":"goal","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(QGB)","loc":"d,265:5,265:8","dtypep":"(QGB)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(QGB)","loc":"d,265:5,265:8","dtypep":"(QGB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"valuep": []}, {"type":"MEMBERDTYPE","name":"comment","addr":"(RGB)","loc":"d,266:12,266:19","dtypep":"UNLINKED","isConstrainedRand":false,"name":"comment","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ @@ -2109,11 +2109,11 @@ ],"valuep": []}, {"type":"MEMBERDTYPE","name":"at_least","addr":"(TGB)","loc":"d,267:9,267:17","dtypep":"UNLINKED","isConstrainedRand":false,"name":"at_least","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(UGB)","loc":"d,267:5,267:8","dtypep":"(UGB)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(UGB)","loc":"d,267:5,267:8","dtypep":"(UGB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"valuep": []}, {"type":"MEMBERDTYPE","name":"auto_bin_max","addr":"(VGB)","loc":"d,268:9,268:21","dtypep":"UNLINKED","isConstrainedRand":false,"name":"auto_bin_max","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(WGB)","loc":"d,268:5,268:8","dtypep":"(WGB)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(WGB)","loc":"d,268:5,268:8","dtypep":"(WGB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"valuep": []}, {"type":"MEMBERDTYPE","name":"detect_overlap","addr":"(XGB)","loc":"d,269:9,269:23","dtypep":"UNLINKED","isConstrainedRand":false,"name":"detect_overlap","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ @@ -2130,11 +2130,11 @@ "membersp": [ {"type":"MEMBERDTYPE","name":"weight","addr":"(CHB)","loc":"d,273:9,273:15","dtypep":"UNLINKED","isConstrainedRand":false,"name":"weight","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(DHB)","loc":"d,273:5,273:8","dtypep":"(DHB)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(DHB)","loc":"d,273:5,273:8","dtypep":"(DHB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"valuep": []}, {"type":"MEMBERDTYPE","name":"goal","addr":"(EHB)","loc":"d,274:9,274:13","dtypep":"UNLINKED","isConstrainedRand":false,"name":"goal","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(FHB)","loc":"d,274:5,274:8","dtypep":"(FHB)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(FHB)","loc":"d,274:5,274:8","dtypep":"(FHB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"valuep": []}, {"type":"MEMBERDTYPE","name":"comment","addr":"(GHB)","loc":"d,275:12,275:19","dtypep":"UNLINKED","isConstrainedRand":false,"name":"comment","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ @@ -2142,11 +2142,11 @@ ],"valuep": []}, {"type":"MEMBERDTYPE","name":"at_least","addr":"(IHB)","loc":"d,276:9,276:17","dtypep":"UNLINKED","isConstrainedRand":false,"name":"at_least","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(JHB)","loc":"d,276:5,276:8","dtypep":"(JHB)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(JHB)","loc":"d,276:5,276:8","dtypep":"(JHB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"valuep": []}, {"type":"MEMBERDTYPE","name":"cross_num_print_missing","addr":"(KHB)","loc":"d,277:9,277:32","dtypep":"UNLINKED","isConstrainedRand":false,"name":"cross_num_print_missing","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(LHB)","loc":"d,277:5,277:8","dtypep":"(LHB)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(LHB)","loc":"d,277:5,277:8","dtypep":"(LHB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"valuep": []}, {"type":"MEMBERDTYPE","name":"cross_retain_auto_bins","addr":"(MHB)","loc":"d,278:9,278:31","dtypep":"UNLINKED","isConstrainedRand":false,"name":"cross_retain_auto_bins","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ @@ -2163,11 +2163,11 @@ "membersp": [ {"type":"MEMBERDTYPE","name":"weight","addr":"(RHB)","loc":"d,282:9,282:15","dtypep":"UNLINKED","isConstrainedRand":false,"name":"weight","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(SHB)","loc":"d,282:5,282:8","dtypep":"(SHB)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(SHB)","loc":"d,282:5,282:8","dtypep":"(SHB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"valuep": []}, {"type":"MEMBERDTYPE","name":"goal","addr":"(THB)","loc":"d,283:9,283:13","dtypep":"UNLINKED","isConstrainedRand":false,"name":"goal","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(UHB)","loc":"d,283:5,283:8","dtypep":"(UHB)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(UHB)","loc":"d,283:5,283:8","dtypep":"(UHB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"valuep": []}, {"type":"MEMBERDTYPE","name":"comment","addr":"(VHB)","loc":"d,284:12,284:19","dtypep":"UNLINKED","isConstrainedRand":false,"name":"comment","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ @@ -2200,11 +2200,11 @@ "membersp": [ {"type":"MEMBERDTYPE","name":"weight","addr":"(IIB)","loc":"d,292:9,292:15","dtypep":"UNLINKED","isConstrainedRand":false,"name":"weight","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(JIB)","loc":"d,292:5,292:8","dtypep":"(JIB)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(JIB)","loc":"d,292:5,292:8","dtypep":"(JIB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"valuep": []}, {"type":"MEMBERDTYPE","name":"goal","addr":"(KIB)","loc":"d,293:9,293:13","dtypep":"UNLINKED","isConstrainedRand":false,"name":"goal","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(LIB)","loc":"d,293:5,293:8","dtypep":"(LIB)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(LIB)","loc":"d,293:5,293:8","dtypep":"(LIB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"valuep": []}, {"type":"MEMBERDTYPE","name":"comment","addr":"(MIB)","loc":"d,294:12,294:19","dtypep":"UNLINKED","isConstrainedRand":false,"name":"comment","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ @@ -2225,11 +2225,11 @@ "membersp": [ {"type":"MEMBERDTYPE","name":"weight","addr":"(TIB)","loc":"d,299:9,299:15","dtypep":"UNLINKED","isConstrainedRand":false,"name":"weight","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(UIB)","loc":"d,299:5,299:8","dtypep":"(UIB)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(UIB)","loc":"d,299:5,299:8","dtypep":"(UIB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"valuep": []}, {"type":"MEMBERDTYPE","name":"goal","addr":"(VIB)","loc":"d,300:9,300:13","dtypep":"UNLINKED","isConstrainedRand":false,"name":"goal","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(WIB)","loc":"d,300:5,300:8","dtypep":"(WIB)","keyword":"int","range":"31:0","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(WIB)","loc":"d,300:5,300:8","dtypep":"(WIB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} ],"valuep": []}, {"type":"MEMBERDTYPE","name":"comment","addr":"(XIB)","loc":"d,301:12,301:19","dtypep":"UNLINKED","isConstrainedRand":false,"name":"comment","tag":"","generic":false,"refDTypep":"UNLINKED", "childDTypep": [ @@ -2243,21 +2243,21 @@ "miscsp": [ {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(ZT)", "typesp": [ - {"type":"BASICDTYPE","name":"integer","addr":"(NS)","loc":"d,37:25,37:26","dtypep":"(NS)","keyword":"integer","range":"31:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(N)","loc":"d,39:30,39:31","dtypep":"(N)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"integer","addr":"(NS)","loc":"d,37:25,37:26","dtypep":"(NS)","keyword":"integer","range":"31:0","generic":true,"signed":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(N)","loc":"d,39:30,39:31","dtypep":"(N)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(YE)","loc":"d,49:22,49:24","dtypep":"(YE)","keyword":"logic","generic":true,"rangep": []}, {"type":"VOIDDTYPE","name":"","addr":"(ZT)","loc":"d,51:15,51:24","dtypep":"(ZT)","generic":false}, - {"type":"BASICDTYPE","name":"logic","addr":"(UD)","loc":"d,133:17,133:18","dtypep":"(UD)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(VAB)","loc":"d,135:16,135:17","dtypep":"(VAB)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(UD)","loc":"d,133:17,133:18","dtypep":"(UD)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(VAB)","loc":"d,135:16,135:17","dtypep":"(VAB)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(JCB)","loc":"d,168:14,168:53","dtypep":"(JCB)","keyword":"logic","range":"295:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"string","addr":"(FG)","loc":"d,168:7,168:13","dtypep":"(FG)","keyword":"string","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(S)","loc":"e,14:9,14:11","dtypep":"(S)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(DB)","loc":"e,18:10,18:12","dtypep":"(DB)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(S)","loc":"e,14:9,14:11","dtypep":"(S)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(DB)","loc":"e,18:10,18:12","dtypep":"(DB)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(QC)","loc":"e,33:26,33:31","dtypep":"(QC)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(NC)","loc":"e,33:25,33:26","dtypep":"(NC)","keyword":"logic","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(EF)","loc":"e,45:17,45:38","dtypep":"(EF)","keyword":"logic","range":"63:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(NF)","loc":"e,48:22,48:24","dtypep":"(NF)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(WF)","loc":"e,51:22,51:24","dtypep":"(WF)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(NF)","loc":"e,48:22,48:24","dtypep":"(NF)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(WF)","loc":"e,51:22,51:24","dtypep":"(WF)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(HG)","loc":"e,54:17,54:49","dtypep":"(HG)","keyword":"logic","range":"231:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"QData","addr":"(JG)","loc":"e,54:51,54:56","dtypep":"(JG)","keyword":"QData","range":"63:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(AH)","loc":"e,59:17,59:41","dtypep":"(AH)","keyword":"logic","range":"167:0","generic":true,"rangep": []} diff --git a/test_regress/t/t_event_control_expr_unsup.out b/test_regress/t/t_event_control_expr_unsup.out index 310e7c6ec..baff85dd0 100644 --- a/test_regress/t/t_event_control_expr_unsup.out +++ b/test_regress/t/t_event_control_expr_unsup.out @@ -1,5 +1,5 @@ -%Error-UNSUPPORTED: t/t_event_control_expr_unsup.v:15:21: Unsupported: Impure function calls in sensitivity lists - 15 | always @(posedge foo()); - | ^~~ +%Error-UNSUPPORTED: t/t_event_control_expr_unsup.v:15:20: Unsupported: Impure function calls in sensitivity lists + 15 | always @(posedge foo()); + | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_event_control_expr_unsup.v b/test_regress/t/t_event_control_expr_unsup.v index 4cbfe594c..7a89dfa30 100644 --- a/test_regress/t/t_event_control_expr_unsup.v +++ b/test_regress/t/t_event_control_expr_unsup.v @@ -5,13 +5,13 @@ // SPDX-License-Identifier: CC0-1.0 module t; - int x; + int x; - function bit foo; - x += 1; - return bit'(x % 2); - endfunction + function bit foo; + x += 1; + return bit'(x % 2); + endfunction - always @(posedge foo()); + always @(posedge foo()); endmodule diff --git a/test_regress/t/t_expr_shortcircuit.v b/test_regress/t/t_expr_shortcircuit.v index f3960ce4c..61b175d55 100644 --- a/test_regress/t/t_expr_shortcircuit.v +++ b/test_regress/t/t_expr_shortcircuit.v @@ -4,12 +4,9 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; +module t ( + input clk +); int cyc = 0; @@ -20,8 +17,7 @@ module t (/*AUTOARG*/ endfunction always_ff @(posedge clk) begin - if (cyc[0] == 1'b0 || is_odd(cyc)) - cyc <= cyc + 1; + if (cyc[0] == 1'b0 || is_odd(cyc)) cyc <= cyc + 1; if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_flag_unroll_limit_const.out b/test_regress/t/t_flag_unroll_limit_const.out index 86f4a5bed..d04b5fdbd 100644 --- a/test_regress/t/t_flag_unroll_limit_const.out +++ b/test_regress/t/t_flag_unroll_limit_const.out @@ -1,9 +1,9 @@ -%Error: t/t_flag_unroll_limit_const.v:17:16: Expecting expression to be constant, but can't determine constant for FUNCREF 'f' +%Error: t/t_flag_unroll_limit_const.v:17:19: Expecting expression to be constant, but can't determine constant for FUNCREF 'f' : ... note: In instance 't' t/t_flag_unroll_limit_const.v:9:3: ... Location of non-constant LOOP: Loop simulation took too long; probably this is an infinite loop, otherwise set '--unroll-limit' above 4 - t/t_flag_unroll_limit_const.v:17:16: ... Called from 'f()' with parameters: + t/t_flag_unroll_limit_const.v:17:19: ... Called from 'f()' with parameters: x = ?32?h5 - 17 | output logic[f(5):0] o5 - | ^ + 17 | output logic [f(5):0] o5 + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_flag_unroll_limit_const.v b/test_regress/t/t_flag_unroll_limit_const.v index 56a70124a..129cb4769 100644 --- a/test_regress/t/t_flag_unroll_limit_const.v +++ b/test_regress/t/t_flag_unroll_limit_const.v @@ -12,9 +12,9 @@ function automatic int f(int x); return n; endfunction -module t( - output logic[f(4):0] o4, // Should simulate - output logic[f(5):0] o5 // Should NOT simulate +module t ( + output logic [f(4):0] o4, // Should simulate + output logic [f(5):0] o5 // Should NOT simulate ); endmodule diff --git a/test_regress/t/t_force.v b/test_regress/t/t_force.v index 1cf0d1142..fdcd0103b 100644 --- a/test_regress/t/t_force.v +++ b/test_regress/t/t_force.v @@ -4,9 +4,11 @@ // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t(/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_force_chained.out b/test_regress/t/t_force_chained.out index ddfa52588..e52b51e2b 100644 --- a/test_regress/t/t_force_chained.out +++ b/test_regress/t/t_force_chained.out @@ -1,4 +1,4 @@ -%Error: t/t_force_chained.v:27: got='h0 exp='h00000001 -%Error: t/t_force_chained.v:33: got='h0 exp='h00000002 -%Error: t/t_force_chained.v:40: got='h0 exp='h00000003 -%Error: t/t_force_chained.v:46: got='h0 exp='h00000003 +%Error: t/t_force_chained.v:30: got='h0 exp='h00000001 +%Error: t/t_force_chained.v:36: got='h0 exp='h00000002 +%Error: t/t_force_chained.v:43: got='h0 exp='h00000003 +%Error: t/t_force_chained.v:49: got='h0 exp='h00000003 diff --git a/test_regress/t/t_force_chained.v b/test_regress/t/t_force_chained.v index 9374daf1a..e153980d5 100644 --- a/test_regress/t/t_force_chained.v +++ b/test_regress/t/t_force_chained.v @@ -4,9 +4,12 @@ // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 -`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0) +// verilog_format: off +`define stop // TODO +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on -module t; + module t; reg [1:0] a; wire [1:0] b = 1; bit [1:0] c; diff --git a/test_regress/t/t_force_complex_sel_unsup.out b/test_regress/t/t_force_complex_sel_unsup.out index 0643f7fd4..9ea437eee 100644 --- a/test_regress/t/t_force_complex_sel_unsup.out +++ b/test_regress/t/t_force_complex_sel_unsup.out @@ -1,10 +1,10 @@ -%Error-UNSUPPORTED: t/t_force_complex_sel_unsup.v:37:22: Unsupported: Force / release statement with complex select expression +%Error-UNSUPPORTED: t/t_force_complex_sel_unsup.v:41:22: Unsupported: Force / release statement with complex select expression : ... note: In instance 't' - 37 | force logic_arr[($c(1))] = 0; + 41 | force logic_arr[($c(1))] = 0; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_force_complex_sel_unsup.v:44:24: Unsupported: Force / release statement with complex select expression +%Error-UNSUPPORTED: t/t_force_complex_sel_unsup.v:51:24: Unsupported: Force / release statement with complex select expression : ... note: In instance 't' - 44 | release logic_arr[($c(1))]; + 51 | release logic_arr[($c(1))]; | ^ %Error: Exiting due to diff --git a/test_regress/t/t_force_complex_sel_unsup.v b/test_regress/t/t_force_complex_sel_unsup.v index d9c243a08..cefad335c 100644 --- a/test_regress/t/t_force_complex_sel_unsup.v +++ b/test_regress/t/t_force_complex_sel_unsup.v @@ -4,9 +4,11 @@ // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on `ifdef VERILATOR // The '$c(1)' is there to prevent inlining of the signal by V3Gate @@ -31,23 +33,31 @@ module t ( /*AUTOARG*/ cyc <= cyc + 1; if (cyc == 0) begin logic_arr[`IMPURE_ONE] <= 1; - end else if (cyc == 1) begin + end + else if (cyc == 1) begin `checkh(logic_arr[`IMPURE_ONE], 1); - end else if (cyc == 2) begin + end + else if (cyc == 2) begin force logic_arr[`IMPURE_ONE] = 0; - end else if (cyc == 3) begin + end + else if (cyc == 3) begin `checkh(logic_arr[`IMPURE_ONE], 0); logic_arr[`IMPURE_ONE] <= 1; - end else if (cyc == 4) begin + end + else if (cyc == 4) begin `checkh(logic_arr[`IMPURE_ONE], 0); - end else if (cyc == 5) begin + end + else if (cyc == 5) begin release logic_arr[`IMPURE_ONE]; - end else if (cyc == 6) begin + end + else if (cyc == 6) begin `checkh(logic_arr[`IMPURE_ONE], 0); logic_arr[`IMPURE_ONE] <= 1; - end else if (cyc == 7) begin + end + else if (cyc == 7) begin `checkh(logic_arr[`IMPURE_ONE], 1); - end else if (cyc == 8) begin + end + else if (cyc == 8) begin $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_force_func.out b/test_regress/t/t_force_func.out index 7ecdbb3c0..e5f197a92 100644 --- a/test_regress/t/t_force_func.out +++ b/test_regress/t/t_force_func.out @@ -1,4 +1,4 @@ -%Error: t/t_force_func.v:26: got='h0 exp='h00000001 -%Error: t/t_force_func.v:34: got='h0 exp='h00000002 -%Error: t/t_force_func.v:39: got='h0 exp='h00000003 -%Error: t/t_force_func.v:43: got='h0 exp='h00000003 +%Error: t/t_force_func.v:29: got='h0 exp='h00000001 +%Error: t/t_force_func.v:37: got='h0 exp='h00000002 +%Error: t/t_force_func.v:42: got='h0 exp='h00000003 +%Error: t/t_force_func.v:46: got='h0 exp='h00000003 diff --git a/test_regress/t/t_force_func.v b/test_regress/t/t_force_func.v index 91b019421..a09453610 100644 --- a/test_regress/t/t_force_func.v +++ b/test_regress/t/t_force_func.v @@ -4,9 +4,12 @@ // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 -`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0) +// verilog_format: off +`define stop // TODO +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on -function bit [1:0] get_arg (bit [1:0] x); + function bit [1:0] get_arg (bit [1:0] x); return x; endfunction diff --git a/test_regress/t/t_force_immediate_release.v b/test_regress/t/t_force_immediate_release.v index ce54f467f..0debeeb65 100644 --- a/test_regress/t/t_force_immediate_release.v +++ b/test_regress/t/t_force_immediate_release.v @@ -4,8 +4,10 @@ // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on module t; diff --git a/test_regress/t/t_force_initial.v b/test_regress/t/t_force_initial.v index d909c07ce..93f52c25c 100644 --- a/test_regress/t/t_force_initial.v +++ b/test_regress/t/t_force_initial.v @@ -4,9 +4,12 @@ // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 -`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0) +// verilog_format: off +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on -module t; + module t; reg [1:0] a = 0; reg [1:0] b = 2; diff --git a/test_regress/t/t_force_mid.v b/test_regress/t/t_force_mid.v index f630466a8..ce9d67435 100644 --- a/test_regress/t/t_force_mid.v +++ b/test_regress/t/t_force_mid.v @@ -4,8 +4,10 @@ // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on module t(/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_force_multi.v b/test_regress/t/t_force_multi.v index 30e3fbd88..5ab3a10ce 100644 --- a/test_regress/t/t_force_multi.v +++ b/test_regress/t/t_force_multi.v @@ -4,8 +4,10 @@ // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on module t(/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_force_port_inline.v b/test_regress/t/t_force_port_inline.v index 062ddb88c..8be1995c6 100644 --- a/test_regress/t/t_force_port_inline.v +++ b/test_regress/t/t_force_port_inline.v @@ -4,8 +4,10 @@ // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on module sub( input wire [7:0] i, diff --git a/test_regress/t/t_force_readwrite.v b/test_regress/t/t_force_readwrite.v index 202bfb408..3272b9e01 100644 --- a/test_regress/t/t_force_readwrite.v +++ b/test_regress/t/t_force_readwrite.v @@ -13,7 +13,7 @@ module t; logic a; logic b = 1; logic c; - Cls cls = new; + Cls cls = new; initial begin force a = b; diff --git a/test_regress/t/t_force_readwrite_unsup.v b/test_regress/t/t_force_readwrite_unsup.v index e3f8074b0..11bc3ce8a 100644 --- a/test_regress/t/t_force_readwrite_unsup.v +++ b/test_regress/t/t_force_readwrite_unsup.v @@ -18,7 +18,7 @@ endclass module t; logic a; logic b = 1; - Cls cls = new; + Cls cls = new; initial begin force a = b; diff --git a/test_regress/t/t_force_release.out b/test_regress/t/t_force_release.out index 86850b874..11b13fbac 100644 --- a/test_regress/t/t_force_release.out +++ b/test_regress/t/t_force_release.out @@ -1,4 +1,4 @@ 0 d=0,e=0 10 d=1,e=1 20 d=1,e=0 -%Error: t/t_force_release.v:36: got='h1 exp='h00000000 +%Error: t/t_force_release.v:39: got='h1 exp='h00000000 diff --git a/test_regress/t/t_force_release.v b/test_regress/t/t_force_release.v index 6fd13338d..7dbff39c2 100644 --- a/test_regress/t/t_force_release.v +++ b/test_regress/t/t_force_release.v @@ -4,11 +4,14 @@ // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 -`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0) +// verilog_format: off +`define stop // TODO +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on // Example from IEEE 1800-2023 10.6.2 -module t; + module t; logic a, b, c, d; wire e; and and1 (e, a, b, c); diff --git a/test_regress/t/t_force_release_net.v b/test_regress/t/t_force_release_net.v index b91df1085..6bf47e073 100644 --- a/test_regress/t/t_force_release_net.v +++ b/test_regress/t/t_force_release_net.v @@ -4,8 +4,10 @@ // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_force_release_var.v b/test_regress/t/t_force_release_var.v index 6f2791e63..0790cc752 100644 --- a/test_regress/t/t_force_release_var.v +++ b/test_regress/t/t_force_release_var.v @@ -4,8 +4,10 @@ // any use, without warranty, 2021 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_force_rhs_ref.v b/test_regress/t/t_force_rhs_ref.v index a6515bec1..069adb0cf 100644 --- a/test_regress/t/t_force_rhs_ref.v +++ b/test_regress/t/t_force_rhs_ref.v @@ -4,8 +4,10 @@ // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on module t; reg [1:0] a; diff --git a/test_regress/t/t_force_rhs_ref_multi_lhs.v b/test_regress/t/t_force_rhs_ref_multi_lhs.v index 10711caec..15fc1f711 100644 --- a/test_regress/t/t_force_rhs_ref_multi_lhs.v +++ b/test_regress/t/t_force_rhs_ref_multi_lhs.v @@ -4,8 +4,10 @@ // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on module t; bit [1:0] a; diff --git a/test_regress/t/t_force_rhs_ref_multiple.v b/test_regress/t/t_force_rhs_ref_multiple.v index 84900b7dd..afc2c390d 100644 --- a/test_regress/t/t_force_rhs_ref_multiple.v +++ b/test_regress/t/t_force_rhs_ref_multiple.v @@ -4,8 +4,10 @@ // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on module t; logic [7:0] a = 1; diff --git a/test_regress/t/t_force_struct_partial.v b/test_regress/t/t_force_struct_partial.v index 7490facaa..7e4d452cf 100644 --- a/test_regress/t/t_force_struct_partial.v +++ b/test_regress/t/t_force_struct_partial.v @@ -4,8 +4,10 @@ // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on typedef struct packed { logic sig1; diff --git a/test_regress/t/t_force_subnet.v b/test_regress/t/t_force_subnet.v index 39f82f8ff..893b95096 100644 --- a/test_regress/t/t_force_subnet.v +++ b/test_regress/t/t_force_subnet.v @@ -4,8 +4,10 @@ // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on module t(/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_force_subvar.v b/test_regress/t/t_force_subvar.v index 13726af61..21ebd199e 100644 --- a/test_regress/t/t_force_subvar.v +++ b/test_regress/t/t_force_subvar.v @@ -4,8 +4,10 @@ // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on module t(/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_force_tri.out b/test_regress/t/t_force_tri.out index 9a80c51c3..ec2e7742f 100644 --- a/test_regress/t/t_force_tri.out +++ b/test_regress/t/t_force_tri.out @@ -1,6 +1,6 @@ -%Error-UNSUPPORTED: t/t_force_tri.v:27:10: Unsupported tristate construct: ASSIGNFORCE +%Error-UNSUPPORTED: t/t_force_tri.v:29:10: Unsupported tristate construct: ASSIGNFORCE : ... note: In instance 't' - 27 | force bus = 4'bzz10; + 29 | force bus = 4'bzz10; | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_force_tri.v b/test_regress/t/t_force_tri.v index 62dbd1938..517a4482f 100644 --- a/test_regress/t/t_force_tri.v +++ b/test_regress/t/t_force_tri.v @@ -4,8 +4,10 @@ // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on module t(/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_force_unpacked.v b/test_regress/t/t_force_unpacked.v index 5bf44ed78..1304bbbb4 100644 --- a/test_regress/t/t_force_unpacked.v +++ b/test_regress/t/t_force_unpacked.v @@ -4,15 +4,15 @@ // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on -module t ( /*AUTOARG*/ - // Inputs - clk +module t ( + input clk ); - input clk; integer cyc = 0; diff --git a/test_regress/t/t_force_unpacked_unsup.v b/test_regress/t/t_force_unpacked_unsup.v index ba14be968..b98036d03 100644 --- a/test_regress/t/t_force_unpacked_unsup.v +++ b/test_regress/t/t_force_unpacked_unsup.v @@ -4,15 +4,15 @@ // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on -module t ( /*AUTOARG*/ - // Inputs - clk +module t ( + input clk ); - input clk; integer cyc = 0; diff --git a/test_regress/t/t_foreach_noivar.v b/test_regress/t/t_foreach_noivar.v index 93a804c49..7f5606605 100644 --- a/test_regress/t/t_foreach_noivar.v +++ b/test_regress/t/t_foreach_noivar.v @@ -4,13 +4,15 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; reg [63:0] sum; // Checked not in objects - reg [2:1] [4:3] array [5:6] [7:8]; + reg [2:1][4:3] array[5:6][7:8]; initial begin sum = 0; diff --git a/test_regress/t/t_foreach_noivar_bad.out b/test_regress/t/t_foreach_noivar_bad.out index 2494ada33..0b411572c 100644 --- a/test_regress/t/t_foreach_noivar_bad.out +++ b/test_regress/t/t_foreach_noivar_bad.out @@ -1,11 +1,11 @@ -%Warning-NOEFFECT: t/t_foreach_noivar.v:17:5: foreach with no loop variable has no effect +%Warning-NOEFFECT: t/t_foreach_noivar.v:19:5: foreach with no loop variable has no effect : ... note: In instance 't' - 17 | foreach (array[]) begin + 19 | foreach (array[]) begin | ^~~~~~~ ... For warning description see https://verilator.org/warn/NOEFFECT?v=latest ... Use "/* verilator lint_off NOEFFECT */" and lint_on around source to disable this message. -%Warning-NOEFFECT: t/t_foreach_noivar.v:23:5: foreach with no loop variable has no effect +%Warning-NOEFFECT: t/t_foreach_noivar.v:25:5: foreach with no loop variable has no effect : ... note: In instance 't' - 23 | foreach (array[,,]) begin + 25 | foreach (array[,,]) begin | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_fork_delay.v b/test_regress/t/t_fork_delay.v index 50b19f307..fef847a6e 100644 --- a/test_regress/t/t_fork_delay.v +++ b/test_regress/t/t_fork_delay.v @@ -5,12 +5,12 @@ // SPDX-License-Identifier: CC0-1.0 module t; - integer i=0; + integer i = 0; initial begin fork - i=1; + i = 1; join_none - if(i==1) $stop; + if (i == 1) $stop; $finish; end endmodule diff --git a/test_regress/t/t_fork_delay_finish.v b/test_regress/t/t_fork_delay_finish.v index 5da994438..a36e09a02 100644 --- a/test_regress/t/t_fork_delay_finish.v +++ b/test_regress/t/t_fork_delay_finish.v @@ -7,9 +7,11 @@ module t; bit flag; initial begin - fork begin + fork + begin $stop; - end join_none + end + join_none $finish; end endmodule diff --git a/test_regress/t/t_func_automatic_clear.v b/test_regress/t/t_func_automatic_clear.v index 4f88849e4..5b1dd3ef1 100644 --- a/test_regress/t/t_func_automatic_clear.v +++ b/test_regress/t/t_func_automatic_clear.v @@ -4,9 +4,11 @@ // any use, without warranty, 2025 by Augustin Fabre. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on // Bug5747: Make sure that a variable with automatic storage is freshly // allocated when entering the function. diff --git a/test_regress/t/t_func_call_super_arg.v b/test_regress/t/t_func_call_super_arg.v index e3429ec61..6c2af983c 100644 --- a/test_regress/t/t_func_call_super_arg.v +++ b/test_regress/t/t_func_call_super_arg.v @@ -7,7 +7,7 @@ class base; function new(string name); $display(name); - if(name == "42") $finish; + if (name == "42") $finish; endfunction function string retstr(); diff --git a/test_regress/t/t_func_purification.v b/test_regress/t/t_func_purification.v index cef807bc8..50dd549f3 100644 --- a/test_regress/t/t_func_purification.v +++ b/test_regress/t/t_func_purification.v @@ -14,7 +14,8 @@ module t; if (x) begin if (x) begin return 1; - end else begin + end + else begin $c(""); end return 0; diff --git a/test_regress/t/t_func_virt_new.v b/test_regress/t/t_func_virt_new.v index 149e8b286..b7e0d2b1c 100644 --- a/test_regress/t/t_func_virt_new.v +++ b/test_regress/t/t_func_virt_new.v @@ -4,13 +4,16 @@ // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 -class cl #(type T= int); +class cl #( + type T = int +); function void f(); T obj = new; endfunction endclass virtual class vcl; -endclass; +endclass +; module t; cl #(vcl) c = new; initial begin diff --git a/test_regress/t/t_func_virt_new_bad.out b/test_regress/t/t_func_virt_new_bad.out index 8b1c621bf..3f44029b9 100755 --- a/test_regress/t/t_func_virt_new_bad.out +++ b/test_regress/t/t_func_virt_new_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_func_virt_new_bad.v:9:13: Illegal to call 'new' using an abstract virtual class 'vcl' (IEEE 1800-2023 8.21) - : ... note: In instance 't' - 9 | T obj = new; +%Error: t/t_func_virt_new_bad.v:11:13: Illegal to call 'new' using an abstract virtual class 'vcl' (IEEE 1800-2023 8.21) + : ... note: In instance 't' + 11 | T obj = new; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_func_virt_new_bad.v b/test_regress/t/t_func_virt_new_bad.v index 8424235f4..125cb9c13 100644 --- a/test_regress/t/t_func_virt_new_bad.v +++ b/test_regress/t/t_func_virt_new_bad.v @@ -4,13 +4,16 @@ // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 -class cl #(type T= int); +class cl #( + type T = int +); function void f(); T obj = new; endfunction endclass virtual class vcl; -endclass; +endclass +; module t; cl #(vcl) c = new; initial begin diff --git a/test_regress/t/t_gen_class.v b/test_regress/t/t_gen_class.v index 58628ba58..6fc26c1ba 100644 --- a/test_regress/t/t_gen_class.v +++ b/test_regress/t/t_gen_class.v @@ -4,9 +4,11 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module Child; int ch_value; diff --git a/test_regress/t/t_hier_parm_under.v b/test_regress/t/t_hier_parm_under.v index 76711453b..4d36d0dfb 100644 --- a/test_regress/t/t_hier_parm_under.v +++ b/test_regress/t/t_hier_parm_under.v @@ -6,8 +6,8 @@ module sub; /* verilator hier_block */ - parametrized #(.ARG(1)) parametrized1(); - parametrized #(.ARG(2)) parametrized2(); + parametrized #(.ARG(1)) parametrized1 (); + parametrized #(.ARG(2)) parametrized2 (); initial begin if (parametrized1.ARG != 1) $stop; @@ -17,10 +17,12 @@ module sub; end endmodule -module parametrized #(parameter ARG=0); +module parametrized #( + parameter ARG = 0 +); // This is a parametrized non-hier block under a hier block endmodule module t; - sub sub(); + sub sub (); endmodule diff --git a/test_regress/t/t_inst_nansi_param.v b/test_regress/t/t_inst_nansi_param.v index 7d4c1baa0..52cf4c164 100644 --- a/test_regress/t/t_inst_nansi_param.v +++ b/test_regress/t/t_inst_nansi_param.v @@ -4,7 +4,9 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module sub(i); +module sub ( + i +); parameter N = 3; input [N : 0] i; // Note 3:0 conflicts until parameterize wire [2:0] i; @@ -12,5 +14,5 @@ endmodule module t; wire [2:0] i; - sub #(.N(2)) sub(.i); + sub #(.N(2)) sub (.i); endmodule diff --git a/test_regress/t/t_inst_tree_inl0_pub1.py b/test_regress/t/t_inst_tree_inl0_pub1.py index 3fa932f0e..a8a063375 100755 --- a/test_regress/t/t_inst_tree_inl0_pub1.py +++ b/test_regress/t/t_inst_tree_inl0_pub1.py @@ -14,7 +14,8 @@ test.top_filename = "t/t_inst_tree.v" default_vltmt_threads = test.get_default_vltmt_threads test.compile( - verilator_flags2=['--stats', test.t_dir + "/" + test.name + ".vlt"], + # Disable --inline-cfuncs so functions exist to be combined + verilator_flags2=['--stats', '--inline-cfuncs', '0', test.t_dir + "/" + test.name + ".vlt"], # Force 3 threads even if we have fewer cores threads=(default_vltmt_threads if test.vltmt else 1)) diff --git a/test_regress/t/t_interface_array4.v b/test_regress/t/t_interface_array4.v index f3042fa2d..afb4f45c5 100644 --- a/test_regress/t/t_interface_array4.v +++ b/test_regress/t/t_interface_array4.v @@ -24,9 +24,13 @@ class Cls; endtask endclass -module devA (Ifc s); +module devA ( + Ifc s +); endmodule -module devB (Ifc s); +module devB ( + Ifc s +); endmodule module t; diff --git a/test_regress/t/t_interface_gen14.v b/test_regress/t/t_interface_gen14.v index c79823019..0803cc0cd 100644 --- a/test_regress/t/t_interface_gen14.v +++ b/test_regress/t/t_interface_gen14.v @@ -4,31 +4,30 @@ // without warranty. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop -`define checkd(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0d exp=%0d\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on -interface a_if #(parameter int a_param=0)(); - logic[a_param-1:0] x; +interface a_if #( + parameter int a_param = 0 +) (); + logic [a_param-1:0] x; - function void to_if(input logic[a_param-1:0] x_in); + function void to_if(input logic [a_param-1:0] x_in); x = x_in; endfunction - function logic[a_param-1:0] from_if(); + function logic [a_param-1:0] from_if(); return x; endfunction endinterface -module tb(); +module tb (); genvar a; generate - for (a=1; a<3; a++) begin : gen_a - a_if #(.a_param(a)) a_if_a(); + for (a = 1; a < 3; a++) begin : gen_a + a_if #(.a_param(a)) a_if_a (); initial begin #1; a_if_a.to_if(a); diff --git a/test_regress/t/t_interface_modport_expr.out b/test_regress/t/t_interface_modport_expr.out new file mode 100644 index 000000000..277926b00 --- /dev/null +++ b/test_regress/t/t_interface_modport_expr.out @@ -0,0 +1,39 @@ +%Error-UNSUPPORTED: t/t_interface_modport_expr.v:15:22: Unsupported: Modport expressions (IEEE 1800-2023 25.5.4) + 15 | modport mp1(input .a(sig_a), output .b(sig_b)); + | ^ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: t/t_interface_modport_expr.v:15:22: Modport item not found: 'a' + 15 | modport mp1(input .a(sig_a), output .b(sig_b)); + | ^ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error-UNSUPPORTED: t/t_interface_modport_expr.v:15:40: Unsupported: Modport expressions (IEEE 1800-2023 25.5.4) + 15 | modport mp1(input .a(sig_a), output .b(sig_b)); + | ^ +%Error: t/t_interface_modport_expr.v:15:40: Modport item not found: 'b' + 15 | modport mp1(input .a(sig_a), output .b(sig_b)); + | ^ +%Error-UNSUPPORTED: t/t_interface_modport_expr.v:16:22: Unsupported: Modport expressions (IEEE 1800-2023 25.5.4) + 16 | modport mp2(input .a(sig_c), output .b(sig_d)); + | ^ +%Error: t/t_interface_modport_expr.v:16:22: Modport item not found: 'a' + 16 | modport mp2(input .a(sig_c), output .b(sig_d)); + | ^ +%Error-UNSUPPORTED: t/t_interface_modport_expr.v:16:40: Unsupported: Modport expressions (IEEE 1800-2023 25.5.4) + 16 | modport mp2(input .a(sig_c), output .b(sig_d)); + | ^ +%Error: t/t_interface_modport_expr.v:16:40: Modport item not found: 'b' + 16 | modport mp2(input .a(sig_c), output .b(sig_d)); + | ^ +%Error: t/t_interface_modport_expr.v:28:18: Can't find definition of 'a' in dotted variable/method: 'i.a' + 28 | assign i.b = i.a; + | ^ +%Error: t/t_interface_modport_expr.v:28:12: Can't find definition of 'b' in dotted variable/method: 'i.b' + 28 | assign i.b = i.a; + | ^ +%Error: t/t_interface_modport_expr.v:22:18: Can't find definition of 'a' in dotted variable/method: 'i.a' + 22 | assign i.b = i.a; + | ^ +%Error: t/t_interface_modport_expr.v:22:12: Can't find definition of 'b' in dotted variable/method: 'i.b' + 22 | assign i.b = i.a; + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_interface_modport_expr.py b/test_regress/t/t_interface_modport_expr.py new file mode 100755 index 000000000..7a0f86f5e --- /dev/null +++ b/test_regress/t/t_interface_modport_expr.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, + expect_filename=test.golden_filename, + verilator_flags2=["--binary"]) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_modport_expr.v b/test_regress/t/t_interface_modport_expr.v new file mode 100644 index 000000000..112403ef7 --- /dev/null +++ b/test_regress/t/t_interface_modport_expr.v @@ -0,0 +1,46 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2025 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +interface my_if; + logic sig_a, sig_b, sig_c, sig_d; + + modport mp1(input .a(sig_a), output .b(sig_b)); + modport mp2(input .a(sig_c), output .b(sig_d)); +endinterface + +module mod1 ( + my_if.mp1 i +); + assign i.b = i.a; +endmodule + +module mod2 ( + my_if.mp2 i +); + assign i.b = i.a; +endmodule + +module top (); + my_if myIf (); + assign myIf.sig_a = 1'b1, myIf.sig_c = 1'b1; + + mod1 mod1Instance (myIf); + mod2 mod2Instance (myIf); + + initial begin + #1; + `checkh(myIf.sig_a, myIf.sig_b); + `checkh(myIf.sig_c, myIf.sig_d); + #1; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_interface_modport_expr_partsel.out b/test_regress/t/t_interface_modport_expr_partsel.out new file mode 100644 index 000000000..deb4ee46c --- /dev/null +++ b/test_regress/t/t_interface_modport_expr_partsel.out @@ -0,0 +1,39 @@ +%Error-UNSUPPORTED: t/t_interface_modport_expr_partsel.v:16:22: Unsupported: Modport expressions (IEEE 1800-2023 25.5.4) + 16 | modport mp1(input .in(a[7:0]), output .out(b)); + | ^~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: t/t_interface_modport_expr_partsel.v:16:22: Modport item not found: 'in' + 16 | modport mp1(input .in(a[7:0]), output .out(b)); + | ^~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error-UNSUPPORTED: t/t_interface_modport_expr_partsel.v:16:42: Unsupported: Modport expressions (IEEE 1800-2023 25.5.4) + 16 | modport mp1(input .in(a[7:0]), output .out(b)); + | ^~~ +%Error: t/t_interface_modport_expr_partsel.v:16:42: Modport item not found: 'out' + 16 | modport mp1(input .in(a[7:0]), output .out(b)); + | ^~~ +%Error-UNSUPPORTED: t/t_interface_modport_expr_partsel.v:17:22: Unsupported: Modport expressions (IEEE 1800-2023 25.5.4) + 17 | modport mp2(input .in(a[15:8]), output .out(c)); + | ^~ +%Error: t/t_interface_modport_expr_partsel.v:17:22: Modport item not found: 'in' + 17 | modport mp2(input .in(a[15:8]), output .out(c)); + | ^~ +%Error-UNSUPPORTED: t/t_interface_modport_expr_partsel.v:17:43: Unsupported: Modport expressions (IEEE 1800-2023 25.5.4) + 17 | modport mp2(input .in(a[15:8]), output .out(c)); + | ^~~ +%Error: t/t_interface_modport_expr_partsel.v:17:43: Modport item not found: 'out' + 17 | modport mp2(input .in(a[15:8]), output .out(c)); + | ^~~ +%Error: t/t_interface_modport_expr_partsel.v:29:21: Can't find definition of 'in' in dotted variable/method: 'i.in' + 29 | assign i.out = ~i.in; + | ^~ +%Error: t/t_interface_modport_expr_partsel.v:29:12: Can't find definition of 'out' in dotted variable/method: 'i.out' + 29 | assign i.out = ~i.in; + | ^~~ +%Error: t/t_interface_modport_expr_partsel.v:23:20: Can't find definition of 'in' in dotted variable/method: 'i.in' + 23 | assign i.out = i.in; + | ^~ +%Error: t/t_interface_modport_expr_partsel.v:23:12: Can't find definition of 'out' in dotted variable/method: 'i.out' + 23 | assign i.out = i.in; + | ^~~ +%Error: Exiting due to diff --git a/test_regress/t/t_interface_modport_expr_partsel.py b/test_regress/t/t_interface_modport_expr_partsel.py new file mode 100755 index 000000000..7a0f86f5e --- /dev/null +++ b/test_regress/t/t_interface_modport_expr_partsel.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, + expect_filename=test.golden_filename, + verilator_flags2=["--binary"]) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_modport_expr_partsel.v b/test_regress/t/t_interface_modport_expr_partsel.v new file mode 100644 index 000000000..e18b2bb43 --- /dev/null +++ b/test_regress/t/t_interface_modport_expr_partsel.v @@ -0,0 +1,47 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2025 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +interface my_if; + logic [15:0] a; + logic [7:0] b, c; + + modport mp1(input .in(a[7:0]), output .out(b)); + modport mp2(input .in(a[15:8]), output .out(c)); +endinterface + +module mod1 ( + my_if.mp1 i +); + assign i.out = i.in; +endmodule + +module mod2 ( + my_if.mp2 i +); + assign i.out = ~i.in; +endmodule + +module top (); + my_if myIf (); + assign myIf.a = 16'habcd; + + mod1 mod1Instance (myIf); + mod2 mod2Instance (myIf); + + initial begin + #1; + `checkh(myIf.b, myIf.a[7:0]); + `checkh(myIf.c, ~myIf.a[15:8]); + #1; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_interface_param_dependency.v b/test_regress/t/t_interface_param_dependency.v index f90d24a59..94c8af207 100644 --- a/test_regress/t/t_interface_param_dependency.v +++ b/test_regress/t/t_interface_param_dependency.v @@ -7,9 +7,10 @@ // without warranty, 2025 by Paul Swirhun // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop -`define checkd(gotv, - expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on interface TEST_IF #( parameter int FOO = 1, @@ -66,7 +67,7 @@ module submod_assert #( // Test mixed parameters: constant + interface port reference TEST_IF #( - .FOO(7), // Constant parameter + .FOO(7), // Constant parameter .BAR(iface.FOO) // References interface port ) iface_mixed (); @@ -108,7 +109,7 @@ module submod_assert #( // Test BAR-only interface submod_assert2 #( - .EXPECTED_FOO(1), // FOO = default + .EXPECTED_FOO(1), // FOO = default .EXPECTED_BAR(EXPECTED_BAR) // BAR = specified value ) u_bar_only_assert ( .iface(iface_bar_only) @@ -184,7 +185,7 @@ module param_chain #( // Submodule uses interface (FOO=3, BAR should be 30) submod_iface chain_sub ( .result(result), - .iface (chain_iface) + .iface(chain_iface) ); // Assert the chain works correctly @@ -218,19 +219,19 @@ module t; // Test interface as port parameter submod_iface u0 ( .result(result[0]), - .iface (tif_1) + .iface(tif_1) ); submod_iface u1 ( .result(result[1]), - .iface (tif_2) + .iface(tif_2) ); submod_iface u2 ( .result(result[2]), - .iface (tif_3) + .iface(tif_3) ); submod_iface u3 ( .result(result[3]), - .iface (tif_4) + .iface(tif_4) ); // Test modport as port parameter diff --git a/test_regress/t/t_json_only_begin_hier.out b/test_regress/t/t_json_only_begin_hier.out index 771c33e1c..ccc21a73e 100644 --- a/test_regress/t/t_json_only_begin_hier.out +++ b/test_regress/t/t_json_only_begin_hier.out @@ -41,7 +41,7 @@ "miscsp": [ {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"UNLINKED", "typesp": [ - {"type":"BASICDTYPE","name":"integer","addr":"(G)","loc":"d,24:12,24:13","dtypep":"(G)","keyword":"integer","range":"31:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"integer","addr":"(G)","loc":"d,24:12,24:13","dtypep":"(G)","keyword":"integer","range":"31:0","generic":true,"signed":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(V)","loc":"d,13:14,13:20","dtypep":"(V)","keyword":"logic","generic":true,"rangep": []} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", diff --git a/test_regress/t/t_json_only_debugcheck.out b/test_regress/t/t_json_only_debugcheck.out index 55f653fec..bd6608cac 100644 --- a/test_regress/t/t_json_only_debugcheck.out +++ b/test_regress/t/t_json_only_debugcheck.out @@ -2957,7 +2957,7 @@ {"type":"CONST","name":"4'h4","addr":"(SRB)","loc":"d,20:30,20:31","dtypep":"(RB)"} ]} ]}, - {"type":"BASICDTYPE","name":"integer","addr":"(P)","loc":"d,23:4,23:11","dtypep":"(P)","keyword":"integer","range":"31:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"integer","addr":"(P)","loc":"d,23:4,23:11","dtypep":"(P)","keyword":"integer","range":"31:0","generic":true,"signed":true,"rangep": []}, {"type":"REFDTYPE","name":"my_t","addr":"(M)","loc":"d,24:4,24:8","dtypep":"(MRB)","generic":false,"typedefp":"UNLINKED","refDTypep":"(MRB)","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []}, {"type":"BASICDTYPE","name":"string","addr":"(PB)","loc":"d,28:4,28:10","dtypep":"(PB)","keyword":"string","generic":true,"rangep": []}, {"type":"UNPACKARRAYDTYPE","name":"","addr":"(ZB)","loc":"d,17:12,17:16","dtypep":"(ZB)","isCompound":false,"declRange":"[7:0]","generic":false,"refDTypep":"(MRB)","childDTypep": [], @@ -2990,7 +2990,7 @@ {"type":"CONST","name":"32'h0","addr":"(BSB)","loc":"d,17:12,17:16","dtypep":"(EC)"} ]} ]}, - {"type":"BASICDTYPE","name":"logic","addr":"(IB)","loc":"d,23:23,23:24","dtypep":"(IB)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(IB)","loc":"d,23:23,23:24","dtypep":"(IB)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, {"type":"VOIDDTYPE","name":"","addr":"(AB)","loc":"a,0:0,0:0","dtypep":"(AB)","generic":false}, {"type":"BASICDTYPE","name":"bit","addr":"(EN)","loc":"a,0:0,0:0","dtypep":"(EN)","keyword":"bit","range":"63:0","generic":true,"rangep": []}, {"type":"UNPACKARRAYDTYPE","name":"","addr":"(T)","loc":"d,11:8,11:9","dtypep":"(T)","isCompound":false,"declRange":"[0:0]","generic":false,"refDTypep":"(EN)","childDTypep": [], diff --git a/test_regress/t/t_json_only_debugcheck.py b/test_regress/t/t_json_only_debugcheck.py index 810a93a19..5b6b6a7c5 100755 --- a/test_regress/t/t_json_only_debugcheck.py +++ b/test_regress/t/t_json_only_debugcheck.py @@ -14,7 +14,9 @@ test.top_filename = "t/t_enum_type_methods.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" -test.compile(verilator_flags2=['--no-std', '--debug-check', '--no-json-edit-nums', '--flatten'], +test.compile(verilator_flags2=[ + '--no-std', '--debug-check', '--no-json-edit-nums', '--flatten', '--inline-cfuncs', '0' +], verilator_make_gmake=False, make_top_shell=False, make_main=False) diff --git a/test_regress/t/t_json_only_first.out b/test_regress/t/t_json_only_first.out index f3e62d144..876052c83 100644 --- a/test_regress/t/t_json_only_first.out +++ b/test_regress/t/t_json_only_first.out @@ -92,7 +92,7 @@ "typesp": [ {"type":"BASICDTYPE","name":"logic","addr":"(I)","loc":"d,34:24,34:27","dtypep":"(I)","keyword":"logic","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(G)","loc":"d,15:16,15:17","dtypep":"(G)","keyword":"logic","range":"3:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(MB)","loc":"d,19:18,19:19","dtypep":"(MB)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(MB)","loc":"d,19:18,19:19","dtypep":"(MB)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, {"type":"VOIDDTYPE","name":"","addr":"(XB)","loc":"a,0:0,0:0","dtypep":"(XB)","generic":false} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", diff --git a/test_regress/t/t_json_only_flat.out b/test_regress/t/t_json_only_flat.out index eb85d7d29..284efe8f4 100644 --- a/test_regress/t/t_json_only_flat.out +++ b/test_regress/t/t_json_only_flat.out @@ -172,7 +172,7 @@ "typesp": [ {"type":"BASICDTYPE","name":"logic","addr":"(J)","loc":"d,34:24,34:27","dtypep":"(J)","keyword":"logic","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(H)","loc":"d,15:16,15:17","dtypep":"(H)","keyword":"logic","range":"3:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(Q)","loc":"d,19:18,19:19","dtypep":"(Q)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(Q)","loc":"d,19:18,19:19","dtypep":"(Q)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, {"type":"VOIDDTYPE","name":"","addr":"(LD)","loc":"a,0:0,0:0","dtypep":"(LD)","generic":false} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", diff --git a/test_regress/t/t_json_only_flat_vlvbound.out b/test_regress/t/t_json_only_flat_vlvbound.out index f39d40eee..1f7009569 100644 --- a/test_regress/t/t_json_only_flat_vlvbound.out +++ b/test_regress/t/t_json_only_flat_vlvbound.out @@ -309,11 +309,11 @@ {"type":"BASICDTYPE","name":"logic","addr":"(CD)","loc":"d,19:34,19:39","dtypep":"(CD)","keyword":"logic","range":"1:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(H)","loc":"d,9:11,9:16","dtypep":"(H)","keyword":"logic","range":"15:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(K)","loc":"d,11:12,11:17","dtypep":"(K)","keyword":"logic","range":"6:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"integer","addr":"(WB)","loc":"d,17:5,17:12","dtypep":"(WB)","keyword":"integer","range":"31:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(PD)","loc":"d,19:10,19:11","dtypep":"(PD)","keyword":"logic","range":"2:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"integer","addr":"(WB)","loc":"d,17:5,17:12","dtypep":"(WB)","keyword":"integer","range":"31:0","generic":true,"signed":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(PD)","loc":"d,19:10,19:11","dtypep":"(PD)","keyword":"logic","range":"2:0","generic":true,"signed":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(LD)","loc":"d,19:11,19:12","dtypep":"(LD)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(GD)","loc":"d,19:20,19:21","dtypep":"(GD)","keyword":"logic","range":"3:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(RC)","loc":"d,18:12,18:13","dtypep":"(RC)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(GD)","loc":"d,19:20,19:21","dtypep":"(GD)","keyword":"logic","range":"3:0","generic":true,"signed":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(RC)","loc":"d,18:12,18:13","dtypep":"(RC)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, {"type":"VOIDDTYPE","name":"","addr":"(UF)","loc":"a,0:0,0:0","dtypep":"(UF)","generic":false} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", diff --git a/test_regress/t/t_json_only_primary_io.out b/test_regress/t/t_json_only_primary_io.out index 6482cfc3f..7ea175a86 100644 --- a/test_regress/t/t_json_only_primary_io.out +++ b/test_regress/t/t_json_only_primary_io.out @@ -2,56 +2,56 @@ "modulesp": [ {"type":"MODULE","name":"top","addr":"(E)","loc":"d,7:8,7:11","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"top","level":1,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"clk","addr":"(F)","loc":"d,8:9,8:12","dtypep":"(G)","origName":"clk","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"a1","addr":"(H)","loc":"d,9:9,9:11","dtypep":"(G)","origName":"a1","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"a2","addr":"(I)","loc":"d,10:9,10:11","dtypep":"(G)","origName":"a2","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"ready","addr":"(J)","loc":"d,11:10,11:15","dtypep":"(G)","origName":"ready","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"ready_reg","addr":"(K)","loc":"d,13:8,13:17","dtypep":"(G)","origName":"ready_reg","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"CELL","name":"and_cell","addr":"(L)","loc":"d,15:11,15:19","origName":"and_cell","recursive":false,"modp":"(M)", + {"type":"VAR","name":"clk","addr":"(F)","loc":"d,13:9,13:12","dtypep":"(G)","origName":"clk","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"a1","addr":"(H)","loc":"d,14:9,14:11","dtypep":"(G)","origName":"a1","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"a2","addr":"(I)","loc":"d,15:9,15:11","dtypep":"(G)","origName":"a2","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"ready","addr":"(J)","loc":"d,16:10,16:15","dtypep":"(G)","origName":"ready","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"ready_reg","addr":"(K)","loc":"d,18:8,18:17","dtypep":"(G)","origName":"ready_reg","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"CELL","name":"and_cell","addr":"(L)","loc":"d,20:11,20:19","origName":"and_cell","recursive":false,"modp":"(M)", "pinsp": [ - {"type":"PIN","name":"a1","addr":"(N)","loc":"d,16:6,16:8","svDotName":true,"svImplicit":false,"modVarp":"(O)","modPTypep":"UNLINKED", + {"type":"PIN","name":"a1","addr":"(N)","loc":"d,21:8,21:10","svDotName":true,"svImplicit":false,"modVarp":"(O)","modPTypep":"UNLINKED", "exprp": [ - {"type":"VARREF","name":"a1","addr":"(P)","loc":"d,16:9,16:11","dtypep":"(G)","access":"RD","varp":"(H)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"a1","addr":"(P)","loc":"d,21:11,21:13","dtypep":"(G)","access":"RD","varp":"(H)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, - {"type":"PIN","name":"a2","addr":"(Q)","loc":"d,17:6,17:8","svDotName":true,"svImplicit":false,"modVarp":"(R)","modPTypep":"UNLINKED", + {"type":"PIN","name":"a2","addr":"(Q)","loc":"d,22:8,22:10","svDotName":true,"svImplicit":false,"modVarp":"(R)","modPTypep":"UNLINKED", "exprp": [ - {"type":"VARREF","name":"a2","addr":"(S)","loc":"d,17:9,17:11","dtypep":"(G)","access":"RD","varp":"(I)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"a2","addr":"(S)","loc":"d,22:11,22:13","dtypep":"(G)","access":"RD","varp":"(I)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, - {"type":"PIN","name":"zn","addr":"(T)","loc":"d,18:6,18:8","svDotName":true,"svImplicit":false,"modVarp":"(U)","modPTypep":"UNLINKED", + {"type":"PIN","name":"zn","addr":"(T)","loc":"d,23:8,23:10","svDotName":true,"svImplicit":false,"modVarp":"(U)","modPTypep":"UNLINKED", "exprp": [ - {"type":"VARREF","name":"ready_reg","addr":"(V)","loc":"d,18:9,18:18","dtypep":"(G)","access":"WR","varp":"(K)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"ready_reg","addr":"(V)","loc":"d,23:11,23:20","dtypep":"(G)","access":"WR","varp":"(K)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ],"paramsp": [],"rangep": [],"intfRefsp": []}, - {"type":"ALWAYS","name":"","addr":"(W)","loc":"d,21:16,21:17","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(W)","loc":"d,26:16,26:17","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ - {"type":"ASSIGNW","name":"","addr":"(X)","loc":"d,21:16,21:17","dtypep":"(G)", + {"type":"ASSIGNW","name":"","addr":"(X)","loc":"d,26:16,26:17","dtypep":"(G)", "rhsp": [ - {"type":"VARREF","name":"ready_reg","addr":"(Y)","loc":"d,13:8,13:17","dtypep":"(G)","access":"RD","varp":"(K)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"ready_reg","addr":"(Y)","loc":"d,18:8,18:17","dtypep":"(G)","access":"RD","varp":"(K)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "lhsp": [ - {"type":"VARREF","name":"ready","addr":"(Z)","loc":"d,21:16,21:17","dtypep":"(G)","access":"WR","varp":"(J)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"ready","addr":"(Z)","loc":"d,26:16,26:17","dtypep":"(G)","access":"WR","varp":"(J)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]} ]}, - {"type":"MODULE","name":"and2_x1","addr":"(M)","loc":"d,24:8,24:15","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"and2_x1","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"and2_x1","addr":"(M)","loc":"d,29:8,29:15","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"and2_x1","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"a1","addr":"(O)","loc":"d,25:14,25:16","dtypep":"(G)","origName":"a1","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"a2","addr":"(R)","loc":"d,26:14,26:16","dtypep":"(G)","origName":"a2","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"zn","addr":"(U)","loc":"d,27:15,27:17","dtypep":"(G)","origName":"zn","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"ALWAYS","name":"","addr":"(AB)","loc":"d,29:15,29:16","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"VAR","name":"a1","addr":"(O)","loc":"d,30:16,30:18","dtypep":"(G)","origName":"a1","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"a2","addr":"(R)","loc":"d,31:16,31:18","dtypep":"(G)","origName":"a2","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"zn","addr":"(U)","loc":"d,32:17,32:19","dtypep":"(G)","origName":"zn","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"ALWAYS","name":"","addr":"(AB)","loc":"d,34:13,34:14","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ - {"type":"ASSIGNW","name":"","addr":"(BB)","loc":"d,29:15,29:16","dtypep":"(G)", + {"type":"ASSIGNW","name":"","addr":"(BB)","loc":"d,34:13,34:14","dtypep":"(G)", "rhsp": [ - {"type":"AND","name":"","addr":"(CB)","loc":"d,29:21,29:22","dtypep":"(G)", + {"type":"AND","name":"","addr":"(CB)","loc":"d,34:19,34:20","dtypep":"(G)", "lhsp": [ - {"type":"VARREF","name":"a1","addr":"(DB)","loc":"d,25:14,25:16","dtypep":"(G)","access":"RD","varp":"(O)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"a1","addr":"(DB)","loc":"d,30:16,30:18","dtypep":"(G)","access":"RD","varp":"(O)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "rhsp": [ - {"type":"VARREF","name":"a2","addr":"(EB)","loc":"d,26:14,26:16","dtypep":"(G)","access":"RD","varp":"(R)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"a2","addr":"(EB)","loc":"d,31:16,31:18","dtypep":"(G)","access":"RD","varp":"(R)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ], "lhsp": [ - {"type":"VARREF","name":"zn","addr":"(FB)","loc":"d,29:15,29:16","dtypep":"(G)","access":"WR","varp":"(U)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"zn","addr":"(FB)","loc":"d,34:13,34:14","dtypep":"(G)","access":"WR","varp":"(U)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]} ]} @@ -59,7 +59,7 @@ "miscsp": [ {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(GB)", "typesp": [ - {"type":"BASICDTYPE","name":"logic","addr":"(G)","loc":"d,25:14,25:16","dtypep":"(G)","keyword":"logic","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(G)","loc":"d,30:16,30:18","dtypep":"(G)","keyword":"logic","generic":true,"rangep": []}, {"type":"VOIDDTYPE","name":"","addr":"(GB)","loc":"a,0:0,0:0","dtypep":"(GB)","generic":false} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", diff --git a/test_regress/t/t_json_only_primary_io.v b/test_regress/t/t_json_only_primary_io.v index 832cdb87e..578897780 100644 --- a/test_regress/t/t_json_only_primary_io.v +++ b/test_regress/t/t_json_only_primary_io.v @@ -4,7 +4,12 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module top(clk, a1, a2, ready); +module top ( + clk, + a1, + a2, + ready +); input clk; input a1; input a2; @@ -13,18 +18,18 @@ module top(clk, a1, a2, ready); wire ready_reg; and2_x1 and_cell ( - .a1(a1), - .a2(a2), - .zn(ready_reg) + .a1(a1), + .a2(a2), + .zn(ready_reg) ); assign ready = ready_reg; endmodule module and2_x1 ( - input wire a1, - input wire a2, - output wire zn + input wire a1, + input wire a2, + output wire zn ); - assign zn = (a1 & a2); + assign zn = (a1 & a2); endmodule diff --git a/test_regress/t/t_json_only_tag.out b/test_regress/t/t_json_only_tag.out index c902c8fda..8a8395be3 100644 --- a/test_regress/t/t_json_only_tag.out +++ b/test_regress/t/t_json_only_tag.out @@ -53,7 +53,7 @@ {"type":"VAR","name":"value","addr":"(X)","loc":"d,8:12,8:17","dtypep":"(W)","origName":"value","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"MODPORT","name":"out_modport","addr":"(MB)","loc":"d,9:12,9:23", "varsp": [ - {"type":"MODPORTVARREF","name":"value","addr":"(NB)","loc":"d,9:32,9:37","direction":"OUTPUT","varp":"(X)"} + {"type":"MODPORTVARREF","name":"value","addr":"(NB)","loc":"d,9:32,9:37","direction":"OUTPUT","varp":"(X)","exprp": []} ]} ]} ],"filesp": [], @@ -61,7 +61,7 @@ {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(JB)", "typesp": [ {"type":"VOIDDTYPE","name":"","addr":"(JB)","loc":"d,41:7,41:8","dtypep":"(JB)","generic":false}, - {"type":"BASICDTYPE","name":"integer","addr":"(W)","loc":"d,8:4,8:11","dtypep":"(W)","keyword":"integer","range":"31:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"integer","addr":"(W)","loc":"d,8:4,8:11","dtypep":"(W)","keyword":"integer","range":"31:0","generic":true,"signed":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(G)","loc":"d,14:11,14:17","dtypep":"(G)","keyword":"logic","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(OB)","loc":"d,21:7,21:12","dtypep":"(OB)","keyword":"logic","generic":false,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(PB)","loc":"d,22:7,22:12","dtypep":"(PB)","keyword":"logic","generic":false,"rangep": []}, diff --git a/test_regress/t/t_lib_clk_vec.v b/test_regress/t/t_lib_clk_vec.v index ddc4ef3c0..5309766af 100644 --- a/test_regress/t/t_lib_clk_vec.v +++ b/test_regress/t/t_lib_clk_vec.v @@ -11,9 +11,9 @@ localparam int N = 5; `ifdef LIB_CREATE // This is built with --lib-create -module sub( - input logic [N-1:0] clkvec, - output logic [7:0] cnt[N] +module sub ( + input logic [N-1:0] clkvec, + output logic [7:0] cnt[N] ); for (genvar i = 0; i < N; ++i) begin : GEN @@ -30,17 +30,20 @@ endmodule module top; logic [N-1:0] clkvec = N'(0); - logic [7:0] cnt [N]; + logic [7:0] cnt[N]; // Generate clocks by rotation always #5 clkvec = {clkvec[N-2:0], clkvec[N-1] | ~|clkvec}; - sub sub_i(clkvec, cnt); + sub sub_i ( + clkvec, + cnt + ); always @(clkvec) begin #1; $write("%10t %05b", $time, clkvec); - for (int i = N-1; i >= 0; --i) begin + for (int i = N - 1; i >= 0; --i) begin $write(" cnt[%0d]=%02d", i, cnt[i]); end $write("\n"); diff --git a/test_regress/t/t_lint_assigneqexpr.v b/test_regress/t/t_lint_assigneqexpr.v index 0c56cb583..da3fa3f33 100644 --- a/test_regress/t/t_lint_assigneqexpr.v +++ b/test_regress/t/t_lint_assigneqexpr.v @@ -12,7 +12,11 @@ module t ( output logic d_o ); // verilator lint_off PINMISSING - Sub sub (.a_i({a2_i, a1_i, a0_i}), .b_i, .d_o); + Sub sub ( + .a_i({a2_i, a1_i, a0_i}), + .b_i, + .d_o + ); // verilator lint_on PINMISSING endmodule diff --git a/test_regress/t/t_lint_assigneqexpr_bad.out b/test_regress/t/t_lint_assigneqexpr_bad.out index 6c7aab3b8..0b2ab275f 100644 --- a/test_regress/t/t_lint_assigneqexpr_bad.out +++ b/test_regress/t/t_lint_assigneqexpr_bad.out @@ -1,11 +1,11 @@ -%Warning-ASSIGNEQEXPR: t/t_lint_assigneqexpr.v:28:11: Assignment '=' inside expression +%Warning-ASSIGNEQEXPR: t/t_lint_assigneqexpr.v:32:11: Assignment '=' inside expression : ... Was a '==' intended, or suggest use a separate statement - 28 | c_o = 1 + 32 | c_o = 1 | ^ ... For warning description see https://verilator.org/warn/ASSIGNEQEXPR?v=latest ... Use "/* verilator lint_off ASSIGNEQEXPR */" and lint_on around source to disable this message. -%Warning-ASSIGNEQEXPR: t/t_lint_assigneqexpr.v:30:11: Assignment '=' inside expression +%Warning-ASSIGNEQEXPR: t/t_lint_assigneqexpr.v:34:11: Assignment '=' inside expression : ... Was a '==' intended, or suggest use a separate statement - 30 | c_o = 0 + 34 | c_o = 0 | ^ %Error: Exiting due to diff --git a/test_regress/t/t_lint_functimectl_bad.out b/test_regress/t/t_lint_functimectl_bad.out index 4e37bd5a0..6b0fce0da 100644 --- a/test_regress/t/t_lint_functimectl_bad.out +++ b/test_regress/t/t_lint_functimectl_bad.out @@ -1,6 +1,6 @@ %Error-FUNCTIMECTL: t/t_lint_functimectl_bad.v:12:5: Functions cannot contain time-controlling statements (IEEE 1800-2023 13.4) : ... note: In instance 't' - 12 | @e; + 12 | @e; | ^ : ... Suggest make caller 'function calls_timing_ctl' a task 11 | function void calls_timing_ctl; @@ -8,7 +8,7 @@ ... For error description see https://verilator.org/warn/FUNCTIMECTL?v=latest %Error-FUNCTIMECTL: t/t_lint_functimectl_bad.v:17:5: Functions cannot contain time-controlling statements (IEEE 1800-2023 13.4) : ... note: In instance 't' - 17 | wait (s); + 17 | wait (s); | ^~~~ : ... Suggest make caller 'function calls_timing_ctl' a task 11 | function void calls_timing_ctl; diff --git a/test_regress/t/t_lint_functimectl_bad.v b/test_regress/t/t_lint_functimectl_bad.v index b099cd58f..90bbeb1e9 100644 --- a/test_regress/t/t_lint_functimectl_bad.v +++ b/test_regress/t/t_lint_functimectl_bad.v @@ -9,12 +9,12 @@ module t; logic s; function void calls_timing_ctl; - @e; // <--- Bad IEEE 1800-2023 13.4 time-controlling - fork // <--- Bad IEEE 1800-2023 13.4 time-controlling + @e; // <--- Bad IEEE 1800-2023 13.4 time-controlling + fork // <--- Bad IEEE 1800-2023 13.4 time-controlling join - fork // <--- Bad IEEE 1800-2023 13.4 time-controlling + fork // <--- Bad IEEE 1800-2023 13.4 time-controlling join_any - wait (s); // <--- Bad IEEE 1800-2023 13.4 time-controlling + wait (s); // <--- Bad IEEE 1800-2023 13.4 time-controlling // TODO wait_order (e); // TODO ## // TODO expect diff --git a/test_regress/t/t_lint_implicitstatic_bad.v b/test_regress/t/t_lint_implicitstatic_bad.v index 4fd096336..c766749f7 100644 --- a/test_regress/t/t_lint_implicitstatic_bad.v +++ b/test_regress/t/t_lint_implicitstatic_bad.v @@ -28,12 +28,12 @@ module t ( endtask function int f_no_implicit_static(); - localparam int ONE = 1; // No warning here + localparam int ONE = 1; // No warning here return ONE; endfunction task t_no_implicit_static(); - localparam TWO = 2; // No warning here + localparam TWO = 2; // No warning here endtask endmodule diff --git a/test_regress/t/t_lint_lint_bad.out b/test_regress/t/t_lint_lint_bad.out index fa391bb3f..de4d5c887 100644 --- a/test_regress/t/t_lint_lint_bad.out +++ b/test_regress/t/t_lint_lint_bad.out @@ -1,6 +1,6 @@ -%Warning-IMPLICIT: t/t_lint_lint_bad.v:9:7: Signal definition not found, creating implicitly: 'implicit_out' - 9 | not(implicit_out, i); - | ^~~~~~~~~~~~ +%Warning-IMPLICIT: t/t_lint_lint_bad.v:9:8: Signal definition not found, creating implicitly: 'implicit_out' + 9 | not (implicit_out, i); + | ^~~~~~~~~~~~ ... For warning description see https://verilator.org/warn/IMPLICIT?v=latest ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_lint_bad.v b/test_regress/t/t_lint_lint_bad.v index 88372ded3..4fdbcc574 100644 --- a/test_regress/t/t_lint_lint_bad.v +++ b/test_regress/t/t_lint_lint_bad.v @@ -6,5 +6,5 @@ module t; wire i = 0; - not(implicit_out, i); + not (implicit_out, i); endmodule diff --git a/test_regress/t/t_lint_modmissing.v b/test_regress/t/t_lint_modmissing.v index 6a6d7284e..9798cf4e6 100644 --- a/test_regress/t/t_lint_modmissing.v +++ b/test_regress/t/t_lint_modmissing.v @@ -4,7 +4,9 @@ // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module t(input i); - // verilator lint_off MODMISSING - foobar sub(i); +module t ( + input i +); + // verilator lint_off MODMISSING + foobar sub (i); endmodule diff --git a/test_regress/t/t_lint_range_negative_bad.v b/test_regress/t/t_lint_range_negative_bad.v index a9689b70e..f1a578184 100644 --- a/test_regress/t/t_lint_range_negative_bad.v +++ b/test_regress/t/t_lint_range_negative_bad.v @@ -9,9 +9,11 @@ module t; int array2_bad[-1]; // <--- Error: Must be positive size localparam X = 32'bz; logic [X:0] x; // <--- Error: X range - sub #(1) u_sub(); + sub #(1) u_sub (); endmodule -module sub #(parameter SIZE=0); +module sub #( + parameter SIZE = 0 +); int ignore[SIZE]; endmodule diff --git a/test_regress/t/t_lparam_assign_iface_array_typedef.v b/test_regress/t/t_lparam_assign_iface_array_typedef.v index fd6655de2..1a8722e92 100644 --- a/test_regress/t/t_lparam_assign_iface_array_typedef.v +++ b/test_regress/t/t_lparam_assign_iface_array_typedef.v @@ -3,33 +3,27 @@ // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -// -// +// verilog_format: off `define stop $stop -`define checkd(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0d exp=%0d\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on package a_pkg; - typedef struct packed { - int unsigned IdBits; - } cfg_t; + typedef struct packed {int unsigned IdBits;} cfg_t; endpackage interface bus_if #( - parameter a_pkg::cfg_t cfg = 0 -)(); + parameter a_pkg::cfg_t cfg = 0 +) (); typedef logic [cfg.IdBits-1:0] id_t; id_t id; endinterface -module a_mod #()( - bus_if bus_tgt_io - ,bus_if bus_mst_io +module a_mod #( +) ( + bus_if bus_tgt_io, + bus_if bus_mst_io ); localparam type tgt_id_t = bus_tgt_io.id_t; @@ -46,18 +40,18 @@ module a_mod #()( endmodule -module t( - input logic clk +module t ( + input logic clk ); localparam a_pkg::cfg_t cfg0 = '{IdBits: 5}; localparam a_pkg::cfg_t cfg1 = '{IdBits: 10}; - bus_if #(.cfg(cfg0)) bus_io0(); - bus_if #(.cfg(cfg1)) bus_io1(); + bus_if #(.cfg(cfg0)) bus_io0 (); + bus_if #(.cfg(cfg1)) bus_io1 (); - a_mod a_mod0( - .bus_tgt_io(bus_io0) - ,.bus_mst_io(bus_io1) + a_mod a_mod0 ( + .bus_tgt_io(bus_io0), + .bus_mst_io(bus_io1) ); initial begin diff --git a/test_regress/t/t_lparam_assign_iface_array_typedef2.v b/test_regress/t/t_lparam_assign_iface_array_typedef2.v index d077e3296..0eafeb872 100644 --- a/test_regress/t/t_lparam_assign_iface_array_typedef2.v +++ b/test_regress/t/t_lparam_assign_iface_array_typedef2.v @@ -3,16 +3,11 @@ // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -// -// +// verilog_format: off `define stop $stop -`define checkd(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0d exp=%0d\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on package a_pkg; typedef struct packed { @@ -56,8 +51,8 @@ module t( bus_if #(.cfg(cfg1)) bus_mst_io_a [2] (); a_mod a_mod0( - .bus_tgt_io_a(bus_tgt_io_a) - ,.bus_mst_io_a(bus_mst_io_a) + .bus_tgt_io_a(bus_tgt_io_a), + .bus_mst_io_a(bus_mst_io_a) ); initial begin diff --git a/test_regress/t/t_lparam_assign_iface_typedef.v b/test_regress/t/t_lparam_assign_iface_typedef.v index 71fdbdb08..169bdbaff 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef.v +++ b/test_regress/t/t_lparam_assign_iface_typedef.v @@ -5,19 +5,15 @@ // SPDX-License-Identifier: CC0-1.0 // // assign localparam from interface typedef, single level nesting -// +// verilog_format: off `define stop $stop -`define checkh(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0h exp=%0h\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0h exp=%0h\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on interface x_if #( - parameter int p_awidth = 4 - ,parameter int p_dwidth = 7 + parameter int p_awidth = 4, + parameter int p_dwidth = 7 )(); typedef struct packed { logic [p_awidth-1:0] addr; @@ -31,8 +27,8 @@ endinterface module top(); x_if #( - .p_awidth(16) - ,.p_dwidth(8) + .p_awidth(16), + .p_dwidth(8) ) if0(); localparam p0_rq_t = if0.rq_t; diff --git a/test_regress/t/t_lparam_assign_iface_typedef2.v b/test_regress/t/t_lparam_assign_iface_typedef2.v index 2bcf96896..7bebb16cc 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef2.v +++ b/test_regress/t/t_lparam_assign_iface_typedef2.v @@ -6,18 +6,14 @@ // interface x_if #( - parameter int a_width = 3 -)(); + parameter int a_width = 3 +) (); - typedef struct packed { - logic [a_width-1:0] addr; - } rq_t; + typedef struct packed {logic [a_width-1:0] addr;} rq_t; endinterface -module top(); - x_if #( - .a_width(8) - ) if0(); +module top (); + x_if #(.a_width(8)) if0 (); localparam type p0_t = if0.rq_t; diff --git a/test_regress/t/t_lparam_assign_iface_typedef3.v b/test_regress/t/t_lparam_assign_iface_typedef3.v index 972755ba7..4f95854b8 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef3.v +++ b/test_regress/t/t_lparam_assign_iface_typedef3.v @@ -5,27 +5,17 @@ // SPDX-License-Identifier: CC0-1.0 // // assign localparam from interface typedef, single level nesting -// +// verilog_format: off `define stop $stop -`define checkd(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0d exp=%0d\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); - -`define checkh(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0h exp=%0h\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0h exp=%0h\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on interface x_if #( - parameter int p_awidth = 4 - ,parameter int p_dwidth = 7 -)(); + parameter int p_awidth = 4, + parameter int p_dwidth = 7 +) (); localparam int Bits = p_awidth + p_dwidth; typedef struct packed { logic [p_awidth-1:0] addr; @@ -33,11 +23,11 @@ interface x_if #( } rq_t; endinterface -module top(); +module top (); x_if #( - .p_awidth(16) - ,.p_dwidth(8) - ) if0 [2](); + .p_awidth(16), + .p_dwidth(8) + ) if0[2] (); localparam type p0_rq_t = if0[0].rq_t; @@ -50,10 +40,10 @@ module top(); initial begin #1; - `checkd(if0[0].Bits,24); - `checkd($bits(rq),24); - `checkh(rq.addr,16'h1234); - `checkh(rq.data,8'h37); + `checkd(if0[0].Bits, 24); + `checkd($bits(rq), 24); + `checkh(rq.addr, 16'h1234); + `checkh(rq.data, 8'h37); $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested.v b/test_regress/t/t_lparam_assign_iface_typedef_nested.v index a3cfb9665..3fa06a292 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested.v @@ -16,8 +16,8 @@ interface y_if #( endinterface interface x_if #( - parameter int p_awidth = 4 - ,parameter int p_dwidth = 7 + parameter int p_awidth = 4, + parameter int p_dwidth = 7 )(); typedef struct packed { logic [p_awidth-1:0] addr; @@ -33,8 +33,8 @@ endinterface module top(); x_if #( - .p_awidth(16) - ,.p_dwidth(8) + .p_awidth(16), + .p_dwidth(8) ) if0(); localparam p0_rq2_t = if0.y_if0.rq2_t; diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested2.v b/test_regress/t/t_lparam_assign_iface_typedef_nested2.v index dccc8b428..3670a3e58 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested2.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested2.v @@ -8,43 +8,36 @@ // instance of type, assign to instance and check // +// verilog_format: off `define stop $stop -`define checkh(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0h exp=%0h\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0h exp=%0h\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on interface y_if #( - parameter int p_awidth = 3 -)(); - typedef struct packed { - logic [p_awidth-1:0] addr; - } rq2_t; + parameter int p_awidth = 3 +) (); + typedef struct packed {logic [p_awidth-1:0] addr;} rq2_t; endinterface interface x_if #( - parameter int p_awidth = 4 - ,parameter int p_dwidth = 7 -)(); + parameter int p_awidth = 4, + parameter int p_dwidth = 7 +) (); typedef struct packed { logic [p_awidth-1:0] addr; logic [p_dwidth-1:0] data; } rq_t; - typedef struct packed { - logic [p_dwidth-1:0] data; - } rs_t; + typedef struct packed {logic [p_dwidth-1:0] data;} rs_t; - y_if#(.p_awidth(p_awidth)) y_if0(); + y_if #(.p_awidth(p_awidth)) y_if0 (); endinterface -module top(); +module top (); x_if #( - .p_awidth(16) - ,.p_dwidth(8) - ) if0(); + .p_awidth(16), + .p_dwidth(8) + ) if0 (); localparam p0_rq2_t = if0.y_if0.rq2_t; diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested3.v b/test_regress/t/t_lparam_assign_iface_typedef_nested3.v index cb2ee3b6f..244901b6e 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested3.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested3.v @@ -8,44 +8,37 @@ // including nesting // +// verilog_format: off `define stop $stop -`define checkh(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0h exp=%0h\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0h exp=%0h\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on interface y_if #( - parameter int p_awidth = 3 -)(); - typedef struct packed { - logic [p_awidth-1:0] addr; - } rq2_t; + parameter int p_awidth = 3 +) (); + typedef struct packed {logic [p_awidth-1:0] addr;} rq2_t; endinterface interface x_if #( - parameter int p_awidth = 4 - ,parameter int p_dwidth = 7 -)(); + parameter int p_awidth = 4, + parameter int p_dwidth = 7 +) (); typedef struct packed { logic [p_awidth-1:0] addr; logic [p_dwidth-1:0] data; } rq_t; - typedef struct packed { - logic [p_dwidth-1:0] data; - } rs_t; + typedef struct packed {logic [p_dwidth-1:0] data;} rs_t; - y_if#(.p_awidth(p_awidth)) y_if0(); + y_if #(.p_awidth(p_awidth)) y_if0 (); endinterface -module top(); +module top (); x_if #( - .p_awidth(16) - ,.p_dwidth(8) - ) if0(); + .p_awidth(16), + .p_dwidth(8) + ) if0 (); localparam p0_rq2_t = if0.y_if0.rq2_t; localparam p0_rq_t = if0.rq_t; diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested4.v b/test_regress/t/t_lparam_assign_iface_typedef_nested4.v index 3dc4a1c77..a5fe6288c 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested4.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested4.v @@ -8,42 +8,33 @@ // including nesting // +// verilog_format: off `define stop $stop -`define checkh(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0h exp=%0h\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0h exp=%0h\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on interface y_if #( - parameter int p_awidth = 3 -)(); - typedef struct packed { - logic [p_awidth-1:0] addr; - } rq2_t; + parameter int p_awidth = 3 +) (); + typedef struct packed {logic [p_awidth-1:0] addr;} rq2_t; endinterface interface x_if #( - parameter int p_awidth = 4 - ,parameter int p_dwidth = 7 -)(); - typedef struct packed { - logic [p_awidth-1:0] addr; - } rq_t; + parameter int p_awidth = 4, + parameter int p_dwidth = 7 +) (); + typedef struct packed {logic [p_awidth-1:0] addr;} rq_t; - typedef struct packed { - logic [p_dwidth-1:0] data; - } rs_t; + typedef struct packed {logic [p_dwidth-1:0] data;} rs_t; - y_if#(.p_awidth(p_awidth)) y_if0(); + y_if #(.p_awidth(p_awidth)) y_if0 (); endinterface -module top(); +module top (); x_if #( - .p_awidth(16) - ,.p_dwidth(8) - ) if0(); + .p_awidth(16), + .p_dwidth(8) + ) if0 (); localparam type p0_rq2_t = if0.y_if0.rq2_t; localparam type p0_rq_t = if0.rq_t; diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested5.v b/test_regress/t/t_lparam_assign_iface_typedef_nested5.v index 5d80e4f43..cfb0cde7f 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested5.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested5.v @@ -8,54 +8,43 @@ // including nesting. param dependency. // +// verilog_format: off `define stop $stop -`define checkh(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0h exp=%0h\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0h exp=%0h\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on interface z_if #( - parameter int p_bwidth = 25 -)(); - typedef struct packed { - logic [p_bwidth-1:0] data; - } req_t; + parameter int p_bwidth = 25 +) (); + typedef struct packed {logic [p_bwidth-1:0] data;} req_t; logic sig_a; logic sig_b; endinterface interface y_if #( - parameter int p_awidth = 3 -)(); - typedef struct packed { - logic [p_awidth-1:0] addr; - } rq2_t; + parameter int p_awidth = 3 +) (); + typedef struct packed {logic [p_awidth-1:0] addr;} rq2_t; endinterface interface x_if #( - parameter int p_awidth = 4 - ,parameter int p_dwidth = 7 -)(); - typedef struct packed { - logic [p_awidth-1:0] addr; - } rq_t; + parameter int p_awidth = 4, + parameter int p_dwidth = 7 +) (); + typedef struct packed {logic [p_awidth-1:0] addr;} rq_t; - typedef struct packed { - logic [p_dwidth-1:0] data; - } rs_t; + typedef struct packed {logic [p_dwidth-1:0] data;} rs_t; - y_if#(.p_awidth(p_awidth)) y_if0(); - z_if#(.p_bwidth(p_awidth+p_dwidth)) z_if0(); + y_if #(.p_awidth(p_awidth)) y_if0 (); + z_if #(.p_bwidth(p_awidth + p_dwidth)) z_if0 (); endinterface -module top(); +module top (); x_if #( - .p_awidth(16) - ,.p_dwidth(8) - ) if0(); + .p_awidth(16), + .p_dwidth(8) + ) if0 (); localparam p0_rq2_t = if0.y_if0.rq2_t; localparam p0_rq_t = if0.rq_t; diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested6.v b/test_regress/t/t_lparam_assign_iface_typedef_nested6.v index 527fcee7c..c53c5a299 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested6.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested6.v @@ -24,8 +24,8 @@ interface y_if #( endinterface interface z_if #( - parameter int p_awidth = 3 - ,parameter int p_dwidth = 9 + parameter int p_awidth = 3, + parameter int p_dwidth = 9 ); x_if #(p_awidth) x_if0(); y_if #(p_dwidth) y_if0(); diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules.v b/test_regress/t/t_lparam_assign_iface_typedef_nested_modules.v index 680277722..fea53a1fc 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_modules.v @@ -9,8 +9,8 @@ // interface bus_if #( - parameter int p_awidth = 4 - ,parameter int p_dwidth = 7 + parameter int p_awidth = 4, + parameter int p_dwidth = 7 ); typedef struct packed { logic [p_awidth-1:0] addr; diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules2.v b/test_regress/t/t_lparam_assign_iface_typedef_nested_modules2.v index d32aedfe1..d6722ebce 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules2.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_modules2.v @@ -9,31 +9,24 @@ // parameter // +// verilog_format: off `define stop $stop -`define checkh(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0h exp=%0h\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0h exp=%0h\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on interface bus_if #( - parameter int p_awidth = 4 - ,parameter int p_dwidth = 7 + parameter int p_awidth = 4, + parameter int p_dwidth = 7 ); - typedef struct packed { - logic [p_awidth-1:0] addr; - } rq_t; - typedef struct packed { - logic [p_dwidth-1:0] data; - } rs_t; + typedef struct packed {logic [p_awidth-1:0] addr;} rq_t; + typedef struct packed {logic [p_dwidth-1:0] data;} rs_t; rq_t rq; rs_t rs; endinterface -module a_mod( - bus_if bus_io +module a_mod ( + bus_if bus_io ); localparam bus_rq_t = bus_io.rq_t; localparam bus_rs_t = bus_io.rs_t; @@ -47,12 +40,13 @@ module a_mod( assign bus_io.rs = rs; endmodule -module top(); - bus_if #(.p_awidth(16), .p_dwidth(8)) bus_io(); +module top (); + bus_if #( + .p_awidth(16), + .p_dwidth(8) + ) bus_io (); - a_mod a_mod_inst( - .bus_io(bus_io) - ); + a_mod a_mod_inst (.bus_io(bus_io)); initial begin #1; diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules3.v b/test_regress/t/t_lparam_assign_iface_typedef_nested_modules3.v index 0e02d9095..fe82ad430 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules3.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_modules3.v @@ -8,42 +8,33 @@ // including nesting // +// verilog_format: off `define stop $stop -`define checkh(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0h exp=%0h\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0h exp=%0h\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on interface y_if #( - parameter int p_awidth = 3 -)(); - typedef struct packed { - logic [p_awidth-1:0] addr; - } rq2_t; + parameter int p_awidth = 3 +) (); + typedef struct packed {logic [p_awidth-1:0] addr;} rq2_t; endinterface interface x_if #( - parameter int p_awidth = 4 - ,parameter int p_dwidth = 7 -)(); - typedef struct packed { - logic [p_awidth-1:0] addr; - } rq_t; + parameter int p_awidth = 4, + parameter int p_dwidth = 7 +) (); + typedef struct packed {logic [p_awidth-1:0] addr;} rq_t; - typedef struct packed { - logic [p_dwidth-1:0] data; - } rs_t; + typedef struct packed {logic [p_dwidth-1:0] data;} rs_t; - y_if#(.p_awidth(p_awidth)) y_if0(); + y_if #(.p_awidth(p_awidth)) y_if0 (); endinterface -module top(); +module top (); x_if #( - .p_awidth(16) - ,.p_dwidth(8) - ) if0(); + .p_awidth(16), + .p_dwidth(8) + ) if0 (); localparam p0_rq2_t = if0.y_if0.rq2_t; localparam p0_rq_t = if0.rq_t; diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg.v b/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg.v index 9f7524fb2..86fdaaf83 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg.v @@ -9,38 +9,33 @@ // ultimately interface // +// verilog_format: off `define stop $stop -`define checkh(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0h exp=%0h\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0h exp=%0h\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on package a_pkg; typedef struct packed { - int unsigned awidth; - int unsigned dwidth; + int unsigned awidth; + int unsigned dwidth; } cfg_t; endpackage interface bus_if #( - parameter int p_awidth = 4 - ,parameter int p_dwidth = 7 + parameter int p_awidth = 4, + parameter int p_dwidth = 7 ); - typedef struct packed { - logic [p_awidth-1:0] addr; - } rq_t; - typedef struct packed { - logic [p_dwidth-1:0] data; - } rs_t; + typedef struct packed {logic [p_awidth-1:0] addr;} rq_t; + typedef struct packed {logic [p_dwidth-1:0] data;} rs_t; rq_t rq; rs_t rs; endinterface -module a_mod #(parameter a_pkg::cfg_t cfg=0)( - bus_if bus_io +module a_mod #( + parameter a_pkg::cfg_t cfg = 0 +) ( + bus_if bus_io ); localparam bus_rq_t = bus_io.rq_t; localparam bus_rs_t = bus_io.rs_t; @@ -56,16 +51,14 @@ module a_mod #(parameter a_pkg::cfg_t cfg=0)( end endmodule -module top(); - localparam a_pkg::cfg_t cfg = '{ - awidth : 16 - ,dwidth : 8 - }; - bus_if #(.p_awidth(16), .p_dwidth(8)) bus_io(); +module top (); + localparam a_pkg::cfg_t cfg = '{awidth : 16, dwidth : 8}; + bus_if #( + .p_awidth(16), + .p_dwidth(8) + ) bus_io (); - a_mod #(cfg) a_mod_inst( - .bus_io(bus_io) - ); + a_mod #(cfg) a_mod_inst (.bus_io(bus_io)); initial begin #1; diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg4.v b/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg4.v index 5f3267ce7..3f03f7e9d 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg4.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg4.v @@ -28,9 +28,9 @@ interface tb_if #(parameter cca::cfg_t cfg=0)(); endinterface module modA#( - parameter aer::cfg_t cfg=0 + parameter aer::cfg_t cfg=0, // - ,localparam type rule_t = amb::rule_t + localparam type rule_t = amb::rule_t )(); localparam cca::cfg_t cca_cfg = '{ diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg.v b/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg.v index f337492dd..23b8c1422 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg.v @@ -9,69 +9,50 @@ // to pass params to module hierarchy and ultimately interface // +// verilog_format: off `define stop $stop -`define checkd(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0d exp=%0d\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); - -`define checkh(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0h exp=%0h\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0h exp=%0h\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on package a_pkg; typedef struct packed { - int unsigned a_cfg; - int unsigned b_cfg; - int unsigned d_cfg; + int unsigned a_cfg; + int unsigned b_cfg; + int unsigned d_cfg; } cfg_t; endpackage interface z_if #( - parameter a_pkg::cfg_t CFG = 0 -)(); - typedef struct packed { - logic [CFG.d_cfg + CFG.a_cfg - 1:0] data; - } req_t; + parameter a_pkg::cfg_t CFG = 0 +) (); + typedef struct packed {logic [CFG.d_cfg + CFG.a_cfg - 1:0] data;} req_t; logic sig_a; logic sig_b; endinterface interface y_if #( - parameter a_pkg::cfg_t CFG = 0 -)(); - typedef struct packed { - logic [CFG.a_cfg-1:0] addr; - } rq2_t; + parameter a_pkg::cfg_t CFG = 0 +) (); + typedef struct packed {logic [CFG.a_cfg-1:0] addr;} rq2_t; endinterface interface x_if #( - parameter a_pkg::cfg_t CFG = 0 -)(); - typedef struct packed { - logic [CFG.a_cfg-1:0] addr; - } rq_t; + parameter a_pkg::cfg_t CFG = 0 +) (); + typedef struct packed {logic [CFG.a_cfg-1:0] addr;} rq_t; - typedef struct packed { - logic [CFG.d_cfg-1:0] data; - } rs_t; + typedef struct packed {logic [CFG.d_cfg-1:0] data;} rs_t; - y_if#(.CFG(CFG)) y_if0(); - z_if#(.CFG(CFG)) z_if0(); + y_if #(.CFG(CFG)) y_if0 (); + z_if #(.CFG(CFG)) z_if0 (); endinterface -module top(); +module top (); localparam a_pkg::cfg_t CFG = '{a_cfg: 16, b_cfg: 8, d_cfg: 8}; - x_if #( - .CFG(CFG) - ) if0(); + x_if #(.CFG(CFG)) if0 (); localparam p0_rq2_t = if0.y_if0.rq2_t; localparam p0_rq_t = if0.rq_t; diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg2.v b/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg2.v index 95fbb5b4e..8bd1c7c49 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg2.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg2.v @@ -9,13 +9,10 @@ // to pass params to module hierarchy and ultimately interface // +// verilog_format: off `define stop $stop -`define checkh(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0h exp=%0h\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0h exp=%0h\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on package a_pkg; typedef struct packed { @@ -26,46 +23,36 @@ package a_pkg; endpackage interface z_if #( - parameter a_pkg::cfg_t CFG = 0 -)(); - typedef struct packed { - logic [CFG.d_cfg + CFG.a_cfg - 1:0] data; - } req_t; + parameter a_pkg::cfg_t CFG = 0 +) (); + typedef struct packed {logic [CFG.d_cfg + CFG.a_cfg - 1:0] data;} req_t; logic sig_a; logic sig_b; endinterface interface y_if #( - parameter a_pkg::cfg_t CFG = 0 -)(); - typedef struct packed { - logic [CFG.a_cfg-1:0] addr; - } rq2_t; + parameter a_pkg::cfg_t CFG = 0 +) (); + typedef struct packed {logic [CFG.a_cfg-1:0] addr;} rq2_t; endinterface interface x_if #( - parameter a_pkg::cfg_t CFG = 0 -)(); - typedef struct packed { - logic [CFG.a_cfg-1:0] addr; - } rq_t; + parameter a_pkg::cfg_t CFG = 0 +) (); + typedef struct packed {logic [CFG.a_cfg-1:0] addr;} rq_t; - typedef struct packed { - logic [CFG.d_cfg-1:0] data; - } rs_t; + typedef struct packed {logic [CFG.d_cfg-1:0] data;} rs_t; - y_if#(.CFG(CFG)) y_if0(); - z_if#(.CFG(CFG)) z_if0(); + y_if #(.CFG(CFG)) y_if0 (); + z_if #(.CFG(CFG)) z_if0 (); endinterface -module top(); +module top (); localparam a_pkg::cfg_t CFG = '{a_cfg: 16, b_cfg: 8, d_cfg: 8}; - x_if #( - .CFG(CFG) - ) if0(); + x_if #(.CFG(CFG)) if0 (); localparam type p0_rq2_t = if0.y_if0.rq2_t; localparam type p0_rq_t = if0.rq_t; diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg3.v b/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg3.v index 197b9b99c..f9536da4a 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg3.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg3.v @@ -5,31 +5,26 @@ // SPDX-License-Identifier: CC0-1.0 // // +// verilog_format: off `define stop $stop -`define checkd(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0d exp=%0d\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on package a_pkg; - typedef struct packed { - int unsigned IdBits; - } cfg_t; + typedef struct packed {int unsigned IdBits;} cfg_t; endpackage interface bus_if #( - parameter a_pkg::cfg_t cfg = 0 -)(); + parameter a_pkg::cfg_t cfg = 0 +) (); typedef logic [cfg.IdBits-1:0] id_t; endinterface module a_mod #( - parameter int p_expect = 0 -)( - bus_if bus_io + parameter int p_expect = 0 +) ( + bus_if bus_io ); localparam type cfg_id_t = bus_io.id_t; @@ -43,22 +38,18 @@ module a_mod #( endmodule -module t( - input logic clk +module t ( + input logic clk ); localparam a_pkg::cfg_t cfg0 = '{IdBits: 5}; localparam a_pkg::cfg_t cfg1 = '{IdBits: 10}; - bus_if #(.cfg(cfg0)) bus_if0(); - bus_if #(.cfg(cfg1)) bus_if1(); + bus_if #(.cfg(cfg0)) bus_if0 (); + bus_if #(.cfg(cfg1)) bus_if1 (); - a_mod #(5) a_mod0( - .bus_io(bus_if0) - ); + a_mod #(5) a_mod0 (.bus_io(bus_if0)); - a_mod #(10) a_mod1( - .bus_io(bus_if1) - ); + a_mod #(10) a_mod1 (.bus_io(bus_if1)); initial begin #10; diff --git a/test_regress/t/t_math_cv_bitop.v b/test_regress/t/t_math_cv_bitop.v index 9a4cbcf6a..e5ba80fd4 100644 --- a/test_regress/t/t_math_cv_bitop.v +++ b/test_regress/t/t_math_cv_bitop.v @@ -4,8 +4,10 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module sub ( input wire clock_4, diff --git a/test_regress/t/t_math_cv_concat.v b/test_regress/t/t_math_cv_concat.v index 5f4b9e37d..cbecf25f6 100644 --- a/test_regress/t/t_math_cv_concat.v +++ b/test_regress/t/t_math_cv_concat.v @@ -4,8 +4,10 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0h\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; // Issue #5972 diff --git a/test_regress/t/t_math_cv_format.v b/test_regress/t/t_math_cv_format.v index 1896c2bc3..ddb6661d6 100644 --- a/test_regress/t/t_math_cv_format.v +++ b/test_regress/t/t_math_cv_format.v @@ -4,8 +4,10 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; wire signed [21:10] out0; diff --git a/test_regress/t/t_math_pow.v b/test_regress/t/t_math_pow.v index 286fe0546..e1c4f73eb 100644 --- a/test_regress/t/t_math_pow.v +++ b/test_regress/t/t_math_pow.v @@ -6,19 +6,14 @@ `define STRINGIFY(x) `"x`" +// verilog_format: off `define stop $stop -`ifdef VERILATOR - `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) -`else - `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0) -`endif +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; +module t ( + input clk +); reg [66:0] a; reg [66:0] b; diff --git a/test_regress/t/t_math_pow7.v b/test_regress/t/t_math_pow7.v index 68a14e599..20c2070a2 100644 --- a/test_regress/t/t_math_pow7.v +++ b/test_regress/t/t_math_pow7.v @@ -6,12 +6,10 @@ `define STRINGIFY(x) `"x`" +// verilog_format: off `define stop $stop -`ifdef VERILATOR - `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) -`else - `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0) -`endif +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_math_repl3_bad.out b/test_regress/t/t_math_repl3_bad.out index 33fa422b5..c4e14547f 100644 --- a/test_regress/t/t_math_repl3_bad.out +++ b/test_regress/t/t_math_repl3_bad.out @@ -1,27 +1,27 @@ -%Error: t/t_math_repl3_bad.v:14:50: Replication value of < 0 or X/Z not legal (IEEE 1800-2023 11.4.12.1): '32'hfffffff8' +%Error: t/t_math_repl3_bad.v:15:50: Replication value of < 0 or X/Z not legal (IEEE 1800-2023 11.4.12.1): '32'hfffffff8' : ... note: In instance 't' - 14 | link_data_reg_in = {{((NUM_LANES - 2) * 8) {1'b0}}, link_data_reg[15:8]}; + 15 | link_data_reg_in = {{((NUM_LANES - 2) * 8) {1'b0}}, link_data_reg[15:8]}; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Warning-SELRANGE: t/t_math_repl3_bad.v:14:72: Selection index out of range: 15:8 outside 7:0 +%Warning-SELRANGE: t/t_math_repl3_bad.v:15:72: Selection index out of range: 15:8 outside 7:0 : ... note: In instance 't' - 14 | link_data_reg_in = {{((NUM_LANES - 2) * 8) {1'b0}}, link_data_reg[15:8]}; + 15 | link_data_reg_in = {{((NUM_LANES - 2) * 8) {1'b0}}, link_data_reg[15:8]}; | ^ ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. -%Warning-WIDTHTRUNC: t/t_math_repl3_bad.v:14:24: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's REPLICATE generates 9 bits. +%Warning-WIDTHTRUNC: t/t_math_repl3_bad.v:15:24: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's REPLICATE generates 9 bits. : ... note: In instance 't' - 14 | link_data_reg_in = {{((NUM_LANES - 2) * 8) {1'b0}}, link_data_reg[15:8]}; + 15 | link_data_reg_in = {{((NUM_LANES - 2) * 8) {1'b0}}, link_data_reg[15:8]}; | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. -%Error: t/t_math_repl3_bad.v:16:19: Replication value of < 0 or X/Z not legal (IEEE 1800-2023 11.4.12.1): '32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz' +%Error: t/t_math_repl3_bad.v:17:19: Replication value of < 0 or X/Z not legal (IEEE 1800-2023 11.4.12.1): '32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz' : ... note: In instance 't' - 16 | other = {32'bz{1'b1}}; + 17 | other = {32'bz{1'b1}}; | ^ -%Warning-WIDTHEXPAND: t/t_math_repl3_bad.v:16:11: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's REPLICATE generates 1 bits. +%Warning-WIDTHEXPAND: t/t_math_repl3_bad.v:17:11: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's REPLICATE generates 1 bits. : ... note: In instance 't' - 16 | other = {32'bz{1'b1}}; + 17 | other = {32'bz{1'b1}}; | ^ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. diff --git a/test_regress/t/t_math_repl3_bad.v b/test_regress/t/t_math_repl3_bad.v index b0e33eaca..66192c87e 100644 --- a/test_regress/t/t_math_repl3_bad.v +++ b/test_regress/t/t_math_repl3_bad.v @@ -5,7 +5,8 @@ // SPDX-License-Identifier: CC0-1.0 module t #( - parameter NUM_LANES = 1); + parameter NUM_LANES = 1 +); reg [(NUM_LANES*8)-1:0] link_data_reg, link_data_reg_in; reg [1:0] other; diff --git a/test_regress/t/t_math_shiftls.v b/test_regress/t/t_math_shiftls.v index 334f1a104..561a04f6e 100644 --- a/test_regress/t/t_math_shiftls.v +++ b/test_regress/t/t_math_shiftls.v @@ -4,8 +4,10 @@ // any use, without warranty, 2025 by Zhen Yan. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkd(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__, `__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module top (out33); diff --git a/test_regress/t/t_math_shiftrs2.v b/test_regress/t/t_math_shiftrs2.v index 541902b6b..821604679 100644 --- a/test_regress/t/t_math_shiftrs2.v +++ b/test_regress/t/t_math_shiftrs2.v @@ -4,8 +4,10 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkd(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__, `__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module top(out35); output wire [2:0] out35; diff --git a/test_regress/t/t_metacmt_fargs.v b/test_regress/t/t_metacmt_fargs.v index 2264fc67b..88fd04bb4 100644 --- a/test_regress/t/t_metacmt_fargs.v +++ b/test_regress/t/t_metacmt_fargs.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 // verilator fargs --binary -Wno-WIDTHEXPAND -/* verilator fargs -Wno-WIDTHTRUNC *//* verilator fargs --trace-vcd --stats */ +/* verilator fargs -Wno-WIDTHTRUNC */ /* verilator fargs --trace-vcd --stats */ module top; @@ -14,7 +14,7 @@ module top; reg [3:0] cyc = 0; always @(posedge clk) begin - cyc <= cyc + 10'd1; // Intentional width warning + cyc <= cyc + 10'd1; // Intentional width warning $display("%8t %1d", $time, cyc); if (cyc == 3'd7) begin // Intentional width warning $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_mod_interface_clocking.v b/test_regress/t/t_mod_interface_clocking.v index 22e6c7161..c59b05702 100644 --- a/test_regress/t/t_mod_interface_clocking.v +++ b/test_regress/t/t_mod_interface_clocking.v @@ -6,8 +6,8 @@ interface axi_if; logic clk; - wire rlast; - wire rvalid; + wire rlast; + wire rvalid; clocking cb @(posedge clk); inout rlast, rvalid; endclocking @@ -47,5 +47,8 @@ endmodule module t; axi_if axi_vi (); - sub i_sub (.axi1(axi_vi), .axi2(axi_vi)); + sub i_sub ( + .axi1(axi_vi), + .axi2(axi_vi) + ); endmodule diff --git a/test_regress/t/t_mod_param_class_typedef1.v b/test_regress/t/t_mod_param_class_typedef1.v index 4da5e7a31..74ff9c26a 100644 --- a/test_regress/t/t_mod_param_class_typedef1.v +++ b/test_regress/t/t_mod_param_class_typedef1.v @@ -10,16 +10,14 @@ // verilog_format: on class p_class #( - parameter TLEN = 2, - localparam type T = logic [TLEN-1:0] + parameter TLEN = 2, + localparam type T = logic [TLEN-1:0] ); - typedef struct packed { - T a; - } p_type; + typedef struct packed {T a;} p_type; endclass module p_mod #( - parameter type T = logic + parameter type T = logic ); initial begin #1; @@ -27,11 +25,11 @@ module p_mod #( end endmodule -module the_top #()(); +module the_top #() (); typedef p_class#(8)::p_type p_type_t; - p_mod #(p_type_t) p1(); + p_mod #(p_type_t) p1 (); - p_mod #( p_class#(8)::p_type ) p2(); + p_mod #(p_class#(8)::p_type) p2 (); initial begin #2; diff --git a/test_regress/t/t_mod_param_class_typedef2.v b/test_regress/t/t_mod_param_class_typedef2.v index a749557a3..2c8955cbf 100644 --- a/test_regress/t/t_mod_param_class_typedef2.v +++ b/test_regress/t/t_mod_param_class_typedef2.v @@ -10,16 +10,14 @@ // verilog_format: on class p_class #( - parameter TLEN = 2, - localparam type T = logic [TLEN-1:0] + parameter TLEN = 2, + localparam type T = logic [TLEN-1:0] ); - typedef struct packed { - T a, b; - } p_type; + typedef struct packed {T a, b;} p_type; endclass module p_mod #( - parameter type T = logic + parameter type T = logic ); initial begin #1; @@ -28,13 +26,13 @@ module p_mod #( endmodule module the_top #() (); - p_mod #(.T(p_class#(8)::p_type)) p1(); + p_mod #(.T(p_class#(8)::p_type)) p1 (); typedef p_class#(8) p_class_8; - p_mod #(.T(p_class_8::p_type)) p2(); + p_mod #(.T(p_class_8::p_type)) p2 (); typedef p_class#(8)::p_type p_class_type_8; - p_mod #(.T(p_class_type_8)) p4(); + p_mod #(.T(p_class_type_8)) p4 (); initial begin #2; diff --git a/test_regress/t/t_mod_param_class_typedef3.v b/test_regress/t/t_mod_param_class_typedef3.v index 08bcd004b..81e28b61f 100644 --- a/test_regress/t/t_mod_param_class_typedef3.v +++ b/test_regress/t/t_mod_param_class_typedef3.v @@ -10,16 +10,14 @@ // verilog_format: on class p_class #( - parameter TLEN = 2, - localparam type T = logic [TLEN-1:0] + parameter TLEN = 2, + localparam type T = logic [TLEN-1:0] ); - typedef struct packed { - T a, b; - } p_type; + typedef struct packed {T a, b;} p_type; endclass module p_mod #( - parameter type T = logic + parameter type T = logic ); initial begin #1; @@ -31,7 +29,7 @@ module the_top #() (); typedef p_class#(8) p_class_8; typedef p_class_8::p_type p_type_8; - p_mod #(.T(p_type_8)) p3(); + p_mod #(.T(p_type_8)) p3 (); initial begin #2; diff --git a/test_regress/t/t_mod_param_class_typedef4.v b/test_regress/t/t_mod_param_class_typedef4.v index 08142c739..555c9b46b 100644 --- a/test_regress/t/t_mod_param_class_typedef4.v +++ b/test_regress/t/t_mod_param_class_typedef4.v @@ -10,16 +10,14 @@ // verilog_format: on class p_class #( - parameter TLEN = 2, - localparam type T = logic [TLEN-1:0] + parameter TLEN = 2, + localparam type T = logic [TLEN-1:0] ); - typedef struct packed { - T a, b; - } p_type; + typedef struct packed {T a, b;} p_type; endclass module p_mod #( - parameter type T = logic + parameter type T = logic ); initial begin #1; @@ -28,16 +26,16 @@ module p_mod #( endmodule module the_top #() (); - p_mod #(.T(p_class#(8)::p_type)) p1(); + p_mod #(.T(p_class#(8)::p_type)) p1 (); typedef p_class#(8) p_class_8; - p_mod #(.T(p_class_8::p_type)) p2(); + p_mod #(.T(p_class_8::p_type)) p2 (); typedef p_class_8::p_type p_type_8; - p_mod #(.T(p_type_8)) p3(); + p_mod #(.T(p_type_8)) p3 (); typedef p_class#(8)::p_type p_class_type_8; - p_mod #(.T(p_class_type_8)) p4(); + p_mod #(.T(p_class_type_8)) p4 (); initial begin #2; diff --git a/test_regress/t/t_mod_param_class_typedef5.v b/test_regress/t/t_mod_param_class_typedef5.v index 63542975a..d496e5cfa 100644 --- a/test_regress/t/t_mod_param_class_typedef5.v +++ b/test_regress/t/t_mod_param_class_typedef5.v @@ -9,15 +9,21 @@ `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); // verilog_format: on -class xxx_class #(parameter int X = 1); - typedef logic [X-1:0] cmd_tag_t; +class xxx_class #( + parameter int X = 1 +); + typedef logic [X-1:0] cmd_tag_t; endclass -module mod_a #(parameter p_width=16) (); +module mod_a #( + parameter p_width = 16 +) (); endmodule -module mod_b #(parameter type io_type_t = logic) ( - io_type_t io +module mod_b #( + parameter type io_type_t = logic +) ( + io_type_t io ); initial begin @@ -26,13 +32,13 @@ module mod_b #(parameter type io_type_t = logic) ( end endmodule -module the_top(); +module the_top (); xxx_class#(16)::cmd_tag_t tag; - mod_a #($bits(tag)) t0(); + mod_a #($bits(tag)) t0 (); typedef xxx_class#(16)::cmd_tag_t tag_t; tag_t tag_io; - mod_b #(tag_t) t1(tag_io); + mod_b #(tag_t) t1 (tag_io); initial begin #2; diff --git a/test_regress/t/t_mod_param_class_typedef6.v b/test_regress/t/t_mod_param_class_typedef6.v index fc4d675e6..f8a9aa139 100644 --- a/test_regress/t/t_mod_param_class_typedef6.v +++ b/test_regress/t/t_mod_param_class_typedef6.v @@ -9,16 +9,20 @@ `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); // verilog_format: on -class xxx_class #(parameter int X = 1); - typedef logic [X-1:0] cmd_tag_t; +class xxx_class #( + parameter int X = 1 +); + typedef logic [X-1:0] cmd_tag_t; endclass -module mod_a #(parameter p_width=16) (); +module mod_a #( + parameter p_width = 16 +) (); endmodule -module the_top(); +module the_top (); xxx_class#(16)::cmd_tag_t tag; - mod_a #($bits(tag)) t0(); + mod_a #($bits(tag)) t0 (); initial begin #2; diff --git a/test_regress/t/t_mod_param_class_typedef7.v b/test_regress/t/t_mod_param_class_typedef7.v index b4859c879..756bc62b0 100644 --- a/test_regress/t/t_mod_param_class_typedef7.v +++ b/test_regress/t/t_mod_param_class_typedef7.v @@ -16,16 +16,20 @@ package pf; } cfg_t; endpackage -virtual class xxx_class #(parameter pf::cfg_t Cfg); +virtual class xxx_class #( + parameter pf::cfg_t Cfg +); typedef struct packed { logic [$clog2(Cfg.CcNumTl)-1:0] tl_index; logic [$clog2(Cfg.PqSize)-1:0] pq_index; } cmd_tag_t; endclass -module mod2 #(parameter p_width=16) ( - output logic [p_width-1:0] q, - input logic [p_width-1:0] d +module mod2 #( + parameter p_width = 16 +) ( + output logic [p_width-1:0] q, + input logic [p_width-1:0] d ); assign q = d; @@ -35,15 +39,15 @@ module mod2 #(parameter p_width=16) ( end endmodule -module top(); - localparam pf::cfg_t Cfg0 = '{ - CcNumTl:8 - ,PqSize:12 - }; +module top (); + localparam pf::cfg_t Cfg0 = '{CcNumTl: 8, PqSize: 12}; xxx_class#(Cfg0)::cmd_tag_t tag, tag_q; - mod2 #($bits(tag)) t0(tag_q, tag); + mod2 #($bits(tag)) t0 ( + tag_q, + tag + ); initial begin #1; diff --git a/test_regress/t/t_nba_hier.v b/test_regress/t/t_nba_hier.v index 40db25713..87967b19c 100644 --- a/test_regress/t/t_nba_hier.v +++ b/test_regress/t/t_nba_hier.v @@ -4,8 +4,10 @@ // any use, without warranty, 2020 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on module t; @@ -14,15 +16,15 @@ module t; logic [7:0] x; - sub a_0(); - sub a_1(); + sub a_0 (); + sub a_1 (); always @(posedge clk) begin a_0.x[3:0] <= ~x[3:0]; a_1.x[7:0] <= ~x; end - sub b_0(); - sub b_1(); + sub b_0 (); + sub b_1 (); always begin // Having this @posedge here makes this a 'suspendable' process, causing // the use of the FlagUnique scheme @@ -31,8 +33,8 @@ module t; b_1.x[7:0] <= ~x; end - sub c_0(); - sub c_1(); + sub c_0 (); + sub c_1 (); always @(posedge clk) begin c_0.x[3:0] <= ~x[3:0]; c_1.x[7:0] <= ~x; @@ -40,15 +42,15 @@ module t; assign c_0.x[9:8] = 2'd1; assign c_1.x[9:8] = 2'd2; - sub d_0(); - sub d_1(); + sub d_0 (); + sub d_1 (); always @(posedge clk) begin d_0.y[0][3:0] <= ~x[3:0]; d_1.y[0][7:0] <= ~x; end - sub e_0(); - sub e_1(); + sub e_0 (); + sub e_1 (); always @(posedge clk) begin for (int i = 0; i < 2; ++i) begin e_0.y[i][3:0] <= ~x[3:0]; @@ -71,10 +73,10 @@ module t; `checkh(c_1.x[9:8], 2'h2); `checkh(d_0.y[0][3:0], 4'h3); `checkh(d_1.y[0][7:0], 8'h33); - for (int i = 0; i < 2; ++i) begin + for (int i = 0; i < 2; ++i) begin `checkh(e_0.y[i][3:0], 4'h3); `checkh(e_1.y[i][7:0], 8'h33); - end + end #1; x = 8'h55; @@ -90,10 +92,10 @@ module t; `checkh(c_1.x[9:8], 2'h2); `checkh(d_0.y[0][3:0], 4'ha); `checkh(d_1.y[0][7:0], 8'haa); - for (int i = 0; i < 2; ++i) begin + for (int i = 0; i < 2; ++i) begin `checkh(e_0.y[i][3:0], 4'ha); `checkh(e_1.y[i][7:0], 8'haa); - end + end #1; $finish; @@ -103,5 +105,5 @@ endmodule module sub; logic [9:0] x; - logic [9:0] y [99]; + logic [9:0] y[99]; endmodule diff --git a/test_regress/t/t_nba_mixed_update_clocked.v b/test_regress/t/t_nba_mixed_update_clocked.v index 86f274928..20c4e9063 100644 --- a/test_regress/t/t_nba_mixed_update_clocked.v +++ b/test_regress/t/t_nba_mixed_update_clocked.v @@ -4,14 +4,14 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop -`define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: cyc=%0d got='h%x exp='h%x\n", `__FILE__,`__LINE__, cyc, (got), (exp)); `stop; end while(0) +`define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: cyc=%0d got='h%x exp='h%x\n", `__FILE__,`__LINE__, cyc, (gotv), (expv)); `stop; end while(0) +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); reg [31:0] cyc = 0; diff --git a/test_regress/t/t_nba_mixed_update_comb.v b/test_regress/t/t_nba_mixed_update_comb.v index e9ff73c76..c8c002d87 100644 --- a/test_regress/t/t_nba_mixed_update_comb.v +++ b/test_regress/t/t_nba_mixed_update_comb.v @@ -4,15 +4,14 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop -`define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: cyc=%0d got='h%x exp='h%x\n", `__FILE__,`__LINE__, cyc, (got), (exp)); `stop; end while(0) - -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +`define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: cyc=%0d got='h%x exp='h%x\n", `__FILE__,`__LINE__, cyc, (gotv), (expv)); `stop; end while(0) +// verilog_format: on +module t ( + input clk +); reg [31:0] cyc = 0; reg [31:0] sameAsCycButCantBeOptimized_0 = '0; diff --git a/test_regress/t/t_nba_shared_flag_reuse.v b/test_regress/t/t_nba_shared_flag_reuse.v index 0b3ae9555..2116c45ba 100644 --- a/test_regress/t/t_nba_shared_flag_reuse.v +++ b/test_regress/t/t_nba_shared_flag_reuse.v @@ -4,8 +4,10 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on module t; @@ -17,13 +19,13 @@ module t; reg r_valid; - reg [31:0] addr [1:0]; - reg [7:0] len [1:0]; + reg [31:0] addr[1:0]; + reg [7:0] len[1:0]; always #5 clk = ~clk; initial begin - #5; // Align with negedge clk + #5; // Align with negedge clk #20; `checkh(addr[0], 32'h0000_0000); @@ -65,8 +67,7 @@ module t; if (aw_valid) begin addr[0] <= 32'h33333333; len[0] <= 8'hff; - if (w_valid) - addr[0] <= 32'h44444444; + if (w_valid) addr[0] <= 32'h44444444; end end end diff --git a/test_regress/t/t_opt_0.v b/test_regress/t/t_opt_0.v index 225e16609..55b645c5f 100644 --- a/test_regress/t/t_opt_0.v +++ b/test_regress/t/t_opt_0.v @@ -8,7 +8,8 @@ module t; for (genvar k = 0; k < 1; k++) begin : gen_empty // empty end - initial for (int i = 0; i < 1; i++) begin : gen_i - // empty - end + initial + for (int i = 0; i < 1; i++) begin : gen_i + // empty + end endmodule diff --git a/test_regress/t/t_opt_const_big_or_tree.v b/test_regress/t/t_opt_const_big_or_tree.v index 7a7902187..f24ecb010 100644 --- a/test_regress/t/t_opt_const_big_or_tree.v +++ b/test_regress/t/t_opt_const_big_or_tree.v @@ -4,6 +4,7 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off module t (input x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31, x32, x33, x34, x35, x36, x37, x38, x39, x40, x41, x42, x43, @@ -82,8 +83,7 @@ module t (input x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x987, x988, x989, x990, x991, x992, x993, x994, x995, x996, x997, x998, x999, output [1:0] out - ); - +); assign out = {(x0 | x1 | x2 | x3 | x4 | x5 | x6 | x7 | x8 | x9 | x10 | x11 | x12 | x13 | x14 | x15 | x16 | x17 | x18 | x19 | x20 | x21 | x22 | x23 @@ -176,5 +176,6 @@ module t (input x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, | x976 | x977 | x978 | x979 | x980 | x981 | x982 | x983 | x984 | x985 | x986 | x987 | x988 | x989 | x990 | x991 | x992 | x993 | x994 | x995 | x996 | x997 | x998 | x999), 1'b0}; +// verilog_format: on endmodule diff --git a/test_regress/t/t_opt_const_cond_redundant.v b/test_regress/t/t_opt_const_cond_redundant.v index cf1c89ba2..8dcb36a90 100644 --- a/test_regress/t/t_opt_const_cond_redundant.v +++ b/test_regress/t/t_opt_const_cond_redundant.v @@ -36,8 +36,8 @@ module t ( $finish; end - if (direction == UP) ++ups; - else if (direction == UP) ++ups; + if (direction == UP)++ups; + else if (direction == UP)++ups; else ups += 1000; case (direction) diff --git a/test_regress/t/t_opt_inline_cfuncs.py b/test_regress/t/t_opt_inline_cfuncs.py new file mode 100755 index 000000000..5e2ad15b3 --- /dev/null +++ b/test_regress/t/t_opt_inline_cfuncs.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +# Use --output-split-cfuncs to create small functions that can be inlined +# Also test --inline-cfuncs-product option +test.compile(verilator_flags2=[ + "--stats", "--binary", "--output-split-cfuncs", "1", "--inline-cfuncs-product", "200" +]) + +# Verify inlining happened with exact count +test.file_grep(test.stats, r'Optimizations, Inlined CFuncs\s+(\d+)', 39) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_opt_inline_cfuncs.v b/test_regress/t/t_opt_inline_cfuncs.v new file mode 100644 index 000000000..6f95df5e6 --- /dev/null +++ b/test_regress/t/t_opt_inline_cfuncs.v @@ -0,0 +1,58 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// Test module designed to generate multiple small CFuncs that can be inlined +// Uses generate to create multiple sub-module instances +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc = 0; + + parameter CNT = 8; + + wire [31:0] w [CNT:0]; + reg [31:0] w0; + assign w[0] = w0; + + // Generate multiple sub-modules - each creates CFuncs that can be inlined + generate + for (genvar g=0; g 0 always) +test.compile(verilator_flags2=[ + "--stats", "--binary", "--inline-cfuncs", "1", "--inline-cfuncs-product", "0" +]) + +test.file_grep(test.stats, r'Optimizations, Inlined CFuncs\s+(\d+)', 0) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_opt_inline_cfuncs_threshold.v b/test_regress/t/t_opt_inline_cfuncs_threshold.v new file mode 100644 index 000000000..1970ece2e --- /dev/null +++ b/test_regress/t/t_opt_inline_cfuncs_threshold.v @@ -0,0 +1,27 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// Test module to exercise threshold checking in CFunc inlining +// With low thresholds, these functions should NOT be inlined +module t; + reg [31:0] a, b, c, d, e, f, g, h; + + initial begin + // Multiple operations to create larger CFuncs + a = 32'd1; + b = 32'd2; + c = a + b; + d = c * 2; + e = d - 1; + f = e + a; + g = f * b; + h = g + c + d + e + f; + + if (h != 32'd32) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_package_dup_bad2.v b/test_regress/t/t_package_dup_bad2.v index 122723714..8e265c9e7 100644 --- a/test_regress/t/t_package_dup_bad2.v +++ b/test_regress/t/t_package_dup_bad2.v @@ -9,10 +9,10 @@ endpackage module t; IOBUF iocell ( - .O (in), + .O(in), .IO(pad), - .I ('0), - .T (~oe) + .I('0), + .T(~oe) ); endmodule diff --git a/test_regress/t/t_param_array9.v b/test_regress/t/t_param_array9.v index 96e7eb374..81f7a5ce0 100644 --- a/test_regress/t/t_param_array9.v +++ b/test_regress/t/t_param_array9.v @@ -35,13 +35,11 @@ module ring #( .S_IS_T(s_is_t), .S_IS(S_IS) ) p ( - .*); + .* + ); endmodule module t; typedef logic [4:0] i_t; - ring #( - .I_T(i_t) - ) dut ( - .*); + ring #(.I_T(i_t)) dut (.*); endmodule diff --git a/test_regress/t/t_param_pattern3.v b/test_regress/t/t_param_pattern3.v index 9a846b82f..4ea714c5e 100644 --- a/test_regress/t/t_param_pattern3.v +++ b/test_regress/t/t_param_pattern3.v @@ -4,24 +4,23 @@ // without warranty. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop -`define checkd(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0d exp=%0d\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on -class Class_A #(parameter int myparam = 32); +class Class_A #( + parameter int myparam = 32 +); endclass module tb_top; - localparam int WIDTH_A=32; - localparam int WIDTH_B=2*16; + localparam int WIDTH_A = 32; + localparam int WIDTH_B = 2 * 16; - Class_A#(32) a; - Class_A#(WIDTH_A) b; - Class_A#(WIDTH_B) c; + Class_A #(32) a; + Class_A #(WIDTH_A) b; + Class_A #(WIDTH_B) c; initial begin #1; diff --git a/test_regress/t/t_param_resolve_args.v b/test_regress/t/t_param_resolve_args.v index d7d0294f0..2cd61b175 100644 --- a/test_regress/t/t_param_resolve_args.v +++ b/test_regress/t/t_param_resolve_args.v @@ -16,7 +16,10 @@ class Bar; endfunction endclass -class Qux #(type Tfoo, type Tbar); +class Qux #( + type Tfoo, + type Tbar +); static function int get(); return Tfoo::get(Tbar::get()); endfunction diff --git a/test_regress/t/t_property_pexpr.v b/test_regress/t/t_property_pexpr.v index aff72bfc9..82bd119bc 100644 --- a/test_regress/t/t_property_pexpr.v +++ b/test_regress/t/t_property_pexpr.v @@ -4,15 +4,15 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); int cyc; reg [63:0] crc; diff --git a/test_regress/t/t_property_sexpr2_bad.out b/test_regress/t/t_property_sexpr2_bad.out index c19645e7d..74372a23e 100644 --- a/test_regress/t/t_property_sexpr2_bad.out +++ b/test_regress/t/t_property_sexpr2_bad.out @@ -5,6 +5,6 @@ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_property_sexpr2_bad.v:21:35: Delay value is not an elaboration-time constant (IEEE 1800-2023 16.7) : ... note: In instance 't' - 21 | assert property (@(posedge clk) ##(1 + clk) val); + 21 | assert property (@(posedge clk) ##(1+clk) val); | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_property_sexpr2_bad.v b/test_regress/t/t_property_sexpr2_bad.v index 96e6bd67c..c64745024 100644 --- a/test_regress/t/t_property_sexpr2_bad.v +++ b/test_regress/t/t_property_sexpr2_bad.v @@ -18,5 +18,5 @@ module t ( /*AUTOARG*/ end assert property (@(posedge clk) ##clk val); - assert property (@(posedge clk) ##(1 + clk) val); + assert property (@(posedge clk) ##(1+clk) val); endmodule diff --git a/test_regress/t/t_property_sexpr_multi.v b/test_regress/t/t_property_sexpr_multi.v index 283ccb42e..1ee6e9dce 100644 --- a/test_regress/t/t_property_sexpr_multi.v +++ b/test_regress/t/t_property_sexpr_multi.v @@ -7,17 +7,16 @@ `define STRINGIFY(x) `"x`" `define TRIGGER(e) ->e; $display("[cyc=%0d, val=%0d] triggered %s", cyc, val, `STRINGIFY(e)) +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%p exp='h%p\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on -module t ( /*AUTOARG*/ - // Inputs - clk +module t ( + input clk ); - input clk; - bit [1:0] val = 0; event e1; event e2; diff --git a/test_regress/t/t_queue_arg.v b/test_regress/t/t_queue_arg.v index 03e0be8e5..e6e3a9be2 100644 --- a/test_regress/t/t_queue_arg.v +++ b/test_regress/t/t_queue_arg.v @@ -4,8 +4,10 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on typedef struct { string name1; diff --git a/test_regress/t/t_rand_stability_class.py b/test_regress/t/t_rand_stability_class.py new file mode 100755 index 000000000..f989a35fb --- /dev/null +++ b/test_regress/t/t_rand_stability_class.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_rand_stability_class.v b/test_regress/t/t_rand_stability_class.v new file mode 100644 index 000000000..f139994ae --- /dev/null +++ b/test_regress/t/t_rand_stability_class.v @@ -0,0 +1,33 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2025 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + class Cls; + task test_srandom; + int i, j, k; + // $urandom is per-process thread, not affected by object stability/this.srandom(seed) + // "Each object maintains its own internal RNG, which is used exclusively by its randomize() method." + // THis was moved to t_rand_stability_class.v + this.srandom(1234); + i = $urandom; + this.srandom(1234); + j = $urandom; + this.srandom(1234); + k = $urandom; + if (i == j && i == k) $stop; // Small chance randomly i == j, or j == k + endtask + endclass + + Cls c1; + + initial begin + c1 = new; + c1.test_srandom; + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_randcase_fork.py b/test_regress/t/t_randcase_fork.py new file mode 100755 index 000000000..ac142fe63 --- /dev/null +++ b/test_regress/t/t_randcase_fork.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randcase_fork.v b/test_regress/t/t_randcase_fork.v new file mode 100644 index 000000000..499a56273 --- /dev/null +++ b/test_regress/t/t_randcase_fork.v @@ -0,0 +1,24 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2025 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module randcase_tb; + int count; + initial begin + for (int i = 0; i < 100; i++) begin + fork + randcase + 1: count++; + 5: count--; + 3: ; + endcase + join_none + end + #1; + if (count > 30) $stop; // Realistically won't happen (10^25) though not impossible + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_randomize_complex.v b/test_regress/t/t_randomize_complex.v index 37c04e5b7..f6c5afa3e 100644 --- a/test_regress/t/t_randomize_complex.v +++ b/test_regress/t/t_randomize_complex.v @@ -6,34 +6,37 @@ class SubClass; rand bit [2:0] field; - function new (); + function new(); field = 0; endfunction endclass class MyClass; SubClass sc_inst2; - function new (); + function new(); sc_inst2 = new; endfunction -endclass; +endclass +; class Deep; MyClass sc_inst1; - function new (); + function new(); sc_inst1 = new; endfunction -endclass; +endclass +; class WeNeedToGoDeeper; Deep sc_inst; - function new (); + function new(); sc_inst = new; endfunction -endclass; +endclass +; module t; initial begin WeNeedToGoDeeper cl_inst = new; MyClass cl_inst2 = new; - repeat(10) begin + repeat (10) begin if (cl_inst.sc_inst.sc_inst1.sc_inst2.randomize() with {field inside {1, 2, 3};} == 0) begin $stop; end diff --git a/test_regress/t/t_randomize_complex_associative_arrays.v b/test_regress/t/t_randomize_complex_associative_arrays.v index 69d74ce80..fc139db88 100644 --- a/test_regress/t/t_randomize_complex_associative_arrays.v +++ b/test_regress/t/t_randomize_complex_associative_arrays.v @@ -6,28 +6,31 @@ class SubClass; rand bit [2:0] field; - function new (); + function new(); field = 0; endfunction endclass class MyClass; SubClass sc_inst2[int]; - function new (); + function new(); sc_inst2[1] = new; endfunction -endclass; +endclass +; class Deep; MyClass sc_inst1; - function new (); + function new(); sc_inst1 = new; endfunction -endclass; +endclass +; class WeNeedToGoDeeper; Deep sc_inst; - function new (); + function new(); sc_inst = new; endfunction -endclass; +endclass +; module t; initial begin @@ -35,8 +38,10 @@ module t; MyClass cl_inst2[int]; cl_inst["val1"] = new; cl_inst2[0] = new; - repeat(10) begin - if (cl_inst["val1"].sc_inst.sc_inst1.sc_inst2[1].randomize() with {field inside {1, 2, 3};} == 0) begin + repeat (10) begin + if (cl_inst["val1"].sc_inst.sc_inst1.sc_inst2[1].randomize() with { + field inside {1, 2, 3}; + } == 0) begin $stop; end if (cl_inst["val1"].sc_inst.sc_inst1.sc_inst2[1].field < 1 || cl_inst["val1"].sc_inst.sc_inst1.sc_inst2[1].field > 3) begin @@ -49,7 +54,7 @@ module t; $stop; end end - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end endmodule diff --git a/test_regress/t/t_randomize_complex_dynamic_arrays.v b/test_regress/t/t_randomize_complex_dynamic_arrays.v index 0b2ee25a3..308adf6c1 100644 --- a/test_regress/t/t_randomize_complex_dynamic_arrays.v +++ b/test_regress/t/t_randomize_complex_dynamic_arrays.v @@ -6,39 +6,44 @@ class SubClass; rand bit [2:0] field; - function new (); + function new(); field = 0; endfunction endclass class MyClass; SubClass sc_inst2[]; - function new (); - sc_inst2 = new [7]; + function new(); + sc_inst2 = new[7]; sc_inst2[1] = new; endfunction -endclass; +endclass +; class Deep; MyClass sc_inst1; - function new (); + function new(); sc_inst1 = new; endfunction -endclass; +endclass +; class WeNeedToGoDeeper; Deep sc_inst; - function new (); + function new(); sc_inst = new; endfunction -endclass; +endclass +; module t; initial begin WeNeedToGoDeeper cl_inst[]; MyClass cl_inst2[]; - cl_inst = new [3]; - cl_inst2 = new [5]; + cl_inst = new[3]; + cl_inst2 = new[5]; cl_inst[1] = new; cl_inst2[0] = new; - if (cl_inst[1].sc_inst.sc_inst1.sc_inst2[1].randomize() with {field inside {1, 2, 3};} == 0) begin + if (cl_inst[1].sc_inst.sc_inst1.sc_inst2[1].randomize() with { + field inside {1, 2, 3}; + } == 0) begin $stop; end if (cl_inst[1].sc_inst.sc_inst1.sc_inst2[1].field < 1 || cl_inst[1].sc_inst.sc_inst1.sc_inst2[1].field > 3) begin @@ -50,7 +55,7 @@ module t; if (cl_inst2[0].sc_inst2[1].field < 1 || cl_inst2[0].sc_inst2[1].field > 3) begin $stop; end - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end endmodule diff --git a/test_regress/t/t_randomize_complex_member_bad.out b/test_regress/t/t_randomize_complex_member_bad.out index 15f2d826f..845d518c3 100644 --- a/test_regress/t/t_randomize_complex_member_bad.out +++ b/test_regress/t/t_randomize_complex_member_bad.out @@ -1,12 +1,12 @@ -%Error: t/t_randomize_complex_member_bad.v:36:28: Class 'Deep' does not contain field 'sc_inst2' - 36 | if (cl_inst[1].sc_inst.sc_inst2.sc_inst2[1].randomize() with {field inside {1, 2, 3};} == 0) begin +%Error: t/t_randomize_complex_member_bad.v:39:28: Class 'Deep' does not contain field 'sc_inst2' + 39 | if (cl_inst[1].sc_inst.sc_inst2.sc_inst2[1].randomize() with { | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error-UNSUPPORTED: t/t_randomize_complex_member_bad.v:36:49: Unsupported: 'randomize() with' on complex expressions - 36 | if (cl_inst[1].sc_inst.sc_inst2.sc_inst2[1].randomize() with {field inside {1, 2, 3};} == 0) begin +%Error-UNSUPPORTED: t/t_randomize_complex_member_bad.v:39:49: Unsupported: 'randomize() with' on complex expressions + 39 | if (cl_inst[1].sc_inst.sc_inst2.sc_inst2[1].randomize() with { | ^~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error: t/t_randomize_complex_member_bad.v:36:67: Can't find definition of variable: 'field' - 36 | if (cl_inst[1].sc_inst.sc_inst2.sc_inst2[1].randomize() with {field inside {1, 2, 3};} == 0) begin - | ^~~~~ +%Error: t/t_randomize_complex_member_bad.v:40:11: Can't find definition of variable: 'field' + 40 | field inside {1, 2, 3}; + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_randomize_complex_member_bad.v b/test_regress/t/t_randomize_complex_member_bad.v index c521a3638..3673770c0 100644 --- a/test_regress/t/t_randomize_complex_member_bad.v +++ b/test_regress/t/t_randomize_complex_member_bad.v @@ -6,34 +6,39 @@ class SubClass; rand bit [2:0] field; - function new (); + function new(); field = 0; endfunction endclass class MyClass; SubClass sc_inst2[2]; - function new (); + function new(); sc_inst2[1] = new; endfunction -endclass; +endclass +; class Deep; MyClass sc_inst1; - function new (); + function new(); sc_inst1 = new; endfunction -endclass; +endclass +; class WeNeedToGoDeeper; Deep sc_inst; - function new (); + function new(); sc_inst = new; endfunction -endclass; +endclass +; module t; initial begin WeNeedToGoDeeper cl_inst[100]; cl_inst[1] = new; - if (cl_inst[1].sc_inst.sc_inst2.sc_inst2[1].randomize() with {field inside {1, 2, 3};} == 0) begin + if (cl_inst[1].sc_inst.sc_inst2.sc_inst2[1].randomize() with { + field inside {1, 2, 3}; + } == 0) begin $stop; end end diff --git a/test_regress/t/t_randomize_complex_queue.v b/test_regress/t/t_randomize_complex_queue.v index 1d9e3eef6..e1d37155d 100644 --- a/test_regress/t/t_randomize_complex_queue.v +++ b/test_regress/t/t_randomize_complex_queue.v @@ -6,38 +6,43 @@ class SubClass; rand bit [2:0] field; - function new (); + function new(); field = 0; endfunction endclass class MyClass; SubClass sc_inst2[$]; - function new (); + function new(); SubClass inst = new; - sc_inst2 = { inst }; + sc_inst2 = {inst}; endfunction -endclass; +endclass +; class Deep; MyClass sc_inst1; - function new (); + function new(); sc_inst1 = new; endfunction -endclass; +endclass +; class WeNeedToGoDeeper; Deep sc_inst; - function new (); + function new(); sc_inst = new; endfunction -endclass; +endclass +; module t; initial begin WeNeedToGoDeeper inst = new; MyClass inst2 = new; - WeNeedToGoDeeper cl_inst[$] = { inst }; - MyClass cl_inst2[$] = { inst2 }; - repeat(10) begin - if (cl_inst[0].sc_inst.sc_inst1.sc_inst2[0].randomize() with {field inside {1, 2, 3};} == 0) begin + WeNeedToGoDeeper cl_inst[$] = {inst}; + MyClass cl_inst2[$] = {inst2}; + repeat (10) begin + if (cl_inst[0].sc_inst.sc_inst1.sc_inst2[0].randomize() with { + field inside {1, 2, 3}; + } == 0) begin $stop; end if (cl_inst[0].sc_inst.sc_inst1.sc_inst2[0].field < 1 || cl_inst[0].sc_inst.sc_inst1.sc_inst2[0].field > 3) begin diff --git a/test_regress/t/t_randomize_complex_typedef.v b/test_regress/t/t_randomize_complex_typedef.v index 4d8e94589..e9baa725c 100644 --- a/test_regress/t/t_randomize_complex_typedef.v +++ b/test_regress/t/t_randomize_complex_typedef.v @@ -6,31 +6,34 @@ class SubClass; rand bit [2:0] field; - function new (); + function new(); field = 0; endfunction endclass typedef SubClass Sc_t; class MyClass; Sc_t sc_inst2[2]; - function new (); + function new(); sc_inst2[1] = new; endfunction -endclass; +endclass +; typedef MyClass Mc_t; class Deep; Mc_t sc_inst1; - function new (); + function new(); sc_inst1 = new; endfunction -endclass; +endclass +; typedef Deep D_t; class WeNeedToGoDeeper; D_t sc_inst; - function new (); + function new(); sc_inst = new; endfunction -endclass; +endclass +; typedef WeNeedToGoDeeper WNTGDA_t[100]; typedef MyClass MCA_t[2]; @@ -41,8 +44,10 @@ module t; MCA_t cl_inst2; cl_inst[1] = new; cl_inst2[0] = new; - repeat(10) begin - if (cl_inst[1].sc_inst.sc_inst1.sc_inst2[1].randomize() with {field inside {1, 2, 3};} == 0) begin + repeat (10) begin + if (cl_inst[1].sc_inst.sc_inst1.sc_inst2[1].randomize() with { + field inside {1, 2, 3}; + } == 0) begin $stop; end if (cl_inst[1].sc_inst.sc_inst1.sc_inst2[1].field < 1 || cl_inst[1].sc_inst.sc_inst1.sc_inst2[1].field > 3) begin @@ -55,7 +60,7 @@ module t; $stop; end end - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end endmodule diff --git a/test_regress/t/t_randomize_from_randomized_class.v b/test_regress/t/t_randomize_from_randomized_class.v index 6ac6539f9..2080bf13f 100644 --- a/test_regress/t/t_randomize_from_randomized_class.v +++ b/test_regress/t/t_randomize_from_randomized_class.v @@ -16,7 +16,7 @@ class B; i = 7; endfunction task r(); - if (a.randomize() with { j == i; } == 0) $stop; + if (a.randomize() with {j == i;} == 0) $stop; endtask endclass diff --git a/test_regress/t/t_randomize_local_param.v b/test_regress/t/t_randomize_local_param.v index 15c0a8b28..6735d2cae 100644 --- a/test_regress/t/t_randomize_local_param.v +++ b/test_regress/t/t_randomize_local_param.v @@ -20,7 +20,7 @@ package SubPkg; class p_mem_seq extends uvm_sequence #(s_trgt_txn); rand bit m_wr_flag; virtual task body(); - if (0 !== (m_req.randomize() with {local::m_wr_flag;})) begin + if (0 !== (m_req.randomize() with {local:: m_wr_flag;})) begin end endtask endclass diff --git a/test_regress/t/t_randomize_nested_unsup.v b/test_regress/t/t_randomize_nested_unsup.v index 8a47d9167..aa4977f57 100644 --- a/test_regress/t/t_randomize_nested_unsup.v +++ b/test_regress/t/t_randomize_nested_unsup.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 class A; - rand logic[31:0] rdata; + rand logic [31:0] rdata; endclass module t; diff --git a/test_regress/t/t_randomize_this_with.v b/test_regress/t/t_randomize_this_with.v index cc7d3fce5..60bbd72d7 100644 --- a/test_regress/t/t_randomize_this_with.v +++ b/test_regress/t/t_randomize_this_with.v @@ -4,8 +4,10 @@ // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on class Cls; rand int v_rand; @@ -13,7 +15,7 @@ class Cls; task body; int x; v_norand = 42; - x = this.randomize() with {v_rand==0;}; + x = this.randomize() with {v_rand == 0;}; `checkd(v_rand, 0); `checkd(v_norand, 42); endtask diff --git a/test_regress/t/t_randsequence.v b/test_regress/t/t_randsequence.v index 3653f141e..92ae8d320 100644 --- a/test_regress/t/t_randsequence.v +++ b/test_regress/t/t_randsequence.v @@ -6,9 +6,11 @@ // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// verilog_format: off `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); `define check_range(gotv,minv,maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d-%0d\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); $stop; end while(0); `define check_within_30_percent(gotv,val) `check_range((gotv), (val) * 70 / 100, (val) * 130 / 100) +// verilog_format: on module t; diff --git a/test_regress/t/t_randsequence_func.out b/test_regress/t/t_randsequence_func.out index 844aedc05..85994f492 100644 --- a/test_regress/t/t_randsequence_func.out +++ b/test_regress/t/t_randsequence_func.out @@ -1,9 +1,9 @@ -%Error-UNSUPPORTED: t/t_randsequence_func.v:31:23: Unsupported: randsequence production function ports - 31 | void func(int n) : { counts[1] += n; }; +%Error-UNSUPPORTED: t/t_randsequence_func.v:33:23: Unsupported: randsequence production function ports + 33 | void func(int n) : { counts[1] += n; }; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error: t/t_randsequence_func.v:31:23: Input/output/inout does not appear in port list: 'n' - 31 | void func(int n) : { counts[1] += n; }; +%Error: t/t_randsequence_func.v:33:23: Input/output/inout does not appear in port list: 'n' + 33 | void func(int n) : { counts[1] += n; }; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_randsequence_func.v b/test_regress/t/t_randsequence_func.v index c7ff26174..0debc5249 100644 --- a/test_regress/t/t_randsequence_func.v +++ b/test_regress/t/t_randsequence_func.v @@ -6,7 +6,9 @@ // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// verilog_format: off `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); +// verilog_format: on module t; diff --git a/test_regress/t/t_randsequence_randjoin.v b/test_regress/t/t_randsequence_randjoin.v index 857f23622..5b3f17236 100644 --- a/test_regress/t/t_randsequence_randjoin.v +++ b/test_regress/t/t_randsequence_randjoin.v @@ -6,9 +6,11 @@ // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// verilog_format: off `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); `define check_range(gotv,minv,maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d-%0d\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); $stop; end while(0); `define check_within_30_percent(gotv,val) `check_range((gotv), (val) * 70 / 100, (val) * 130 / 100) +// verilog_format: on module t; diff --git a/test_regress/t/t_randsequence_recurse.v b/test_regress/t/t_randsequence_recurse.v index 490be59c0..92fc5f467 100644 --- a/test_regress/t/t_randsequence_recurse.v +++ b/test_regress/t/t_randsequence_recurse.v @@ -6,10 +6,12 @@ // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on -module t(/*AUTOARG*/); +module t; initial begin diff --git a/test_regress/t/t_randsequence_svtests.v b/test_regress/t/t_randsequence_svtests.v index 1b18daa60..6978b9f51 100644 --- a/test_regress/t/t_randsequence_svtests.v +++ b/test_regress/t/t_randsequence_svtests.v @@ -3,7 +3,9 @@ // Based on code Copyright (C) 2019-2021 The SymbiFlow Authors. // SPDX-License-Identifier: ISC +// verilog_format: off `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); +// verilog_format: on module t; diff --git a/test_regress/t/t_resize_lvalue.v b/test_regress/t/t_resize_lvalue.v index 7d4fd97a5..6d7bf873d 100644 --- a/test_regress/t/t_resize_lvalue.v +++ b/test_regress/t/t_resize_lvalue.v @@ -5,13 +5,13 @@ // SPDX-License-Identifier: CC0-1.0 package x_pkg; - typedef bit unsigned [64-1:0] x_reg_data_t ; + typedef bit unsigned [64-1:0] x_reg_data_t; virtual class x_reg; extern virtual task read(output int status, output x_reg_data_t value, input int path); - endclass: x_reg + endclass task x_reg::read(output int status, output x_reg_data_t value, input int path); - endtask: read -endpackage // x_pkg + endtask +endpackage package s_c_env_pkg; import x_pkg::*; @@ -22,11 +22,11 @@ package s_c_env_pkg; val = _val; endfunction extern virtual task read(output int status, output x_reg_data_t value, input int path); - endclass : r_reg_p_s_reg_n_doorbell + endclass task r_reg_p_s_reg_n_doorbell::read(output int status, output x_reg_data_t value, input int path); status = 1; - value = val; - endtask: read + value = val; + endtask class r_block_p_s_reg; rand r_reg_p_s_reg_n_doorbell n_doorbell; @@ -34,7 +34,7 @@ package s_c_env_pkg; function new(int _val); n_doorbell = new(_val); endfunction - endclass : r_block_p_s_reg + endclass class r_top_s_reg; rand r_block_p_s_reg p_s[16]; @@ -42,43 +42,41 @@ package s_c_env_pkg; class s_c_env; r_top_s_reg r_reg_model; - endclass: s_c_env -endpackage // s_c_env_pkg + endclass +endpackage package s_c_sequences_pkg; import x_pkg::*; import s_c_env_pkg::*; class s_c_v_regs_seq; - s_c_env m_env; + s_c_env m_env; virtual task body(); int unsigned p, rdata; - int status; - if (m_env == null) - m_env = new; - if (m_env.r_reg_model == null) - m_env.r_reg_model = new; + int status; + if (m_env == null) m_env = new; + if (m_env.r_reg_model == null) m_env.r_reg_model = new; foreach (m_env.r_reg_model.p_s[p]) begin if (m_env.r_reg_model.p_s[p] == null) begin m_env.r_reg_model.p_s[p] = new(p); end m_env.r_reg_model.p_s[p].n_doorbell.read(status, rdata, 0); if (status != 1) $stop; - if (rdata != p) $stop; + if (rdata != p) $stop; end endtask endclass -endpackage // s_c_sequences_pkg +endpackage module t; s_c_sequences_pkg::s_c_v_regs_seq seq; initial begin - seq = new; - seq.body(); + seq = new; + seq.body(); - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end -endmodule // t +endmodule diff --git a/test_regress/t/t_sarif.out b/test_regress/t/t_sarif.out index 3f98e74a8..79fdaa576 100644 --- a/test_regress/t/t_sarif.out +++ b/test_regress/t/t_sarif.out @@ -1,23 +1,23 @@ -%Warning-MODDUP: t/t_sarif.v:21:8: Duplicate declaration of module: 't' - 21 | module t; +%Warning-MODDUP: t/t_sarif.v:20:8: Duplicate declaration of module: 't' + 20 | module t; | ^ t/t_sarif.v:7:8: ... Location of original declaration - 7 | module t( + 7 | module t ( | ^ ... For warning description see https://verilator.org/warn/MODDUP?v=latest ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message. -%Warning-WIDTHTRUNC: t/t_sarif.v:12:23: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's CONST '5'h1f' generates 5 bits. +%Warning-WIDTHTRUNC: t/t_sarif.v:13:22: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's CONST '5'h1f' generates 5 bits. : ... note: In instance 't' - 12 | wire [1:0] trunced = 5'b11111; - | ^ + 13 | wire [1:0] trunced = 5'b11111; + | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Warning-MULTIDRIVEN: t/t_sarif.v:10:18: Signal has multiple driving blocks with different clocking: 'multidriven' - t/t_sarif.v:15:6: ... Location of first driving block - 15 | multidriven <= '1; - | ^~~~~~~~~~~ - t/t_sarif.v:17:6: ... Location of other driving block - 17 | multidriven <= '0; - | ^~~~~~~~~~~ + t/t_sarif.v:15:26: ... Location of first driving block + 15 | always @(posedge clk1) multidriven <= '1; + | ^~~~~~~~~~~ + t/t_sarif.v:16:26: ... Location of other driving block + 16 | always @(posedge clk2) multidriven <= '0; + | ^~~~~~~~~~~ ... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest ... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message. diff --git a/test_regress/t/t_sarif.sarif.out b/test_regress/t/t_sarif.sarif.out index 6d5fae4b2..425f85e5a 100644 --- a/test_regress/t/t_sarif.sarif.out +++ b/test_regress/t/t_sarif.sarif.out @@ -35,7 +35,7 @@ "level": "warning", "message": { "text": "Duplicate declaration of module: 't'\n... Location of original declaration\n... For warning description see https://verilator.org/warn/MODDUP?v=latest\n... Use \"/* verilator lint_off MODDUP */\" and lint_on around source to disable this message.", - "markdown": "```\n%Warning-MODDUP: t/t_sarif.v:21:8: Duplicate declaration of module: 't'\n 21 | module t; \n | ^\n t/t_sarif.v:7:8: ... Location of original declaration\n 7 | module t(\n | ^\n ... For warning description see https://verilator.org/warn/MODDUP?v=latest\n ... Use \"/* verilator lint_off MODDUP */\" and lint_on around source to disable this message.\n\n```\n" + "markdown": "```\n%Warning-MODDUP: t/t_sarif.v:20:8: Duplicate declaration of module: 't'\n 20 | module t; \n | ^\n t/t_sarif.v:7:8: ... Location of original declaration\n 7 | module t (\n | ^\n ... For warning description see https://verilator.org/warn/MODDUP?v=latest\n ... Use \"/* verilator lint_off MODDUP */\" and lint_on around source to disable this message.\n\n```\n" }, "locations": [ { @@ -45,12 +45,12 @@ }, "region": { "sourceLanguage": "systemverilog", - "startLine": 21, + "startLine": 20, "startColumn": 8, "endColumn": 9, "snippit": { "text": "module t;", - "markdown": "```\n 21 | module t; \n | ^\n\n```\n" + "markdown": "```\n 20 | module t; \n | ^\n\n```\n" } } } @@ -60,7 +60,7 @@ { "message": { "text": "... Location of original declaration\n... For warning description see https://verilator.org/warn/MODDUP?v=latest\n... Use \"/* verilator lint_off MODDUP */\" and lint_on around source to disable this message.", - "markdown": "```\n t/t_sarif.v:7:8: ... Location of original declaration\n 7 | module t(\n | ^\n ... For warning description see https://verilator.org/warn/MODDUP?v=latest\n ... Use \"/* verilator lint_off MODDUP */\" and lint_on around source to disable this message.\n\n```\n" + "markdown": "```\n t/t_sarif.v:7:8: ... Location of original declaration\n 7 | module t (\n | ^\n ... For warning description see https://verilator.org/warn/MODDUP?v=latest\n ... Use \"/* verilator lint_off MODDUP */\" and lint_on around source to disable this message.\n\n```\n" }, "physicalLocation": { "artifactLocation": { @@ -72,8 +72,8 @@ "startColumn": 8, "endColumn": 9, "snippit": { - "text": "module t(", - "markdown": "```\n 7 | module t(\n | ^\n\n```\n" + "text": "module t (", + "markdown": "```\n 7 | module t (\n | ^\n\n```\n" } } } @@ -86,7 +86,7 @@ "level": "warning", "message": { "text": "Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's CONST '5'h1f' generates 5 bits.\n... note: In instance 't'\n... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest\n... Use \"/* verilator lint_off WIDTHTRUNC */\" and lint_on around source to disable this message.", - "markdown": "```\n%Warning-WIDTHTRUNC: t/t_sarif.v:12:23: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's CONST '5'h1f' generates 5 bits.\n : ... note: In instance 't'\n 12 | wire [1:0] trunced = 5'b11111; \n | ^\n ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest\n ... Use \"/* verilator lint_off WIDTHTRUNC */\" and lint_on around source to disable this message.\n\n```\n" + "markdown": "```\n%Warning-WIDTHTRUNC: t/t_sarif.v:13:22: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's CONST '5'h1f' generates 5 bits.\n : ... note: In instance 't'\n 13 | wire [1:0] trunced = 5'b11111; \n | ^\n ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest\n ... Use \"/* verilator lint_off WIDTHTRUNC */\" and lint_on around source to disable this message.\n\n```\n" }, "locations": [ { @@ -96,12 +96,12 @@ }, "region": { "sourceLanguage": "systemverilog", - "startLine": 12, - "startColumn": 23, - "endColumn": 24, + "startLine": 13, + "startColumn": 22, + "endColumn": 23, "snippit": { - "text": " wire [1:0] trunced = 5'b11111;", - "markdown": "```\n 12 | wire [1:0] trunced = 5'b11111; \n | ^\n\n```\n" + "text": " wire [1:0] trunced = 5'b11111;", + "markdown": "```\n 13 | wire [1:0] trunced = 5'b11111; \n | ^\n\n```\n" } } } @@ -114,7 +114,7 @@ "level": "warning", "message": { "text": "Signal has multiple driving blocks with different clocking: 'multidriven'\n... Location of first driving block\n... Location of other driving block\n... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest\n... Use \"/* verilator lint_off MULTIDRIVEN */\" and lint_on around source to disable this message.", - "markdown": "```\n%Warning-MULTIDRIVEN: t/t_sarif.v:10:18: Signal has multiple driving blocks with different clocking: 'multidriven'\n t/t_sarif.v:15:6: ... Location of first driving block\n 15 | multidriven <= '1;\n | ^~~~~~~~~~~\n t/t_sarif.v:17:6: ... Location of other driving block\n 17 | multidriven <= '0;\n | ^~~~~~~~~~~\n ... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest\n ... Use \"/* verilator lint_off MULTIDRIVEN */\" and lint_on around source to disable this message.\n\n```\n" + "markdown": "```\n%Warning-MULTIDRIVEN: t/t_sarif.v:10:18: Signal has multiple driving blocks with different clocking: 'multidriven'\n t/t_sarif.v:15:26: ... Location of first driving block\n 15 | always @(posedge clk1) multidriven <= '1;\n | ^~~~~~~~~~~\n t/t_sarif.v:16:26: ... Location of other driving block\n 16 | always @(posedge clk2) multidriven <= '0;\n | ^~~~~~~~~~~\n ... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest\n ... Use \"/* verilator lint_off MULTIDRIVEN */\" and lint_on around source to disable this message.\n\n```\n" }, "locations": [ { @@ -128,8 +128,8 @@ "startColumn": 18, "endColumn": 29, "snippit": { - "text": " output logic multidriven);", - "markdown": "```\n 10 | output logic multidriven);\n | ^~~~~~~~~~~\n\n```\n" + "text": " output logic multidriven", + "markdown": "```\n 10 | output logic multidriven\n | ^~~~~~~~~~~\n\n```\n" } } } @@ -139,7 +139,7 @@ { "message": { "text": "... Location of first driving block", - "markdown": "```\n t/t_sarif.v:15:6: ... Location of first driving block\n 15 | multidriven <= '1;\n | ^~~~~~~~~~~\n\n```\n" + "markdown": "```\n t/t_sarif.v:15:26: ... Location of first driving block\n 15 | always @(posedge clk1) multidriven <= '1;\n | ^~~~~~~~~~~\n\n```\n" }, "physicalLocation": { "artifactLocation": { @@ -148,11 +148,11 @@ "region": { "sourceLanguage": "systemverilog", "startLine": 15, - "startColumn": 6, - "endColumn": 17, + "startColumn": 26, + "endColumn": 37, "snippit": { - "text": " multidriven <= '1;", - "markdown": "```\n 15 | multidriven <= '1;\n | ^~~~~~~~~~~\n\n```\n" + "text": " always @(posedge clk1) multidriven <= '1;", + "markdown": "```\n 15 | always @(posedge clk1) multidriven <= '1;\n | ^~~~~~~~~~~\n\n```\n" } } } @@ -160,7 +160,7 @@ { "message": { "text": "... Location of other driving block\n... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest\n... Use \"/* verilator lint_off MULTIDRIVEN */\" and lint_on around source to disable this message.", - "markdown": "```\n t/t_sarif.v:17:6: ... Location of other driving block\n 17 | multidriven <= '0;\n | ^~~~~~~~~~~\n ... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest\n ... Use \"/* verilator lint_off MULTIDRIVEN */\" and lint_on around source to disable this message.\n\n```\n" + "markdown": "```\n t/t_sarif.v:16:26: ... Location of other driving block\n 16 | always @(posedge clk2) multidriven <= '0;\n | ^~~~~~~~~~~\n ... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest\n ... Use \"/* verilator lint_off MULTIDRIVEN */\" and lint_on around source to disable this message.\n\n```\n" }, "physicalLocation": { "artifactLocation": { @@ -168,12 +168,12 @@ }, "region": { "sourceLanguage": "systemverilog", - "startLine": 17, - "startColumn": 6, - "endColumn": 17, + "startLine": 16, + "startColumn": 26, + "endColumn": 37, "snippit": { - "text": " multidriven <= '0;", - "markdown": "```\n 17 | multidriven <= '0;\n | ^~~~~~~~~~~\n\n```\n" + "text": " always @(posedge clk2) multidriven <= '0;", + "markdown": "```\n 16 | always @(posedge clk2) multidriven <= '0;\n | ^~~~~~~~~~~\n\n```\n" } } } diff --git a/test_regress/t/t_sarif.v b/test_regress/t/t_sarif.v index 7af1b0fab..f98e3d12b 100644 --- a/test_regress/t/t_sarif.v +++ b/test_regress/t/t_sarif.v @@ -4,17 +4,16 @@ // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module t( +module t ( input clk1, input clk2, - output logic multidriven); + output logic multidriven +); - wire [1:0] trunced = 5'b11111; // Warned + wire [1:0] trunced = 5'b11111; // Warned - always @ (posedge clk1) - multidriven <= '1; - always @ (posedge clk2) - multidriven <= '0; + always @(posedge clk1) multidriven <= '1; + always @(posedge clk2) multidriven <= '0; endmodule diff --git a/test_regress/t/t_scheduling_initial_event.v b/test_regress/t/t_scheduling_initial_event.v index abfe7ee3a..c3e2ee377 100644 --- a/test_regress/t/t_scheduling_initial_event.v +++ b/test_regress/t/t_scheduling_initial_event.v @@ -4,8 +4,10 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on module top; logic pEdge = 1'b0; @@ -75,22 +77,22 @@ module top; `checkh(changePCnt, 3); `checkh(changeNCnt, 3); - `checkh(pEdgeTime[0], 0); + `checkh(pEdgeTime[0], 0); `checkh(pEdgeTime[1], 20); `checkh(pEdgeTime[2], -1); - `checkh(nEdgeTime[0], 0); + `checkh(nEdgeTime[0], 0); `checkh(nEdgeTime[1], 20); `checkh(nEdgeTime[2], -1); - `checkh(edgePTime[0], 0); + `checkh(edgePTime[0], 0); `checkh(edgePTime[1], 10); `checkh(edgePTime[2], 20); - `checkh(edgeNTime[0], 0); + `checkh(edgeNTime[0], 0); `checkh(edgeNTime[1], 10); `checkh(edgeNTime[2], 20); - `checkh(changePTime[0], 0); + `checkh(changePTime[0], 0); `checkh(changePTime[1], 10); `checkh(changePTime[2], 20); - `checkh(changeNTime[0], 0); + `checkh(changeNTime[0], 0); `checkh(changeNTime[1], 10); `checkh(changeNTime[2], 20); $write("*-* All Finished *-*\n"); @@ -104,4 +106,4 @@ module top; always @(changeP) changePTime[changePCnt++] = $time; always @(changeN) changeNTime[changeNCnt++] = $time; -endmodule // test +endmodule // test diff --git a/test_regress/t/t_scheduling_many_clocks.v b/test_regress/t/t_scheduling_many_clocks.v index ca9d71edc..009a8eace 100644 --- a/test_regress/t/t_scheduling_many_clocks.v +++ b/test_regress/t/t_scheduling_many_clocks.v @@ -4,15 +4,14 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on -module t(/*AUTOARG*/ - // Inputs - clk - ); - - input clk; +module t ( + input clk +); localparam int ITERATIONS = 5; localparam int N = 227; diff --git a/test_regress/t/t_sequence_unused.v b/test_regress/t/t_sequence_unused.v index 0d57ea468..2ae824e2e 100644 --- a/test_regress/t/t_sequence_unused.v +++ b/test_regress/t/t_sequence_unused.v @@ -25,9 +25,9 @@ endinterface module t ( input clk - ); +); - apb_if ifc(clk); + apb_if ifc (clk); initial $finish; diff --git a/test_regress/t/t_simulate_array.v b/test_regress/t/t_simulate_array.v index 77c19e2ce..055954f3b 100644 --- a/test_regress/t/t_simulate_array.v +++ b/test_regress/t/t_simulate_array.v @@ -5,20 +5,20 @@ // SPDX-License-Identifier: CC0-1.0 function integer fun; -integer array[0:0]; -begin + integer array[0:0]; + begin array[0] = 10; fun = array[0]; -end + end endfunction module test (); -begin + begin localparam something = fun(); initial begin if (something !== 10) $stop; $write("*-* All Finished *-*\n"); $finish; end -end + end endmodule diff --git a/test_regress/t/t_split_var_auto.v b/test_regress/t/t_split_var_auto.v index 35da922e4..8055bc9a1 100644 --- a/test_regress/t/t_split_var_auto.v +++ b/test_regress/t/t_split_var_auto.v @@ -4,15 +4,14 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on -module t(/*AUTOARG*/ - // Inputs - clk - ); - - input clk; +module t ( + input clk +); logic [31:0] cnt = 0; diff --git a/test_regress/t/t_split_var_issue.v b/test_regress/t/t_split_var_issue.v index 0c7be6ebb..daf23cb9c 100644 --- a/test_regress/t/t_split_var_issue.v +++ b/test_regress/t/t_split_var_issue.v @@ -34,10 +34,10 @@ module sub ( end endmodule -module t (/*AUTOARG*/ - clk - ); - input clk; +module t ( + input clk +); + int cyc = 0; always @ (posedge clk) begin cyc <= cyc + 1; diff --git a/test_regress/t/t_std_randomize.v b/test_regress/t/t_std_randomize.v index ba9b2b5ee..e93c9a753 100644 --- a/test_regress/t/t_std_randomize.v +++ b/test_regress/t/t_std_randomize.v @@ -4,8 +4,10 @@ // any use, without warranty, 2025 by PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop; `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on class std_randomize_class; diff --git a/test_regress/t/t_string_octal.v b/test_regress/t/t_string_octal.v index 035c31a7b..0dc77466f 100644 --- a/test_regress/t/t_string_octal.v +++ b/test_regress/t/t_string_octal.v @@ -4,8 +4,10 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checko(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; string s; diff --git a/test_regress/t/t_struct_negate.v b/test_regress/t/t_struct_negate.v index 6803ef09a..bc0b17a96 100644 --- a/test_regress/t/t_struct_negate.v +++ b/test_regress/t/t_struct_negate.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 module t ( - input logic signed [64:0] i_x, + input logic signed [64:0] i_x, output logic signed [64:0] o_y ); struct {logic signed [64:0] m_x;} s; diff --git a/test_regress/t/t_struct_unpacked_param.v b/test_regress/t/t_struct_unpacked_param.v index 634f3bc1b..9736c98a1 100644 --- a/test_regress/t/t_struct_unpacked_param.v +++ b/test_regress/t/t_struct_unpacked_param.v @@ -37,7 +37,12 @@ module t; // Only localparams are supported, returning constant unpacked structure // from function or passing unpacked structure as parameters is not // (yet) supported - localparam struct_t MY_STRUCT = '{a: 10, b: 5, c: 20, sub: '{a: 100, b: 200, c: 150, subsub: '{default: 10}}}; + localparam struct_t MY_STRUCT = '{ + a: 10, + b: 5, + c: 20, + sub: '{a: 100, b: 200, c: 150, subsub: '{default: 10}} + }; // Make standalone localparam to ensure MY_STRUCT is const localparam int C = MY_STRUCT.c; diff --git a/test_regress/t/t_sys_file_basic_uz.v b/test_regress/t/t_sys_file_basic_uz.v index a407299f1..ed9d61d70 100644 --- a/test_regress/t/t_sys_file_basic_uz.v +++ b/test_regress/t/t_sys_file_basic_uz.v @@ -4,16 +4,16 @@ // any use, without warranty, 2030 by Stephen Henry. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on + module t; int fdin_bin, fdout_txt, fdout_bin; `define STRINGIFY(x) `"x`" -`define checkh(gotv,expv) \ - do if ((gotv) !== (expv)) begin\ - $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv));\ - end while(0) - // // task automatic test1; begin diff --git a/test_regress/t/t_sys_file_scan2.v b/test_regress/t/t_sys_file_scan2.v index 254ee5805..a278bf57c 100644 --- a/test_regress/t/t_sys_file_scan2.v +++ b/test_regress/t/t_sys_file_scan2.v @@ -4,9 +4,11 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; int cfg_file, f_stat; diff --git a/test_regress/t/t_timing_debug1.py b/test_regress/t/t_timing_debug1.py index edded70be..9318069af 100755 --- a/test_regress/t/t_timing_debug1.py +++ b/test_regress/t/t_timing_debug1.py @@ -12,7 +12,8 @@ import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_timing_sched.v" -test.compile(verilator_flags2=["--exe --main --timing"]) +test.compile( + verilator_flags2=["--binary", "--timing", "--inline-cfuncs", "0", "-CFLAGS", "-DVL_DEBUG"]) test.execute(all_run_flags=["+verilator+debug"]) diff --git a/test_regress/t/t_timing_debug2.py b/test_regress/t/t_timing_debug2.py index e6f816ca2..85d63a27d 100755 --- a/test_regress/t/t_timing_debug2.py +++ b/test_regress/t/t_timing_debug2.py @@ -12,7 +12,8 @@ import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_timing_class.v" -test.compile(verilator_flags2=["--exe --main --timing"]) +# Disable --inline-cfuncs so debug traces show all function entries +test.compile(verilator_flags2=["--exe --main --timing --inline-cfuncs 0"]) test.execute(all_run_flags=["+verilator+debug"]) diff --git a/test_regress/t/t_timing_finish2.v b/test_regress/t/t_timing_finish2.v index f715adbcb..57e13c8fd 100644 --- a/test_regress/t/t_timing_finish2.v +++ b/test_regress/t/t_timing_finish2.v @@ -4,8 +4,10 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module tb2 (); parameter CLK_PERIOD = 2; diff --git a/test_regress/t/t_timing_intra_assign_func.v b/test_regress/t/t_timing_intra_assign_func.v index 0e81f3f35..1c8d62fd1 100644 --- a/test_regress/t/t_timing_intra_assign_func.v +++ b/test_regress/t/t_timing_intra_assign_func.v @@ -26,10 +26,10 @@ module t; end initial begin - #1; - ia = 4'd2; - #10; - $write("*-* All Finished *-*\n"); - $finish; + #1; + ia = 4'd2; + #10; + $write("*-* All Finished *-*\n"); + $finish; end endmodule diff --git a/test_regress/t/t_timing_suspend_two_retrigger.v b/test_regress/t/t_timing_suspend_two_retrigger.v index 8180f2fef..840e9790f 100644 --- a/test_regress/t/t_timing_suspend_two_retrigger.v +++ b/test_regress/t/t_timing_suspend_two_retrigger.v @@ -13,7 +13,7 @@ module top; #10; ->b; $display("Sleeping at %0t", $time); - @(a or b); // This must wake at due to 'a' from the other block + @(a or b); // This must wake at due to 'a' from the other block $display("Waking at %0t", $time); if ($time != 20) $stop; @@ -21,7 +21,7 @@ module top; ->a; ->b; $display("Sleeping at %0t", $time); - @(a or b); // This must wake at due to 'a' from the other block + @(a or b); // This must wake at due to 'a' from the other block $display("Waking at %0t", $time); if ($time != 40) $stop; diff --git a/test_regress/t/t_typedef_iface_typedef.v b/test_regress/t/t_typedef_iface_typedef.v index 8c799a496..0331d03ef 100644 --- a/test_regress/t/t_typedef_iface_typedef.v +++ b/test_regress/t/t_typedef_iface_typedef.v @@ -5,35 +5,29 @@ // SPDX-License-Identifier: CC0-1.0 // // assign localparam from interface typedef, single level nesting -// +// verilog_format: off `define stop $stop -`define checkh(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0h exp=%0h\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0h exp=%0h\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on interface x_if #( - parameter int p_awidth = 4 - ,parameter int p_dwidth = 7 -)(); + parameter int p_awidth = 4, + parameter int p_dwidth = 7 +) (); typedef struct packed { logic [p_awidth-1:0] addr; logic [p_dwidth-1:0] data; } rq_t; - typedef struct packed { - logic [p_dwidth-1:0] data; - } rs_t; + typedef struct packed {logic [p_dwidth-1:0] data;} rs_t; endinterface -module top(); +module top (); x_if #( - .p_awidth(16) - ,.p_dwidth(8) - ) if0(); + .p_awidth(16), + .p_dwidth(8) + ) if0 (); typedef if0.rq_t p0_rq_t; diff --git a/test_regress/t/t_typedef_iface_typedef2.v b/test_regress/t/t_typedef_iface_typedef2.v index 69078a9d4..a43f480fc 100644 --- a/test_regress/t/t_typedef_iface_typedef2.v +++ b/test_regress/t/t_typedef_iface_typedef2.v @@ -6,18 +6,14 @@ // interface x_if #( - parameter int a_width = 3 -)(); + parameter int a_width = 3 +) (); - typedef struct packed { - logic [a_width-1:0] addr; - } rq_t; + typedef struct packed {logic [a_width-1:0] addr;} rq_t; endinterface -module top(); - x_if #( - .a_width(8) - ) if0(); +module top (); + x_if #(.a_width(8)) if0 (); typedef if0.rq_t p0_t; diff --git a/test_regress/t/t_typedef_iface_typedef3.v b/test_regress/t/t_typedef_iface_typedef3.v index 1f91f0d3f..9125ef207 100644 --- a/test_regress/t/t_typedef_iface_typedef3.v +++ b/test_regress/t/t_typedef_iface_typedef3.v @@ -5,27 +5,17 @@ // SPDX-License-Identifier: CC0-1.0 // // assign localparam from interface typedef, single level nesting -// +// verilog_format: off `define stop $stop -`define checkd(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0d exp=%0d\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); - -`define checkh(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0h exp=%0h\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0h exp=%0h\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on interface x_if #( - parameter int p_awidth = 4 - ,parameter int p_dwidth = 7 -)(); + parameter int p_awidth = 4, + parameter int p_dwidth = 7 +) (); localparam int Bits = p_awidth + p_dwidth; typedef struct packed { logic [p_awidth-1:0] addr; @@ -34,16 +24,19 @@ interface x_if #( endinterface interface y_if #( - parameter int p_awidth = 4 - ,parameter int p_dwidth = 7 -)(); - x_if #(.p_awidth(p_awidth), .p_dwidth(p_dwidth)) x_if_a[2] (); + parameter int p_awidth = 4, + parameter int p_dwidth = 7 +) (); + x_if #( + .p_awidth(p_awidth), + .p_dwidth(p_dwidth) + ) x_if_a[2] (); endinterface -module top(); +module top (); y_if #( - .p_awidth(16) - ,.p_dwidth(8) + .p_awidth(16), + .p_dwidth(8) ) y_if0 (); typedef y_if0.x_if_a[0].rq_t rq_t; @@ -57,8 +50,8 @@ module top(); initial begin #1; - `checkh(rq.addr,16'h1234); - `checkh(rq.data,8'h37); + `checkh(rq.addr, 16'h1234); + `checkh(rq.data, 8'h37); $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_typedef_iface_typedef4.v b/test_regress/t/t_typedef_iface_typedef4.v index 5486e57e8..9899ce41f 100644 --- a/test_regress/t/t_typedef_iface_typedef4.v +++ b/test_regress/t/t_typedef_iface_typedef4.v @@ -5,49 +5,35 @@ // SPDX-License-Identifier: CC0-1.0 // // assign localparam from interface typedef, single level nesting -// +// verilog_format: off `define stop $stop -`define checkd(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0d exp=%0d\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); - -`define checkh(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0h exp=%0h\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0h exp=%0h\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on interface x_if #( - parameter int p_awidth = 4 -)(); - typedef struct packed { - logic [p_awidth-1:0] addr; - } rq_t; + parameter int p_awidth = 4 +) (); + typedef struct packed {logic [p_awidth-1:0] addr;} rq_t; endinterface interface y_if #( - parameter int p_dwidth = 7 -)(); - typedef struct packed { - logic [p_dwidth-1:0] data; - } rs_t; + parameter int p_dwidth = 7 +) (); + typedef struct packed {logic [p_dwidth-1:0] data;} rs_t; endinterface interface z_if #( - parameter int p_awidth = 3 - ,parameter int p_dwidth = 9 + parameter int p_awidth = 3, + parameter int p_dwidth = 9 ); - x_if #(p_awidth) x_if0(); - y_if #(p_dwidth) y_if0(); + x_if #(p_awidth) x_if0 (); + y_if #(p_dwidth) y_if0 (); endinterface -module a_top( - z_if z_if0 +module a_top ( + z_if z_if0 ); typedef z_if0.x_if0.rq_t rq_t; typedef z_if0.y_if0.rs_t rs_t; @@ -62,16 +48,19 @@ module a_top( initial begin #1; - `checkh(rq.addr,16'h1234); - `checkh(rs.data,8'ha5); + `checkh(rq.addr, 16'h1234); + `checkh(rs.data, 8'ha5); end endmodule -module top(); - z_if #(.p_awidth(16) ,.p_dwidth(8)) z_if0(); +module top (); + z_if #( + .p_awidth(16), + .p_dwidth(8) + ) z_if0 (); - a_top a_top(z_if0); + a_top a_top (z_if0); initial begin #1; diff --git a/test_regress/t/t_typedef_iface_typedef5.v b/test_regress/t/t_typedef_iface_typedef5.v index 5735c10af..b384185c1 100644 --- a/test_regress/t/t_typedef_iface_typedef5.v +++ b/test_regress/t/t_typedef_iface_typedef5.v @@ -5,49 +5,38 @@ // SPDX-License-Identifier: CC0-1.0 // // assign localparam from interface typedef, single level nesting -// +// verilog_format: off `define stop $stop -`define checkd(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0d exp=%0d\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); - -`define checkh(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0h exp=%0h\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0h exp=%0h\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on interface x_if #( - parameter int p_awidth = 4 -)(); - typedef struct packed { - logic [p_awidth-1:0] addr; - } rq_t; + parameter int p_awidth = 4 +) (); + typedef struct packed {logic [p_awidth-1:0] addr;} rq_t; endinterface interface y_if #( - parameter int p_dwidth = 7 -)(); - typedef struct packed { - logic [p_dwidth-1:0] data; - } rs_t; + parameter int p_dwidth = 7 +) (); + typedef struct packed {logic [p_dwidth-1:0] data;} rs_t; endinterface interface z_if #( - parameter int p_awidth = 3 - ,parameter int p_dwidth = 9 + parameter int p_awidth = 3, + parameter int p_dwidth = 9 ); - x_if #(p_awidth) x_if0(); - y_if #(p_dwidth) y_if0(); + x_if #(p_awidth) x_if0 (); + y_if #(p_dwidth) y_if0 (); endinterface -module top(); - z_if #(.p_awidth(16) ,.p_dwidth(8)) if0(); +module top (); + z_if #( + .p_awidth(16), + .p_dwidth(8) + ) if0 (); typedef if0.x_if0.rq_t rq_t; typedef if0.y_if0.rs_t rs_t; @@ -62,8 +51,8 @@ module top(); initial begin #1; - `checkh(rq.addr,16'h1234); - `checkh(rs.data,8'ha5); + `checkh(rq.addr, 16'h1234); + `checkh(rs.data, 8'ha5); $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_typedef_iface_typedef6.v b/test_regress/t/t_typedef_iface_typedef6.v index db4b90ef7..8a824fef4 100644 --- a/test_regress/t/t_typedef_iface_typedef6.v +++ b/test_regress/t/t_typedef_iface_typedef6.v @@ -5,49 +5,38 @@ // SPDX-License-Identifier: CC0-1.0 // // assign localparam from interface typedef, single level nesting -// +// verilog_format: off `define stop $stop -`define checkd(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0d exp=%0d\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); - -`define checkh(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0h exp=%0h\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0h exp=%0h\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on interface x_if #( - parameter int p_awidth = 4 -)(); - typedef struct packed { - logic [p_awidth-1:0] addr; - } rq_t; + parameter int p_awidth = 4 +) (); + typedef struct packed {logic [p_awidth-1:0] addr;} rq_t; endinterface interface y_if #( - parameter int p_dwidth = 7 -)(); - typedef struct packed { - logic [p_dwidth-1:0] data; - } rs_t; + parameter int p_dwidth = 7 +) (); + typedef struct packed {logic [p_dwidth-1:0] data;} rs_t; endinterface interface z_if #( - parameter int p_awidth = 3 - ,parameter int p_dwidth = 9 + parameter int p_awidth = 3, + parameter int p_dwidth = 9 ); - x_if #(p_awidth) x_if0(); - y_if #(p_dwidth) y_if0(); + x_if #(p_awidth) x_if0 (); + y_if #(p_dwidth) y_if0 (); endinterface -module top(); - z_if #(.p_awidth(16) ,.p_dwidth(8)) if0 [2] (); +module top (); + z_if #( + .p_awidth(16), + .p_dwidth(8) + ) if0[2] (); typedef if0[0].x_if0.rq_t rq_t; @@ -59,7 +48,7 @@ module top(); initial begin #1; - `checkh(rq.addr,16'h1234); + `checkh(rq.addr, 16'h1234); $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_typedef_iface_typedef7.v b/test_regress/t/t_typedef_iface_typedef7.v index 2842fad0c..968579e3f 100644 --- a/test_regress/t/t_typedef_iface_typedef7.v +++ b/test_regress/t/t_typedef_iface_typedef7.v @@ -6,24 +6,19 @@ // // Chained typedef aliases from an interface typedef +// verilog_format: off `define stop $stop -`define checkh(gotv,expv) \ - do if ((gotv) !== (expv)) begin \ - $write("%%Error: %s:%0d: got=%0h exp=%0h\n", \ - `__FILE__,`__LINE__, (gotv), (expv)); \ - `stop; \ - end while(0); +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0h exp=%0h\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on interface x_if #( - parameter int p_awidth = 4 -)(); - typedef struct packed { - logic [p_awidth-1:0] addr; - } rq_t; + parameter int p_awidth = 4 +) (); + typedef struct packed {logic [p_awidth-1:0] addr;} rq_t; endinterface -module top(); - x_if #(.p_awidth(16)) if0(); +module top (); + x_if #(.p_awidth(16)) if0 (); // First alias of interface typedef typedef if0.rq_t my_rq_t; @@ -38,7 +33,7 @@ module top(); initial begin #1; - `checkh(rq.addr,16'h1234); + `checkh(rq.addr, 16'h1234); $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_typedef_param_class.v b/test_regress/t/t_typedef_param_class.v index 7d6fc6ac6..21a4da1ef 100644 --- a/test_regress/t/t_typedef_param_class.v +++ b/test_regress/t/t_typedef_param_class.v @@ -4,7 +4,9 @@ // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 -class Class1 #(type T); +class Class1 #( + type T +); typedef T::Some_type2 Some_type1; endclass diff --git a/test_regress/t/t_udp_nonsequential_x.v b/test_regress/t/t_udp_nonsequential_x.v index d2643cd5e..d835943db 100644 --- a/test_regress/t/t_udp_nonsequential_x.v +++ b/test_regress/t/t_udp_nonsequential_x.v @@ -28,9 +28,9 @@ module t (); endmodule -primitive not1 (q, d); +primitive not1(q, d); output q; - input d; + input d; table 0 : 1; 1 : 0; @@ -38,9 +38,9 @@ primitive not1 (q, d); endtable endprimitive -primitive not2 (q, d); +primitive not2(q, d); output q; - input d; + input d; table 0 : 1; 1 : 0; diff --git a/test_regress/t/t_udp_sequential_x.v b/test_regress/t/t_udp_sequential_x.v index 222ea9b1f..ce12aaef6 100644 --- a/test_regress/t/t_udp_sequential_x.v +++ b/test_regress/t/t_udp_sequential_x.v @@ -5,14 +5,20 @@ // SPDX-License-Identifier: CC0-1.0 module t ( - input wire clk - ); + input wire clk +); wire q1; - pos i_pos(q1, clk); + pos i_pos ( + q1, + clk + ); wire q2; - neg i_neg(q2, clk); + neg i_neg ( + q2, + clk + ); integer cycle = 0; always @(posedge clk) begin @@ -31,10 +37,10 @@ module t ( endmodule -primitive pos (q, clk); +primitive pos(q, clk); output q; - reg q; - input clk; + reg q; + input clk; table (01) : ? : 0; // Explicitly set the output to X on clk 0->X edge. @@ -48,10 +54,10 @@ primitive pos (q, clk); endtable endprimitive -primitive neg (q, clk); +primitive neg(q, clk); output q; - reg q; - input clk; + reg q; + input clk; table (10) : ? : 0; // Explicitly set the output to X on clk X->0 edge. diff --git a/test_regress/t/t_unpacked_to_queue.v b/test_regress/t/t_unpacked_to_queue.v index 16191e042..302c2d537 100644 --- a/test_regress/t/t_unpacked_to_queue.v +++ b/test_regress/t/t_unpacked_to_queue.v @@ -5,6 +5,7 @@ // without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop() `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin \ $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", \ @@ -13,6 +14,7 @@ `define checks(gotv,expv) do if ((gotv) != (expv)) begin \ $write("%%Error: %s:%0d: got='%s' exp='%s'\n", \ `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on class check #(parameter WIDTH=8); diff --git a/test_regress/t/t_unpacked_wide_unknown.v b/test_regress/t/t_unpacked_wide_unknown.v index 208f99481..e9a8f4eae 100644 --- a/test_regress/t/t_unpacked_wide_unknown.v +++ b/test_regress/t/t_unpacked_wide_unknown.v @@ -6,7 +6,7 @@ typedef struct packed { logic [149:0] hdr; - logic [1:0] vc; + logic [1:0] vc; } packet_t; module t; diff --git a/test_regress/t/t_unroll_automatic_task_fork.v b/test_regress/t/t_unroll_automatic_task_fork.v index b77d25261..60a2b7045 100644 --- a/test_regress/t/t_unroll_automatic_task_fork.v +++ b/test_regress/t/t_unroll_automatic_task_fork.v @@ -27,53 +27,49 @@ module t; automatic int mod = m; automatic int ch = i; fork : forked_block - task_example(mod, ch); + task_example(mod, ch); join end end - #10 - $write("*-* Test 1 Finished *-*\n"); + #10 $write("*-* Test 1 Finished *-*\n"); for (int m = 0; m < 2; m++) begin for (int i = 0; i < 2; i++) begin : forked_loop automatic int mod = m; automatic int ch = i; fork : forked_block - task_example(mod, ch); + task_example(mod, ch); join_any end end - #10 - $write("*-* Test 2 Finished *-*\n"); + #10 $write("*-* Test 2 Finished *-*\n"); for (int m = 0; m < 2; m++) begin for (int i = 0; i < 2; i++) begin : forked_loop automatic int mod = m; automatic int ch = i; fork : forked_block - task_example(mod, ch); + task_example(mod, ch); $display("extra statement"); join_any end end - #10 - $write("*-* Test 3 Finished *-*\n"); + #10 $write("*-* Test 3 Finished *-*\n"); for (int m = 0; m < 2; m++) begin for (int i = 0; i < 2; i++) begin : forked_loop automatic int mod = m; automatic int ch = i; fork : forked_block - task_example(mod, ch); + task_example(mod, ch); join_none end end - #10 - $write("*-* Test 4 Finished *-*\n"); + #10 $write("*-* Test 4 Finished *-*\n"); $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_unroll_stmt.v b/test_regress/t/t_unroll_stmt.v index 659d9b3e9..d6e7e1a8c 100644 --- a/test_regress/t/t_unroll_stmt.v +++ b/test_regress/t/t_unroll_stmt.v @@ -24,7 +24,7 @@ module t; // While loop with non-trivial init begin automatic int i = 0; - automatic int j = 5; // Not a variable + automatic int j = 5; // Not a variable while (i < j) begin : loop_2 $display("loop_2 %0d %0d", i++, j); end @@ -32,15 +32,15 @@ module t; // Do loop with non-trivial init begin automatic int i = 5; - automatic int j = 0; // Not a variable + automatic int j = 0; // Not a variable do begin : loop_3 $display("loop_3 %0d %0d", --i, j); end while (i > j); end // Do loop that executes once - replaced by V3Const, not unrolled - do begin: loop_4 + do begin : loop_4 $display("loop_4"); - end while(0); + end while (0); // Loop with inlined function as condition static_loop_cond = 0; while (f_loop_cond()) begin : loop_5 @@ -52,8 +52,8 @@ module t; for (int i = 0; i < 10; ++i) begin : loop_6 if (!found) begin $display("loop_6 %0d", i); - if (i == $c32("5")) begin // Unknown condition - $display("stopping loop_6"); // This line is important + if (i == $c32("5")) begin // Unknown condition + $display("stopping loop_6"); // This line is important found = 1; end end diff --git a/test_regress/t/t_var_port_json_only.out b/test_regress/t/t_var_port_json_only.out index 4807228dd..b4eb00370 100644 --- a/test_regress/t/t_var_port_json_only.out +++ b/test_regress/t/t_var_port_json_only.out @@ -91,9 +91,9 @@ ]} ]}, {"type":"BASICDTYPE","name":"logic","addr":"(Z)","loc":"d,38:17,38:18","dtypep":"(Z)","keyword":"logic","range":"5:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(U)","loc":"d,34:27,34:28","dtypep":"(U)","keyword":"logic","range":"5:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"integer","addr":"(G)","loc":"d,18:19,18:26","dtypep":"(G)","keyword":"integer","range":"31:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(VB)","loc":"d,40:37,40:38","dtypep":"(VB)","keyword":"logic","range":"31:0","generic":true,"rangep": []} + {"type":"BASICDTYPE","name":"logic","addr":"(U)","loc":"d,34:27,34:28","dtypep":"(U)","keyword":"logic","range":"5:0","generic":true,"signed":true,"rangep": []}, + {"type":"BASICDTYPE","name":"integer","addr":"(G)","loc":"d,18:19,18:26","dtypep":"(G)","keyword":"integer","range":"31:0","generic":true,"signed":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(VB)","loc":"d,40:37,40:38","dtypep":"(VB)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ diff --git a/test_regress/t/t_var_ref.v b/test_regress/t/t_var_ref.v index 494abbe9a..81feb657a 100644 --- a/test_regress/t/t_var_ref.v +++ b/test_regress/t/t_var_ref.v @@ -4,7 +4,10 @@ // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv));; end while(0); +// verilog_format: off +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t(/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_verilated_debug.out b/test_regress/t/t_verilated_debug.out index 03bf5d11b..e4f93ddf7 100644 --- a/test_regress/t/t_verilated_debug.out +++ b/test_regress/t/t_verilated_debug.out @@ -37,7 +37,6 @@ internalsDump: -V{t#,#}+ Vt_verilated_debug___024root___eval_phase__nba -V{t#,#}+ Vt_verilated_debug___024root___trigger_anySet__act -V{t#,#}+ Vt_verilated_debug___024root___eval_nba --V{t#,#}+ Vt_verilated_debug___024root___nba_sequent__TOP__0 *-* All Finished *-* -V{t#,#}+ Vt_verilated_debug___024root___trigger_clear__act -V{t#,#}+ Vt_verilated_debug___024root___eval_phase__act diff --git a/test_regress/t/t_virtual_interface_delayed.v b/test_regress/t/t_virtual_interface_delayed.v index 9901bf994..20df1840e 100644 --- a/test_regress/t/t_virtual_interface_delayed.v +++ b/test_regress/t/t_virtual_interface_delayed.v @@ -4,8 +4,10 @@ // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on interface Ifc; bit [7:0] rdata; diff --git a/test_regress/t/t_virtual_interface_param.v b/test_regress/t/t_virtual_interface_param.v index 674f2c7c9..032c01fd2 100644 --- a/test_regress/t/t_virtual_interface_param.v +++ b/test_regress/t/t_virtual_interface_param.v @@ -14,8 +14,8 @@ module t; m #(.p(2)) m_i (); initial begin - virtual b_if#(2) vif = m_i.b; - int y = m_i.b.x; + virtual b_if #(2) vif = m_i.b; + int y = m_i.b.x; if (vif.x != 2) $stop; if (y != 2) $stop; diff --git a/test_regress/t/t_virtual_interface_param_bind.v b/test_regress/t/t_virtual_interface_param_bind.v index 9b70d86cc..483166c3a 100644 --- a/test_regress/t/t_virtual_interface_param_bind.v +++ b/test_regress/t/t_virtual_interface_param_bind.v @@ -15,7 +15,7 @@ module t; typedef virtual b_if vif_t; initial begin vif_t vif = t.m_i.if_bind; - int y = t.m_i.if_bind.x; + int y = t.m_i.if_bind.x; if (vif.x != 1) $stop; if (y != 1) $stop; diff --git a/test_regress/t/t_vlt_legacy.v b/test_regress/t/t_vlt_legacy.v index a547e7fb4..8b389fdf1 100644 --- a/test_regress/t/t_vlt_legacy.v +++ b/test_regress/t/t_vlt_legacy.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 module t ( - input clk /*verilator clock_enable*/ + input clk /*verilator clock_enable*/ ); initial $finish; endmodule diff --git a/test_regress/t/t_vlt_timing.v b/test_regress/t/t_vlt_timing.v index e95e1ec99..8472ae6b5 100644 --- a/test_regress/t/t_vlt_timing.v +++ b/test_regress/t/t_vlt_timing.v @@ -12,7 +12,7 @@ module t; int x; // verilator timing_off #1 - fork @e1; @e2; join; + fork @e1; @e2; join @e1 wait(x == 4) x = #1 8; @@ -34,6 +34,6 @@ module t; initial #2 ->e2; - initial #3 $stop; // timeout - initial #1 @(e1, e2) #1 $stop; // timeout + initial #3 $stop; // timeout + initial #1 @(e1, e2) #1 $stop; // timeout endmodule diff --git a/test_regress/t/t_wire_trireg_unsup.out b/test_regress/t/t_wire_trireg_unsup.out index a7ed87914..de967eaa7 100644 --- a/test_regress/t/t_wire_trireg_unsup.out +++ b/test_regress/t/t_wire_trireg_unsup.out @@ -1,24 +1,24 @@ -%Error-UNSUPPORTED: t/t_wire_trireg_unsup.v:11:4: Unsupported: trireg - 11 | trireg unsup; - | ^~~~~~ +%Error-UNSUPPORTED: t/t_wire_trireg_unsup.v:11:3: Unsupported: trireg + 11 | trireg unsup; + | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_wire_trireg_unsup.v:12:4: Unsupported: trireg - 12 | trireg (small) unsup_s; - | ^~~~~~ -%Error: t/t_wire_trireg_unsup.v:12:12: syntax error, unexpected STRENGTH keyword (strong1/etc) - 12 | trireg (small) unsup_s; - | ^~~~~ +%Error-UNSUPPORTED: t/t_wire_trireg_unsup.v:12:3: Unsupported: trireg + 12 | trireg (small) unsup_s; + | ^~~~~~ +%Error: t/t_wire_trireg_unsup.v:12:11: syntax error, unexpected STRENGTH keyword (strong1/etc) + 12 | trireg (small) unsup_s; + | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error-UNSUPPORTED: t/t_wire_trireg_unsup.v:13:4: Unsupported: trireg - 13 | trireg (medium) unsup_m; - | ^~~~~~ -%Error: t/t_wire_trireg_unsup.v:13:12: syntax error, unexpected STRENGTH keyword (strong1/etc) - 13 | trireg (medium) unsup_m; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_wire_trireg_unsup.v:14:4: Unsupported: trireg - 14 | trireg (large) unsup_l; - | ^~~~~~ -%Error: t/t_wire_trireg_unsup.v:14:12: syntax error, unexpected STRENGTH keyword (strong1/etc) - 14 | trireg (large) unsup_l; - | ^~~~~ +%Error-UNSUPPORTED: t/t_wire_trireg_unsup.v:13:3: Unsupported: trireg + 13 | trireg (medium) unsup_m; + | ^~~~~~ +%Error: t/t_wire_trireg_unsup.v:13:11: syntax error, unexpected STRENGTH keyword (strong1/etc) + 13 | trireg (medium) unsup_m; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_wire_trireg_unsup.v:14:3: Unsupported: trireg + 14 | trireg (large) unsup_l; + | ^~~~~~ +%Error: t/t_wire_trireg_unsup.v:14:11: syntax error, unexpected STRENGTH keyword (strong1/etc) + 14 | trireg (large) unsup_l; + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_wire_trireg_unsup.v b/test_regress/t/t_wire_trireg_unsup.v index b704552b4..dd5086be6 100644 --- a/test_regress/t/t_wire_trireg_unsup.v +++ b/test_regress/t/t_wire_trireg_unsup.v @@ -8,9 +8,9 @@ module t; - trireg unsup; - trireg (small) unsup_s; - trireg (medium) unsup_m; - trireg (large) unsup_l; + trireg unsup; + trireg (small) unsup_s; + trireg (medium) unsup_m; + trireg (large) unsup_l; endmodule diff --git a/test_regress/t/t_x_rand_stability.v b/test_regress/t/t_x_rand_stability.v index 5642333f8..5c47811ee 100644 --- a/test_regress/t/t_x_rand_stability.v +++ b/test_regress/t/t_x_rand_stability.v @@ -5,12 +5,10 @@ // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; int cyc = 0; logic [31:0] uninitialized; diff --git a/test_regress/t/t_xml_debugcheck.py b/test_regress/t/t_xml_debugcheck.py index 463ac7aeb..000592728 100755 --- a/test_regress/t/t_xml_debugcheck.py +++ b/test_regress/t/t_xml_debugcheck.py @@ -14,7 +14,7 @@ test.top_filename = "t/t_enum_type_methods.v" out_filename = test.obj_dir + "/V" + test.name + ".xml" -test.compile(verilator_flags2=['--no-std', '--debug-check', '--flatten'], +test.compile(verilator_flags2=['--no-std', '--debug-check', '--flatten', '--inline-cfuncs', '0'], verilator_make_gmake=False, make_top_shell=False, make_main=False)