From 2dc0053ea48e720450e8b5fc8327c7587856d1cd Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 8 Dec 2022 07:23:53 -0500
Subject: [PATCH] Tests: rename

---
 test_regress/t/{t_timing_bug3781.pl => t_timing_dlyassign.pl} | 0
 test_regress/t/{t_timing_bug3781.v => t_timing_dlyassign.v}   | 1 +
 2 files changed, 1 insertion(+)
 rename test_regress/t/{t_timing_bug3781.pl => t_timing_dlyassign.pl} (100%)
 rename test_regress/t/{t_timing_bug3781.v => t_timing_dlyassign.v} (98%)

diff --git a/test_regress/t/t_timing_bug3781.pl b/test_regress/t/t_timing_dlyassign.pl
similarity index 100%
rename from test_regress/t/t_timing_bug3781.pl
rename to test_regress/t/t_timing_dlyassign.pl
diff --git a/test_regress/t/t_timing_bug3781.v b/test_regress/t/t_timing_dlyassign.v
similarity index 98%
rename from test_regress/t/t_timing_bug3781.v
rename to test_regress/t/t_timing_dlyassign.v
index aca002652..42cefffce 100644
--- a/test_regress/t/t_timing_bug3781.v
+++ b/test_regress/t/t_timing_dlyassign.v
@@ -4,6 +4,7 @@
 // any use, without warranty, 2022 by Antmicro Ltd.
 // SPDX-License-Identifier: CC0-1.0
 
+// bug3781
 module t;
     logic clk;
     logic [7:0] data;