diff --git a/test_regress/t/t_timing_bug3781.pl b/test_regress/t/t_timing_dlyassign.pl
similarity index 100%
rename from test_regress/t/t_timing_bug3781.pl
rename to test_regress/t/t_timing_dlyassign.pl
diff --git a/test_regress/t/t_timing_bug3781.v b/test_regress/t/t_timing_dlyassign.v
similarity index 98%
rename from test_regress/t/t_timing_bug3781.v
rename to test_regress/t/t_timing_dlyassign.v
index aca002652..42cefffce 100644
--- a/test_regress/t/t_timing_bug3781.v
+++ b/test_regress/t/t_timing_dlyassign.v
@@ -4,6 +4,7 @@
 // any use, without warranty, 2022 by Antmicro Ltd.
 // SPDX-License-Identifier: CC0-1.0
 
+// bug3781
 module t;
     logic clk;
     logic [7:0] data;