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sv2v
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SystemVerilog to Verilog conversion
5 Commits 1 Branch 14 Tags 3.4 MiB
Haskell 48.1%
SystemVerilog 26.2%
Verilog 16.4%
Yacc 6.4%
Shell 2.5%
Other 0.3%
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Zachary Snow fb8f088bad updated LICENSE to reflect fork 2019-02-08 16:51:20 -05:00
Data Basic build setup! 2019-02-08 01:09:33 -05:00
Language Basic build setup! 2019-02-08 01:09:33 -05:00
.gitignore Fix compiliation; trailing whitespace; added .gitignore 2019-02-07 23:58:34 -05:00
LICENSE updated LICENSE to reflect fork 2019-02-08 16:51:20 -05:00
Makefile Basic build setup! 2019-02-08 01:09:33 -05:00
Setup.hs Initial commit: fork of https://github.com/tomahawkins/verilog 2019-02-07 23:49:12 -05:00
sv2v.cabal Basic build setup! 2019-02-08 01:09:33 -05:00
sv2v.hs Basic build setup! 2019-02-08 01:09:33 -05:00