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Fix compiliation; trailing whitespace; added .gitignore

This commit is contained in:
Zachary Snow 2019-02-07 23:58:34 -05:00
parent 363ca80af2
commit bfafea5dd8
8 changed files with 261 additions and 252 deletions
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2
.gitignore vendored Normal file
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@ -0,0 +1,2 @@
*.swp
dist/

4
Data/BitVec.hs
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@ -8,6 +8,7 @@ module Data.BitVec
) where
import Data.Bits
import Data.Semigroup
data BitVec = BitVec Int Integer deriving (Show, Eq)
@ -39,6 +40,9 @@ instance Bits BitVec where
isSigned _ = False
popCount (BitVec _ v) = popCount v
instance Semigroup BitVec where
(<>) = mappend
instance Monoid BitVec where
mempty = BitVec 0 0
mappend (BitVec w1 v1) (BitVec w2 v2) = BitVec (w1 + w2) (shiftL v1 w2 .|. v2)

37
Language/Verilog/AST.hs
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@ -17,6 +17,7 @@ module Language.Verilog.AST
import Data.Bits
import Data.List
import Data.Maybe
import Data.Semigroup
import Text.Printf
import Data.BitVec
@ -75,7 +76,7 @@ instance Show ModuleItem where
showAssign a = case a of
Nothing -> ""
Just a -> printf " = %s" $ show a
showRange :: Maybe Range -> String
showRange Nothing = ""
showRange (Just (h, l)) = printf "[%s:%s] " (showExprConst h) (showExprConst l)
@ -117,24 +118,24 @@ instance Show UniOp where
USub -> "-"
data BinOp
= And
| Or
| BWAnd
| BWXor
| BWOr
| Mul
| Div
| Mod
| Add
| Sub
= And
| Or
| BWAnd
| BWXor
| BWOr
| Mul
| Div
| Mod
| Add
| Sub
| ShiftL
| ShiftR
| Eq
| Ne
| Lt
| Le
| Gt
| Ge
| Eq
| Ne
| Lt
| Le
| Gt
| Ge
deriving Eq
instance Show BinOp where
@ -210,6 +211,8 @@ instance Bits Expr where
bit = error "Not supported: bit"
popCount = error "Not supported: popCount"
instance Semigroup Expr where
(<>) = mappend
instance Monoid Expr where
mempty = 0

2
Language/Verilog/Parser/Lex.x
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@ -38,7 +38,7 @@ $decimalDigit = [0-9]
@binaryNumber = @size? @binaryBase @binaryValue
@octalNumber = @size? @octalBase @octalValue
@hexNumber = @size? @hexBase @hexValue
-- $exp = [eE]
-- $sign = [\+\-]
-- @realNumber = unsignedNumber "." unsignedNumber | unsignedNumber ( "." unsignedNumber)? exp sign? unsignedNumber

4
Language/Verilog/Parser/Parse.y
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@ -221,7 +221,7 @@ LHS :: { LHS }
| "{" LHSs "}" { LHSConcat $2 }
LHSs :: { [LHS] }
: LHS { [$1] }
: LHS { [$1] }
| LHSs "," LHS { $1 ++ [$3] }
Sense :: { Sense }
@ -356,7 +356,7 @@ toNumber = number . tokenString
where
w = takeWhile (/= '\'') a
b = dropWhile (/= '\'') a
f a
f a
| isPrefixOf "'d" a = read $ drop 2 a
| isPrefixOf "'h" a = read $ "0x" ++ drop 2 a
| isPrefixOf "'b" a = foldl (\ n b -> shiftL n 1 .|. (if b == '1' then 1 else 0)) 0 (drop 2 a)

8
Language/Verilog/Parser/Preprocess.hs
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@ -16,7 +16,7 @@ uncomment file a = uncomment a
removeEOL a = case a of
"" -> ""
'\n' : rest -> '\n' : uncomment rest
'\n' : rest -> '\n' : uncomment rest
'\t' : rest -> '\t' : removeEOL rest
_ : rest -> ' ' : removeEOL rest
@ -42,7 +42,7 @@ uncomment file a = uncomment a
'\\' : '"' : rest -> "\\\"" ++ ignoreString rest
a : rest -> a : ignoreString rest
-- | A simple `define preprocessor.
-- | A simple `define preprocessor.
preprocess :: [(String, String)] -> FilePath -> String -> String
preprocess env file content = unlines $ pp True [] env $ lines $ uncomment file content
where
@ -50,8 +50,8 @@ preprocess env file content = unlines $ pp True [] env $ lines $ uncomment file
pp _ _ _ [] = []
pp on stack env (a : rest) = case words a of
"`define" : name : value -> "" : pp on stack (if on then (name, ppLine env $ unwords value) : env else env) rest
"`ifdef" : name : _ -> "" : pp (on && (elem name $ fst $ unzip env)) (on : stack) env rest
"`ifndef" : name : _ -> "" : pp (on && (notElem name $ fst $ unzip env)) (on : stack) env rest
"`ifdef" : name : _ -> "" : pp (on && (elem name $ fst $ unzip env)) (on : stack) env rest
"`ifndef" : name : _ -> "" : pp (on && (notElem name $ fst $ unzip env)) (on : stack) env rest
"`else" : _
| not $ null stack -> "" : pp (head stack && not on) stack env rest
| otherwise -> error $ "`else without associated `ifdef/`ifndef: " ++ file

452
Language/Verilog/Parser/Tokens.hs
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@ -18,232 +18,232 @@ instance Show Position where
data Token = Token TokenName String Position deriving (Show, Eq)
data TokenName
= KW_alias
| KW_always
| KW_always_comb
| KW_always_ff
| KW_always_latch
| KW_and
| KW_assert
| KW_assign
| KW_assume
| KW_automatic
| KW_before
| KW_begin
| KW_bind
| KW_bins
| KW_binsof
| KW_bit
| KW_break
| KW_buf
| KW_bufif0
| KW_bufif1
| KW_byte
| KW_case
| KW_casex
| KW_casez
| KW_cell
| KW_chandle
| KW_class
| KW_clocking
| KW_cmos
| KW_config
| KW_const
| KW_constraint
| KW_context
| KW_continue
| KW_cover
| KW_covergroup
| KW_coverpoint
| KW_cross
| KW_deassign
| KW_default
| KW_defparam
| KW_design
| KW_disable
| KW_dist
| KW_do
| KW_edge
| KW_else
| KW_end
| KW_endcase
| KW_endclass
| KW_endclocking
| KW_endconfig
| KW_endfunction
| KW_endgenerate
| KW_endgroup
| KW_endinterface
| KW_endmodule
| KW_endpackage
| KW_endprimitive
| KW_endprogram
| KW_endproperty
| KW_endspecify
| KW_endsequence
| KW_endtable
| KW_endtask
| KW_enum
| KW_event
| KW_expect
| KW_export
| KW_extends
| KW_extern
| KW_final
| KW_first_match
| KW_for
| KW_force
| KW_foreach
| KW_forever
| KW_fork
| KW_forkjoin
| KW_function
| KW_function_prototype
| KW_generate
| KW_genvar
| KW_highz0
| KW_highz1
| KW_if
| KW_iff
| KW_ifnone
| KW_ignore_bins
| KW_illegal_bins
| KW_import
| KW_incdir
| KW_include
| KW_initial
| KW_inout
| KW_input
| KW_inside
| KW_instance
| KW_int
| KW_integer
| KW_interface
| KW_intersect
| KW_join
| KW_join_any
| KW_join_none
| KW_large
| KW_liblist
| KW_library
| KW_local
| KW_localparam
| KW_logic
| KW_longint
| KW_macromodule
| KW_matches
| KW_medium
| KW_modport
| KW_module
| KW_nand
| KW_negedge
| KW_new
| KW_nmos
| KW_nor
| KW_noshowcancelled
| KW_not
| KW_notif0
| KW_notif1
| KW_null
| KW_option
| KW_or
| KW_output
| KW_package
| KW_packed
| KW_parameter
| KW_pathpulse_dollar
| KW_pmos
| KW_posedge
| KW_primitive
| KW_priority
| KW_program
| KW_property
| KW_protected
| KW_pull0
| KW_pull1
| KW_pulldown
| KW_pullup
| KW_pulsestyle_onevent
| KW_pulsestyle_ondetect
| KW_pure
| KW_rand
| KW_randc
| KW_randcase
| KW_randsequence
| KW_rcmos
| KW_real
| KW_realtime
| KW_ref
| KW_reg
| KW_release
| KW_repeat
| KW_return
| KW_rnmos
| KW_rpmos
| KW_rtran
| KW_rtranif0
| KW_rtranif1
| KW_scalared
| KW_sequence
| KW_shortint
| KW_shortreal
| KW_showcancelled
| KW_signed
| KW_small
| KW_solve
| KW_specify
| KW_specparam
| KW_static
| KW_strength0
| KW_strength1
| KW_string
| KW_strong0
| KW_strong1
| KW_struct
| KW_super
| KW_supply0
| KW_supply1
| KW_table
| KW_tagged
| KW_task
| KW_this
| KW_throughout
| KW_time
| KW_timeprecision
| KW_timeunit
| KW_tran
| KW_tranif0
| KW_tranif1
| KW_tri
| KW_tri0
| KW_tri1
| KW_triand
| KW_trior
| KW_trireg
| KW_type
| KW_typedef
| KW_type_option
| KW_union
| KW_unique
| KW_unsigned
| KW_use
| KW_var
| KW_vectored
| KW_virtual
| KW_void
| KW_wait
| KW_wait_order
| KW_wand
| KW_weak0
| KW_weak1
| KW_while
| KW_wildcard
| KW_wire
| KW_with
| KW_within
| KW_wor
| KW_xnor
| KW_xor
= KW_alias
| KW_always
| KW_always_comb
| KW_always_ff
| KW_always_latch
| KW_and
| KW_assert
| KW_assign
| KW_assume
| KW_automatic
| KW_before
| KW_begin
| KW_bind
| KW_bins
| KW_binsof
| KW_bit
| KW_break
| KW_buf
| KW_bufif0
| KW_bufif1
| KW_byte
| KW_case
| KW_casex
| KW_casez
| KW_cell
| KW_chandle
| KW_class
| KW_clocking
| KW_cmos
| KW_config
| KW_const
| KW_constraint
| KW_context
| KW_continue
| KW_cover
| KW_covergroup
| KW_coverpoint
| KW_cross
| KW_deassign
| KW_default
| KW_defparam
| KW_design
| KW_disable
| KW_dist
| KW_do
| KW_edge
| KW_else
| KW_end
| KW_endcase
| KW_endclass
| KW_endclocking
| KW_endconfig
| KW_endfunction
| KW_endgenerate
| KW_endgroup
| KW_endinterface
| KW_endmodule
| KW_endpackage
| KW_endprimitive
| KW_endprogram
| KW_endproperty
| KW_endspecify
| KW_endsequence
| KW_endtable
| KW_endtask
| KW_enum
| KW_event
| KW_expect
| KW_export
| KW_extends
| KW_extern
| KW_final
| KW_first_match
| KW_for
| KW_force
| KW_foreach
| KW_forever
| KW_fork
| KW_forkjoin
| KW_function
| KW_function_prototype
| KW_generate
| KW_genvar
| KW_highz0
| KW_highz1
| KW_if
| KW_iff
| KW_ifnone
| KW_ignore_bins
| KW_illegal_bins
| KW_import
| KW_incdir
| KW_include
| KW_initial
| KW_inout
| KW_input
| KW_inside
| KW_instance
| KW_int
| KW_integer
| KW_interface
| KW_intersect
| KW_join
| KW_join_any
| KW_join_none
| KW_large
| KW_liblist
| KW_library
| KW_local
| KW_localparam
| KW_logic
| KW_longint
| KW_macromodule
| KW_matches
| KW_medium
| KW_modport
| KW_module
| KW_nand
| KW_negedge
| KW_new
| KW_nmos
| KW_nor
| KW_noshowcancelled
| KW_not
| KW_notif0
| KW_notif1
| KW_null
| KW_option
| KW_or
| KW_output
| KW_package
| KW_packed
| KW_parameter
| KW_pathpulse_dollar
| KW_pmos
| KW_posedge
| KW_primitive
| KW_priority
| KW_program
| KW_property
| KW_protected
| KW_pull0
| KW_pull1
| KW_pulldown
| KW_pullup
| KW_pulsestyle_onevent
| KW_pulsestyle_ondetect
| KW_pure
| KW_rand
| KW_randc
| KW_randcase
| KW_randsequence
| KW_rcmos
| KW_real
| KW_realtime
| KW_ref
| KW_reg
| KW_release
| KW_repeat
| KW_return
| KW_rnmos
| KW_rpmos
| KW_rtran
| KW_rtranif0
| KW_rtranif1
| KW_scalared
| KW_sequence
| KW_shortint
| KW_shortreal
| KW_showcancelled
| KW_signed
| KW_small
| KW_solve
| KW_specify
| KW_specparam
| KW_static
| KW_strength0
| KW_strength1
| KW_string
| KW_strong0
| KW_strong1
| KW_struct
| KW_super
| KW_supply0
| KW_supply1
| KW_table
| KW_tagged
| KW_task
| KW_this
| KW_throughout
| KW_time
| KW_timeprecision
| KW_timeunit
| KW_tran
| KW_tranif0
| KW_tranif1
| KW_tri
| KW_tri0
| KW_tri1
| KW_triand
| KW_trior
| KW_trireg
| KW_type
| KW_typedef
| KW_type_option
| KW_union
| KW_unique
| KW_unsigned
| KW_use
| KW_var
| KW_vectored
| KW_virtual
| KW_void
| KW_wait
| KW_wait_order
| KW_wand
| KW_weak0
| KW_weak1
| KW_while
| KW_wildcard
| KW_wire
| KW_with
| KW_within
| KW_wor
| KW_xnor
| KW_xor
| Id_simple
| Id_escaped
| Id_system

4
Language/Verilog/Simulator.hs
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@ -56,7 +56,7 @@ getSignalId netlist path = case lookup path paths' of
Nothing -> Nothing
Just i -> Just $ Id i
where
paths = [ (paths, id) | Reg id _ paths _ <- netlist ] ++ [ (paths, id) | Var id _ paths _ <- netlist ]
paths = [ (paths, id) | Reg id _ paths _ <- netlist ] ++ [ (paths, id) | Var id _ paths _ <- netlist ]
paths' = [ (path, id) | (paths, id) <- paths, path <- paths ]
type Memory = IOArray Int BitVec
@ -75,7 +75,7 @@ memory netlist
initialize :: Netlist BlackBoxInit -> Memory -> IORef (Maybe VCDHandle) -> Maybe FilePath -> IORef (IO ()) -> IORef (IO ()) -> IO (Maybe SimResponse)
initialize netlist memory vcd file sample step = do
close vcd sample step
mapM_ (initializeNet memory) netlist
mapM_ (initializeNet memory) netlist
case file of
Nothing -> return ()
Just file -> do