SystemVerilog to Verilog conversion

conversionsystemverilogverilogyosys

Zachary Snow 8bd58e961f Basic build setup!		2019-02-08 01:09:33 -05:00
Data	Basic build setup!	2019-02-08 01:09:33 -05:00
Language	Basic build setup!	2019-02-08 01:09:33 -05:00
.gitignore	Fix compiliation; trailing whitespace; added .gitignore	2019-02-07 23:58:34 -05:00
LICENSE	Initial commit: fork of https://github.com/tomahawkins/verilog	2019-02-07 23:49:12 -05:00
Makefile	Basic build setup!	2019-02-08 01:09:33 -05:00
Setup.hs	Initial commit: fork of https://github.com/tomahawkins/verilog	2019-02-07 23:49:12 -05:00
sv2v.cabal	Basic build setup!	2019-02-08 01:09:33 -05:00
sv2v.hs	Basic build setup!	2019-02-08 01:09:33 -05:00