sv2v/src/Language/SystemVerilog/AST
Zachary Snow 7ea5b60d0b support for inside case statements 2019-12-21 20:41:19 -05:00
..
Attr.hs surprisingly non-disgusting addition of attribute instances to module items and statements 2019-03-26 01:54:16 -04:00
Decl.hs major array pack and flatten update (closes #48) 2019-09-26 23:11:59 -04:00
Description.hs pass through downstream compiler directives 2019-10-10 20:53:49 -04:00
Expr.hs support for inside case statements 2019-12-21 20:41:19 -05:00
GenItem.hs cleanup case representation 2019-12-01 23:25:33 -05:00
LHS.hs language support for LHS streaming operators 2019-09-02 20:46:35 -04:00
ModuleItem.hs language support for final blocks 2019-10-31 20:39:11 -04:00
ModuleItem.hs-boot final major round of splitting and cleanup in the SystemVerilog module 2019-04-03 20:24:09 -04:00
Op.hs support and conversion for -> and <-> 2019-09-15 13:55:40 -04:00
ShowHelp.hs cleaner AST output 2019-10-11 22:38:47 -04:00
Stmt.hs support for inside case statements 2019-12-21 20:41:19 -05:00
Type.hs handle adding packed dimensions to byte, shortint, and longint 2019-10-01 00:03:07 -04:00
Type.hs-boot starting work to clean up and segment AST 2019-03-22 19:39:28 -04:00