mirror of https://github.com/zachjs/sv2v.git
cleaner AST output
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@ -228,6 +228,7 @@ traverseSinglyNestedStmtsM fullMapper = cs
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where
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cs (StmtAttr a stmt) = fullMapper stmt >>= return . StmtAttr a
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cs (Block _ "" [] []) = return Null
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cs (Block _ "" [] [stmt]) = fullMapper stmt
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cs (Block Seq name decls stmts) = do
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stmts' <- mapM fullMapper stmts
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return $ Block Seq name decls $ concatMap explode stmts'
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@ -72,7 +72,7 @@ instance Show Expr where
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show (Repeat e l ) = printf "{%s {%s}}" (show e) (commas $ map show l)
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show (Concat l ) = printf "{%s}" (commas $ map show l)
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show (Stream o e l) = printf "{%s %s%s}" (show o) (show e) (show $ Concat l)
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show (UniOp a b ) = printf "(%s %s)" (show a) (show b)
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show (UniOp o e ) = printf "%s%s" (show o) (show e)
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show (BinOp o a b) = printf "(%s %s %s)" (show a) (show o) (show b)
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show (Dot e n ) = printf "%s.%s" (show e) n
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show (Mux c a b) = printf "(%s ? %s : %s)" (show c) (show a) (show b)
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@ -54,3 +54,7 @@ instance Show GenItem where
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show (GenModuleItem item) = show item
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type GenCase = ([Expr], GenItem)
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showCase :: (Show x, Show y) => ([x], y) -> String
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showCase (a, b) = printf "%s: %s" (commas $ map show a) (show b)
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@ -12,12 +12,10 @@ module Language.SystemVerilog.AST.ShowHelp
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, unlines'
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, commas
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, indentedParenList
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, showCase
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, showEither
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) where
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import Data.List (intercalate)
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import Text.Printf (printf)
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showPad :: Show t => t -> String
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showPad x =
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@ -51,9 +49,6 @@ indentedParenList [] = "()"
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indentedParenList [x] = "(" ++ x ++ ")"
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indentedParenList l = "(\n" ++ (indent $ intercalate ",\n" l) ++ "\n)"
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showCase :: (Show x, Show y) => ([x], y) -> String
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showCase (a, b) = printf "%s: %s" (commas $ map show a) (show b)
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showEither :: (Show a, Show b) => Either a b -> String
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showEither (Left v) = show v
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showEither (Right v) = show v
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@ -25,7 +25,7 @@ module Language.SystemVerilog.AST.Stmt
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import Text.Printf (printf)
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import Language.SystemVerilog.AST.ShowHelp (commas, indent, unlines', showPad, showCase)
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import Language.SystemVerilog.AST.ShowHelp (commas, indent, unlines', showPad)
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import Language.SystemVerilog.AST.Attr (Attr)
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import Language.SystemVerilog.AST.Decl (Decl)
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import Language.SystemVerilog.AST.Expr (Expr, Args(..))
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@ -93,16 +93,32 @@ instance Show Stmt where
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show (DoWhile e s) = printf "do %s while (%s);" (show s) (show e)
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show (Forever s ) = printf "forever %s" (show s)
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show (Foreach x i s) = printf "foreach (%s [ %s ]) %s" x (commas $ map (maybe "" id) i) (show s)
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show (If u a b Null) = printf "%sif (%s) %s" (maybe "" showPad u) (show a) (show b)
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show (If u a b c ) = printf "%sif (%s) %s\nelse %s" (maybe "" showPad u) (show a) (show b) (show c)
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show (If u a b Null) = printf "%sif (%s)%s" (maybe "" showPad u) (show a) (showBranch b)
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show (If u a b c ) = printf "%sif (%s)%s\nelse%s" (maybe "" showPad u) (show a) (showBranch b) (showElseBranch c)
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show (Return e ) = printf "return %s;" (show e)
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show (Timing t s ) = printf "%s %s" (show t) (show s)
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show (Timing t s ) = printf "%s%s" (show t) (showShortBranch s)
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show (Trigger b x) = printf "->%s %s;" (if b then "" else ">") x
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show (Assertion a) = show a
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show (Continue ) = "continue;"
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show (Break ) = "break;"
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show (Null ) = ";"
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showBranch :: Stmt -> String
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showBranch (block @ Block{}) = ' ' : show block
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showBranch stmt = '\n' : (indent $ show stmt)
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showElseBranch :: Stmt -> String
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showElseBranch (stmt @ If{}) = ' ' : show stmt
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showElseBranch stmt = showBranch stmt
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showShortBranch :: Stmt -> String
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showShortBranch (stmt @ AsgnBlk{}) = ' ' : show stmt
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showShortBranch (stmt @ Asgn{}) = ' ' : show stmt
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showShortBranch stmt = showBranch stmt
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showCase :: ([Expr], Stmt) -> String
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showCase (a, b) = printf "%s:%s" (commas $ map show a) (showShortBranch b)
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data CaseKW
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= CaseN
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| CaseZ
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