mirror of https://github.com/zachjs/sv2v.git
handle adding packed dimensions to byte, shortint, and longint
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@ -17,20 +17,6 @@ convert =
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traverseTypes convertType
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convertType :: Type -> Type
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convertType (IntegerAtom TInt sg) = baseType sg Signed 32
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convertType (IntegerAtom TShortint sg) = baseType sg Signed 16
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convertType (IntegerAtom TLongint sg) = baseType sg Signed 64
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convertType (IntegerAtom TByte sg) = baseType sg Unspecified 8
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convertType (IntegerAtom kw sg) = elaborateIntegerAtom $ IntegerAtom kw sg
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convertType (IntegerVector TBit sg rs) = IntegerVector TLogic sg rs
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convertType other = other
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-- makes a integer "compatible" type with the given signing, base signing and
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-- size; if not unspecified, the first signing overrides the second
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baseType :: Signing -> Signing -> Int -> Type
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baseType sgOverride sgBase size =
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IntegerVector TReg sg [(Number hi, Number "0")]
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where
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hi = show (size - 1)
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sg = if sgOverride /= Unspecified
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then sgOverride
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else sgBase
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@ -18,6 +18,7 @@ module Language.SystemVerilog.AST.Type
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, NonIntegerType (..)
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, typeRanges
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, nullRange
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, elaborateIntegerAtom
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) where
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import Text.Printf (printf)
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@ -98,12 +99,32 @@ nullRange t [(Number "0", Number "0")] = t
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nullRange (IntegerAtom TInteger sg) rs =
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-- integer arrays are allowed in SystemVerilog but not in Verilog
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IntegerVector TBit sg (rs ++ [(Number "31", Number "0")])
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nullRange (IntegerAtom TInt sg) rs =
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-- int arrays are allowed in SystemVerilog but not in Verilog
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IntegerVector TBit sg (rs ++ [(Number "31", Number "0")])
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nullRange t rs =
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error $ "non-vector type " ++ show t ++
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" cannot have a packed dimesions:" ++ show rs
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nullRange t rs1 =
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if t == t'
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then error $ "non-vector type " ++ show t ++
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" cannot have packed dimesions:" ++ show rs1
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else tf $ rs1 ++ rs2
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where
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t' = elaborateIntegerAtom t
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(tf, rs2) = typeRanges t'
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elaborateIntegerAtom :: Type -> Type
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elaborateIntegerAtom (IntegerAtom TInt sg) = baseIntType sg Signed 32
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elaborateIntegerAtom (IntegerAtom TShortint sg) = baseIntType sg Signed 16
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elaborateIntegerAtom (IntegerAtom TLongint sg) = baseIntType sg Signed 64
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elaborateIntegerAtom (IntegerAtom TByte sg) = baseIntType sg Unspecified 8
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elaborateIntegerAtom other = other
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-- makes a integer "compatible" type with the given signing, base signing and
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-- size; if not unspecified, the first signing overrides the second
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baseIntType :: Signing -> Signing -> Int -> Type
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baseIntType sgOverride sgBase size =
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IntegerVector TReg sg [(Number hi, Number "0")]
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where
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hi = show (size - 1)
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sg = if sgOverride /= Unspecified
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then sgOverride
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else sgBase
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data Signing
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= Unspecified
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