Zachary Snow 767b05cd06 arguably cleaner Show output for AST modules

2019-02-10 17:59:41 -05:00

Data

Basic build setup!

2019-02-08 01:09:33 -05:00

Language

arguably cleaner Show output for AST modules

2019-02-10 17:59:41 -05:00

.gitignore

updated build procedure

2019-02-08 16:51:32 -05:00

LICENSE

updated LICENSE to reflect fork

2019-02-08 16:51:20 -05:00

Makefile

updated build procedure

2019-02-08 16:51:32 -05:00

Setup.hs

Initial commit: fork of https://github.com/tomahawkins/verilog

2019-02-07 23:49:12 -05:00

sv2v.cabal

updated build procedure

2019-02-08 16:51:32 -05:00

sv2v.hs

support for reduction ops, non-named/non-identifier module instantiation arguments, always @*

2019-02-10 17:47:11 -05:00

S

Description

SystemVerilog to Verilog conversion

conversionsystemverilogverilogyosys

BSD-3-Clause

3.3 MiB

Languages

Haskell 48.1%

SystemVerilog 26.3%

Verilog 16.4%

Yacc 6.4%

Shell 2.4%

Other 0.3%