This website requires JavaScript.
Explore
Help
Sign In
luke
/
sv2v
Watch
1
Star
0
Fork
0
mirror of
https://github.com/zachjs/sv2v.git
synced
2026-09-03 16:39:06 +02:00
Code
Issues
Packages
Projects
Releases
Wiki
Activity
32
Commits
2
Branches
14
Tags
5fae85e6cd1f9ff4ef5b60828592eb46213ef042
T
Code
Clone
HTTPS
Tea CLI
Open with VS Code
Open with VSCodium
Open with Intellij IDEA
Zachary Snow
5fae85e6cd
very preliminary support for typedefs
2019-02-18 03:59:17 -05:00
Convert
very preliminary support for typedefs
2019-02-18 03:59:17 -05:00
Language
very preliminary support for typedefs
2019-02-18 03:59:17 -05:00
.gitignore
switch to using stack
2019-02-11 23:48:49 -05:00
Convert.hs
very preliminary support for typedefs
2019-02-18 03:59:17 -05:00
LICENSE
updated LICENSE to reflect fork
2019-02-08 16:51:20 -05:00
Makefile
switch to using stack
2019-02-11 23:48:49 -05:00
Setup.hs
Initial commit: fork of
https://github.com/tomahawkins/verilog
2019-02-07 23:49:12 -05:00
stack.yaml
switch to using stack
2019-02-11 23:48:49 -05:00
sv2v.cabal
very preliminary support for typedefs
2019-02-18 03:59:17 -05:00
sv2v.hs
added logic to module items; toying with initial Conversion
2019-02-17 23:39:01 -05:00
S
Description
SystemVerilog to Verilog conversion
conversion
systemverilog
verilog
yosys
BSD-3-Clause
3.3
MiB
Languages
Haskell
48.1%
SystemVerilog
26.3%
Verilog
16.4%
Yacc
6.4%
Shell
2.4%
Other
0.3%
