mirror of https://github.com/zachjs/sv2v.git
34 lines
649 B
Haskell
34 lines
649 B
Haskell
{- sv2v
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- Author: Zachary Snow <zach@zachjs.com>
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-
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- SystemVerilog to Verilog conversion
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-}
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module Convert (convert) where
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import Language.SystemVerilog.AST
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import qualified Convert.AlwaysKW
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import qualified Convert.Logic
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import qualified Convert.Typedef
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type Phase = AST -> AST
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phases :: [Phase]
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phases =
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[ Convert.AlwaysKW.convert
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, Convert.Logic.convert
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, Convert.Typedef.convert
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]
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run :: Phase
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run = foldr (.) id phases
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convert :: Phase
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convert descriptions =
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let descriptions' = run descriptions
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in
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if descriptions == descriptions'
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then descriptions
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else convert descriptions'
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