SystemVerilog to Verilog conversion

conversionsystemverilogverilogyosys

Zachary Snow 5b336439fb cleanup of port decl parsing		2019-02-09 18:35:15 -05:00
Data	Basic build setup!	2019-02-08 01:09:33 -05:00
Language	cleanup of port decl parsing	2019-02-09 18:35:15 -05:00
.gitignore	updated build procedure	2019-02-08 16:51:32 -05:00
LICENSE	updated LICENSE to reflect fork	2019-02-08 16:51:20 -05:00
Makefile	updated build procedure	2019-02-08 16:51:32 -05:00
Setup.hs	Initial commit: fork of https://github.com/tomahawkins/verilog	2019-02-07 23:49:12 -05:00
sv2v.cabal	updated build procedure	2019-02-08 16:51:32 -05:00
sv2v.hs	hacky, preliminary support for port declarations in module header	2019-02-09 17:35:31 -05:00