sv2v/test/core/struct_integer.v

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Verilog
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2020-08-12 00:37:21 +02:00
module top;
reg [32*3-1:0] s = {32'd1, 32'd2, 32'd3};
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initial #1 $display("%b %b %b %b", s, s[64+:32], s[32+:32], s[0+:32]);
endmodule