convert logics with initial values to regs, not wires

src/Convert/Logic.hs

@@ -172,7 +172,7 @@ rewriteDeclM (Variable d t x a e) = do
             let location = map accessName accesses
             usedAsReg <- lift $ gets $ Set.member location
             blockLogic <- withinProcedureM
-            if usedAsReg || blockLogic
+            if usedAsReg || blockLogic || e /= Nil
                 then do
                     let dir = if d == Inout then Output else d
                     return (dir, IntegerVector TReg sg rs)

test/core/const.v

@@ -1,5 +1,5 @@
 module top;
     integer w = 11;
-    wire [63:0] x = { 32'd11, 32'd12 };
+    reg [63:0] x = { 32'd11, 32'd12 };
     initial $display("%b %b %b %b", w, x, x[32+:32], x[0+:32]);
 endmodule

test/core/foreach.v

@@ -1,5 +1,5 @@
 module top;
-    wire [7:0] foo = {2'b10,2'b01,2'b11,2'b00};
+    reg [7:0] foo = {2'b10,2'b01,2'b11,2'b00};
     initial begin : f
         integer x;
         for (x = 0; x <= 3; x = x + 1)

test/core/inside_expr.v

@@ -49,8 +49,7 @@ module top;
         $display("test1: %b %b", 3'b0z1, test1(3'b0z1));
     end
 
-    wire [0:2][31:0] arr;
-    assign arr = { 32'd60, 32'd61, 32'd63 };
+    reg [0:2][31:0] arr = { 32'd60, 32'd61, 32'd63 };
     function test2;
         input integer inp;
         integer i;

test/core/interface_nested.v

@@ -1,5 +1,5 @@
 module top;
-    wire x = 1;
+    reg x = 1;
     generate
         if (1) begin : f
             wire x;

test/core/interface_task.v

@@ -3,8 +3,8 @@ module top;
         input reg [31:0] i;
         $display("I x(%0d)", i);
     endtask
-    wire [31:0] w = 31;
-    wire [31:0] y = 42;
+    reg [31:0] w = 31;
+    reg [31:0] y = 42;
     task x;
         input reg [31:0] a, b;
         $display("x('{%0d, %0d})", a, b);

test/core/large_mux.v

@@ -1,7 +1,7 @@
 module top;
     parameter SVO_MODE = "768x576";
     `include "large_mux.vh"
-    wire [31:0] DOUBLE_SVO_HOR_PIXELS = 2 * SVO_HOR_PIXELS;
+    reg [31:0] DOUBLE_SVO_HOR_PIXELS = 2 * SVO_HOR_PIXELS;
     initial begin
         $display("%s", SVO_MODE);
         $display("%d", SVO_HOR_PIXELS);

test/core/struct_integer.v

@@ -1,4 +1,4 @@
 module top;
-    wire [32*3-1:0] s = {32'd1, 32'd2, 32'd3};
+    reg [32*3-1:0] s = {32'd1, 32'd2, 32'd3};
     initial #1 $display("%b %b %b %b", s, s[64+:32], s[32+:32], s[0+:32]);
 endmodule

test/core/struct_unit_array.v

@@ -1,4 +1,4 @@
 module top;
-    wire [2:0] s = 3'b110;
+    reg [2:0] s = 3'b110;
     initial #1 $display("%b", s);
 endmodule

test/core/unbased_unsized.v

@@ -1,5 +1,5 @@
 `define TEST(value) \
-    wire [63:0] val_``value = {64{1'b``value}}; \
+    reg [63:0] val_``value = {64{1'b``value}}; \
     initial $display(`"'value -> %b (%0d) %b (%0d)`", \
         val_``value, $bits(val_``value), \
         1'b``value, $bits(1'b``value) \