mirror of https://github.com/zachjs/sv2v.git
5 lines
144 B
Verilog
5 lines
144 B
Verilog
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module top;
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wire [32*3-1:0] s = {32'd1, 32'd2, 32'd3};
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initial #1 $display("%b %b %b %b", s, s[64+:32], s[32+:32], s[0+:32]);
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endmodule
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