sv2v/test/core/struct_array.v

12 lines
317 B
Verilog
Raw Permalink Normal View History

module Unpacker(in, select, a, b, c);
parameter WIDTH = 8;
input wire [WIDTH*7-1:0] in;
input wire [$clog2(WIDTH)-1:0] select;
output wire a;
output wire [3:0] b;
output wire [1:0] c;
2024-02-12 01:04:48 +01:00
assign a = in[select*7+6];
assign b = in[select*7+5-:4];
assign c = in[select*7+1-:2];
endmodule