partially bump iverilog

.github/workflows/main.yaml

@@ -41,7 +41,7 @@ jobs:
           - macOS-11
     needs: build
     env:
-      IVERILOG_REF: 999bcb69353db5b38aa348f466e51274a6fb99e2
+      IVERILOG_REF: 8ee1d56e1acbc130aa63da3c8ef0d535a551cf28
     steps:
       - uses: actions/checkout@v1
       - name: Install Dependencies (macOS)

test/core/array.sv

@@ -5,7 +5,9 @@ endmodule
 module top;
     logic [1:0] a [3];
     logic [1:0] b [3];
+    logic start;
     always_comb a = b;
+    initial start = 0;
 
     logic x;
     logic [1:0] c [3];

test/core/array.v

@@ -5,7 +5,12 @@ endmodule
 module top;
     reg [5:0] a;
     wire [5:0] b;
-    always @(*) a = b;
+    reg start;
+    always @(*) begin
+        if (start);
+        a = b;
+    end
+    initial start = 0;
 
     reg x;
     wire [5:0] c;

test/core/package_enum_3.sv

@@ -9,10 +9,12 @@ module top;
     import foo_pkg::*;
     wire [2:0] test;
 
+    reg start;
     always_comb begin
         case (test)
             AccessAck: $display("Ack");
             default  : $display("default");
         endcase
     end
+    initial start = 0;
 endmodule

test/core/package_enum_3.v

@@ -2,10 +2,13 @@ module top;
     localparam [2:0] AccessAck = 3'd0;
     wire [2:0] test;
 
+    reg start;
     always @(*) begin
+        if (start);
         case (test)
             AccessAck: $display("Ack");
             default  : $display("default");
         endcase
     end
+    initial start = 0;
 endmodule

test/core/stream.sv

@@ -126,9 +126,9 @@ module top;
 
     logic [31:0] mux1, mux2, mux3, mux4, mux5, mux6;
     initial $monitor("%b %b %b %b %b %b", mux1, mux2, mux3, mux4, mux5, mux6);
-    assign mux1 = i ? {<<1 {in}} : 32'b0;
-    assign mux2 = i ? {>>1 {in}} : {<<1 {in}};
-    assign mux3 = i ? {<<1 {in}} : {<<1 {m}};
+    assign #10 mux1 = i ? {<<1 {in}} : 32'b0;
+    assign #20 mux2 = i ? {>>1 {in}} : {<<1 {in}};
+    assign #30 mux3 = i ? {<<1 {in}} : {<<1 {m}};
     always @* begin
         mux4 = i ? {<<1 {in}} : 32'b0;
         mux5 = i ? {>>1 {in}} : {<<1 {in}};

test/core/stream.v

@@ -151,9 +151,9 @@ module top;
     wire [31:0] mux1, mux2, mux3;
     reg [31:0] mux4, mux5, mux6;
     initial $monitor("%b %b %b %b %b %b", mux1, mux2, mux3, mux4, mux5, mux6);
-    assign mux1 = i ? reverse(in) : 32'b0;
-    assign mux2 = i ? in << 8 : reverse(in);
-    assign mux3 = i ? reverse(in) : reverse(m);
+    assign #10 mux1 = i ? reverse(in) : 32'b0;
+    assign #20 mux2 = i ? in << 8 : reverse(in);
+    assign #30 mux3 = i ? reverse(in) : reverse(m);
     always @* begin
         mux4 = i ? reverse(in) : 32'b0;
         mux5 = i ? in << 8 : reverse(in);

test/core/struct_array.v

@@ -5,9 +5,7 @@ module Unpacker(in, select, a, b, c);
     output wire a;
     output wire [3:0] b;
     output wire [1:0] c;
-    wire [6:0] p;
-    assign p = in[select*7+:7];
-    assign a = p[6:6];
-    assign b = p[5:2];
-    assign c = p[1:0];
+    assign a = in[select*7+6];
+    assign b = in[select*7+5-:4];
+    assign c = in[select*7+1-:2];
 endmodule