mirror of https://github.com/zachjs/sv2v.git
12 lines
317 B
Verilog
12 lines
317 B
Verilog
module Unpacker(in, select, a, b, c);
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parameter WIDTH = 8;
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input wire [WIDTH*7-1:0] in;
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input wire [$clog2(WIDTH)-1:0] select;
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output wire a;
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output wire [3:0] b;
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output wire [1:0] c;
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assign a = in[select*7+6];
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assign b = in[select*7+5-:4];
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assign c = in[select*7+1-:2];
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endmodule
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