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Dr Jonathan Richard Robert Kimmitt 1c63972bd2 005-tilegrid: propagate SING bits for HP-only LIOB18 / LIOI columns 
propagate_IOB_SING and propagate_IOI_SING walk each IO column from a
parent IOB/IOI tile down to the SING half-tiles at the column endpoints
and alias the parent's CLB_IO_CLK bits into both halves (offset=0 for
the bottom SING, offset=99 for the top SING).  The parent-type
allowlists were missing the HP-bank L-column types:

    propagate_IOB_SING: ["LIOB33", "RIOB33", "RIOB18"]    # LIOB18 missing
    propagate_IOI_SING: ["LIOI3",  "RIOI3",  "RIOI"]      # LIOI   missing

On artix7 / kintex7 the leftmost HP column doesn't exist as a parent
LIOB18 / LIOI in the tilegrid, so the omission was latent.  On
virtex7 VX (HP-only) both LIOB18 and RIOB18 columns exist, and the
gap surfaces as half the SING IOB / IOI tiles (the L-column ones)
having empty bits in tilegrid.json:

    LIOB18_SING:  0/14 with bits  ->  14/14
    RIOB18_SING: 14/14 (unchanged)
    LIOI_SING:    0/14 with bits  ->  14/14
    RIOI_SING:   14/14 (unchanged)

Add the missing types.  Cross-checked against iob18's own measured
parent bases (e.g. LIOB18_X81Y2 -> 0x00421000 lines up with the
propagated LIOB18_SING_X81Y1 base 0x00421000 offset=0 and Y51 offset=99).

Also de-wire the iob18_sing sub-fuzzer from TILEGRID_TDB_DEPENDENCIES:
SING tiles aren't independently addressed (they share the parent IOB's
base with a word-offset variant), and half of iob18_sing's tdb entries
land at an unaligned frame (offset+1) that add_tdb's frame-alignment
assertion would reject anyway.  The build rule stays so the fuzzer can
be invoked manually as a Vivado-measurement guard for the propagation.

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
 		2026-05-30 16:02:48 +01:00
..
000-init-db add support for the kintex high performance banks 2024-01-08 14:00:20 +07:00
001-part-yaml Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
005-tilegrid 005-tilegrid: propagate SING bits for HP-only LIOB18 / LIOI columns 2026-05-30 16:02:48 +01:00
007-timing Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
010-clb-lutinit Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
011-clb-ffconfig Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
012-clb-n5ffmux Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
013-clb-ncy0 Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
014-clb-ffsrcemux Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
015-clb-nffmux Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
016-clb-noutmux Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
017-clb-precyinit Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
018-clb-ram virtex7: enable 018-clb-ram (LUTRAM/SRL) — was misdiagnosed as Vivado-version wall 2026-05-27 14:27:08 +01:00
019-clb-ndi1mux Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
025-bram-config Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
026-bram-data Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
027-bram36-config Fix new BRAM36 features. 2020-10-28 13:44:49 -07:00
028-fifo-config Add license headers to tcl files 2020-05-26 07:33:12 -07:00
029-bram-fifo-config Add license headers to tcl files 2020-05-26 07:33:12 -07:00
030-iob Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
030-iob18 virtex7: HP-bank glue codified end-to-end + open-flow validation 2026-05-29 10:13:53 +01:00
031-cmt-mmcm mmcm, pll: use full name for MMCM, and PLL sites 2021-02-26 17:04:03 +01:00
032-cmt-pll mmcm, pll: use full name for MMCM, and PLL sites 2021-02-26 17:04:03 +01:00
033-mon-xadc Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
034-cmt-pll-pips virtex7: HP-bank glue codified end-to-end + open-flow validation 2026-05-29 10:13:53 +01:00
034b-cmt-mmcm-pips virtex7: HP-bank glue codified end-to-end + open-flow validation 2026-05-29 10:13:53 +01:00
035-iob-ilogic Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
035a-iob-idelay Add license headers to tcl files 2020-05-26 07:33:12 -07:00
035a-iob18-idelay virtex7: HP-bank glue codified end-to-end + open-flow validation 2026-05-29 10:13:53 +01:00
035a-iob18-odelay virtex7: HP-bank glue codified end-to-end + open-flow validation 2026-05-29 10:13:53 +01:00
035b-iob-iserdes Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
036-iob-ologic Fix duplicate feature ZBUF and TDDR.SRUSED. 2020-10-02 19:08:36 -07:00
036-iob18-ologic fix obvious issues in 035a-iob18-idelay/bits.dbf and 036-iob18-ologic/bits.dbf 2024-01-08 14:00:20 +07:00
037-iob-pips Add license headers to tcl files 2020-05-26 07:33:12 -07:00
037-iob18-pips virtex7: HP-bank glue codified end-to-end + open-flow validation 2026-05-29 10:13:53 +01:00
038-cfg virtex7: HP-bank glue codified end-to-end + open-flow validation 2026-05-29 10:13:53 +01:00
038-cfg-startup add basic fuzzer for STARTUPE2 2024-01-08 14:00:21 +07:00
039-hclk-config virtex7: HP-bank glue codified end-to-end + open-flow validation 2026-05-29 10:13:53 +01:00
040-clk-hrow-config Add license headers to tcl files 2020-05-26 07:33:12 -07:00
041-clk-hrow-pips virtex7: HP-bank glue codified end-to-end + open-flow validation 2026-05-29 10:13:53 +01:00
042-clk-bufg-config Add license headers to tcl files 2020-05-26 07:33:12 -07:00
043-clk-rebuf-pips virtex7: HP-bank glue codified end-to-end + open-flow validation 2026-05-29 10:13:53 +01:00
044-clk-bufg-pips virtex7: HP-bank glue codified end-to-end + open-flow validation 2026-05-29 10:13:53 +01:00
045-hclk-cmt-pips virtex7: HP-bank glue codified end-to-end + open-flow validation 2026-05-29 10:13:53 +01:00
046-clk-bufg-muxed-pips virtex7: HP-bank glue codified end-to-end + open-flow validation 2026-05-29 10:13:53 +01:00
047-hclk-ioi-pips Add license headers to tcl files 2020-05-26 07:33:12 -07:00
047-hclk-ioi18-pips update copyright year for io*18 fuzzers 2024-01-08 14:00:20 +07:00
047a-hclk-idelayctrl-pips virtex7: HP-bank glue codified end-to-end + open-flow validation 2026-05-29 10:13:53 +01:00
048-int-piplist Add licensing header to Makefiles 2020-05-26 07:33:12 -07:00
049-int-imux-gfan Add license headers to tcl files 2020-05-26 07:33:12 -07:00
050-pip-seed Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
051-pip-imuxlout-bypalts Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
052-pip-clkin Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
053-pip-ctrlin virtex7: 053-pip-ctrlin / 055-pip-gnd — 2*N tile reservation 2026-05-27 14:27:08 +01:00
054-pip-fan-alt Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
055-pip-gnd virtex7: 053-pip-ctrlin / 055-pip-gnd — 2*N tile reservation 2026-05-27 14:27:08 +01:00
056-pip-rem Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
057-pip-bi Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
058-pip-hclk Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
059-pip-byp-bounce Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
060-bram-cascades Add license headers to tcl files 2020-05-26 07:33:12 -07:00
061-pcie-conf cells_data: add clock information on ports.json 2021-03-26 13:47:38 +01:00
062-pcie-int-pips 062-pcie-int-pips: add fuzzer to document PCIE_INT_INTERFACE DELAY PIPs 2021-02-05 19:18:35 +01:00
063-gtp-common-conf cells_data: add clock information on ports.json 2021-03-26 13:47:38 +01:00
063-gtx-common-conf fix 063-gtx-common-conf/attrs.json 2025-04-03 04:52:08 +07:00
064-gtp-channel-conf 064-gtp-channel: fix width of [TR]XOUT_DIV attributes 2021-03-26 13:47:38 +01:00
064-gtx-channel-conf fix 064-gtx-channel-conf/attrs.json 2025-04-02 05:38:24 +07:00
065-gtp-common-pips fuzzers: fix clean in parts fuzzers 2022-03-03 12:50:33 +01:00
065b-gtp-common-pips 065b-gtp-pips: increase iter timeout 2022-03-07 14:57:31 +01:00
066-gtp-int-pips 066-gtp-int-pips: add fuzzer for GTP_INT_INTERFACE DELAY PIPs 2021-02-04 12:35:00 +01:00
071-ppips Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
072-ordered_wires fuzzers: fix clean in parts fuzzers 2022-03-03 12:50:33 +01:00
073-get_counts fuzzers: fix clean in parts fuzzers 2022-03-03 12:50:33 +01:00
074-dump_all virtex7: HP-bank glue codified end-to-end + open-flow validation 2026-05-29 10:13:53 +01:00
075-pins fuzzers: fix clean in parts fuzzers 2022-03-03 12:50:33 +01:00
076-ps7 Add license headers to tcl files 2020-05-26 07:33:12 -07:00
100-dsp-mskpat Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
101-dsp-pips 101-dsp-pips: solve DSP-related PIPs 2021-02-15 13:15:44 +01:00
piplist Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
.gitignore fuzzers: consolidate common gitignores 2018-12-19 18:56:32 -08:00
Makefile virtex7: enable 018-clb-ram (LUTRAM/SRL) — was misdiagnosed as Vivado-version wall 2026-05-27 14:27:08 +01:00
clb.mk 012-clb-d5ff: increased specimens and added c argument 2019-02-15 16:16:41 +01:00
clb_ext.mk Added a makefile which allows to fuzz features for both SLICEM and SLICEL but separate them during database merge. 2019-07-10 15:06:58 +02:00
fuzzer.mk Add left and right clock pips. 2019-02-11 09:59:09 -08:00
int_create_empty_db.sh Add licensing header to bash scripts 2020-05-26 07:33:12 -07:00
int_generate.py Add licensing header to fuzzers' python scripts 2020-05-26 07:33:12 -07:00
int_loop.mk fuzzers: Fix including Makefiles. 2019-01-31 18:24:33 -08:00
int_loop.sh pip fuzzers: enable part specific builds 2021-02-02 19:35:23 +01:00
int_loop_check.py Add licensing header to fuzzers' python scripts 2020-05-26 07:33:12 -07:00
int_maketodo.py Add initial MMCM feature and PIP support. 2020-10-08 17:44:42 -07:00
pip_list.mk Fix 048 not using correct directory. 2019-03-12 10:47:27 -07:00
pip_loop.mk pip fuzzers: enable part specific builds 2021-02-02 19:35:23 +01:00
reseg.sh Add licensing header to bash scripts 2020-05-26 07:33:12 -07:00
run_fuzzer.py run_fuzzer: replace semicolon with dash in stderr and stdout names 2022-02-03 18:14:58 +01:00