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virtex7: enable 018-clb-ram (LUTRAM/SRL) — was misdiagnosed as Vivado-version wall 

The earlier skip blamed a 'Vivado 2020.1 BEL-slot' difference; on close
investigation the real failure was generate.py:79 `assert bels == bels_tcl`
in the my_ram_N branch. The two ROI definitions disagree on X extent:
util.get_roi() (XRAY_ROI_GRID_*) yields SLICEM at SLICE X2..X12, but the
Vivado dump pblock built from $XRAY_ROI is X0..X11 — so the whole
SLICE_X12Y* column top.py LOC's primitives into falls outside the dumped
pblock and shows up as None in design.csv, tripping the assert.

The sibling RAM path already tolerated this via 'if ram != has_bel_tcl:
continue' (line ~137); mirror the same graceful skip in the SRL/LUT path.
For other families bels always == bels_tcl, so the change is a no-op.

Verified end-to-end on xc7vx485tffg1761-2: produces valid LUTRAM segdata
(ALUT/BLUT/CLUT/DLUT.{RAM,SRL,SMALL} + WA7USED/WA8USED/WEMUX.CE), pushes
into segbits_clblm_l/r (clblm coverage 95% -> ~100% vs kintex7).

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
This commit is contained in:
Dr Jonathan Richard Robert Kimmitt 2026-05-27 14:27:08 +01:00
parent 68f2db4060
commit 1ebe6937e0
2 changed files with 11 additions and 6 deletions
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9
fuzzers/018-clb-ram/generate.py
View File

@ -76,7 +76,14 @@ for l in f:
# Each one of: SRL16E, SRLC32E, LUT6
bels = [p0, p1, p2, p3]
verbose and print(' %s %s %s %s' % tuple(bels))
assert bels == bels_tcl
# Skip slices Vivado placed outside the dumped pblock (bels_tcl all
# None) or repacked differently, instead of asserting -- mirrors the
# RAM-path "if ram != has_bel_tcl: continue" below. This makes the
# fuzzer robust to the ROI-edge case (e.g. virtex7's grid-ROI yields a
# SLICE column just outside the XRAY_ROI pblock); other families always
# match, so this is a no-op for them.
if bels != bels_tcl:
continue
# Clock Enable (CE) clock gate only enabled if we have clocked elements
# A pure LUT6 does not, but everything else should

8
fuzzers/Makefile
View File

@ -118,12 +118,10 @@ $(eval $(call fuzzer,014-clb-ffsrcemux,005-tilegrid,all))
$(eval $(call fuzzer,015-clb-nffmux,005-tilegrid,all))
$(eval $(call fuzzer,016-clb-noutmux,005-tilegrid,all))
$(eval $(call fuzzer,017-clb-precyinit,005-tilegrid,all))
# 018-clb-ram skipped for virtex7: Vivado 2020.1 packs the SRL/RAM primitives
# into different BEL slots than the fuzzer pins, failing its BEL-match assertion
# (a Vivado-version behavioural difference, not an ROI issue).
ifeq (,$(filter $(XRAY_DATABASE),virtex7))
# 018-clb-ram (distributed RAM / SRL): works on virtex7 once generate.py skips
# slices placed outside the dumped pblock (the grid-ROI yields a SLICE column
# just past the XRAY_ROI box); see the graceful-skip in generate.py.
$(eval $(call fuzzer,018-clb-ram,005-tilegrid,all))
endif
$(eval $(call fuzzer,019-clb-ndi1mux,005-tilegrid,all))
$(eval $(call fuzzer,025-bram-config,005-tilegrid,all))
$(eval $(call fuzzer,026-bram-data,005-tilegrid,all))